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GB2548126A - A SiC trench transistor - Google Patents

A SiC trench transistor Download PDF

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Publication number
GB2548126A
GB2548126A GB1604046.1A GB201604046A GB2548126A GB 2548126 A GB2548126 A GB 2548126A GB 201604046 A GB201604046 A GB 201604046A GB 2548126 A GB2548126 A GB 2548126A
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United Kingdom
Prior art keywords
region
transistor
base
trench gate
semiconductor
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Application number
GB1604046.1A
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GB201604046D0 (en
GB2548126B (en
Inventor
Jiang Huaping
Ke Maolong
Deviny Ian
Wei Jin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhuzhou CRRC Times Electric Co Ltd
Dynex Semiconductor Ltd
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Zhuzhou CRRC Times Electric Co Ltd
Dynex Semiconductor Ltd
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Priority to GB1604046.1A priority Critical patent/GB2548126B/en
Publication of GB201604046D0 publication Critical patent/GB201604046D0/en
Publication of GB2548126A publication Critical patent/GB2548126A/en
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Abstract

A wide band-gap high voltage trench transistor comprises a semiconductor substrate 410; a semiconductor drift region of a second conductivity type disposed on the semiconductor substrate 420; a trench gate extending from a surface of the transistor to the semiconductor drift region 460; a body region of a first conductivity type 430 located within the semiconductor drift region and by a side of the trench gate; a source region 440 of the second conductivity type located within the body region and by the side of the trench gate, wherein the trench gate 460 is configured to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region; a source connection 470 placed above and in contact with the source region; a base region 500 of the first conductivity type located within the drift region, and a base connection 490 placed above and in contact with the base region. The base region 500 is located at least partially under the trench gate 460. The base connection 490, which may be electrically connected to the source connection 470, is used for electrically grounding the base region, in order to alleviate electric field crowding in the gate oxide at a bottom corner of the trench gate 465. The wide band gap material may be 3-step cubic SiC, 4-step hexagonal SiC or 6-step hexagonal SiC.

Description

A SiC Trench Transistor
FIELD OF THE INVENTION
This invention relates to a trench power semiconductor transistor, particularly but not exclusively, to a wide band-gap material based trench power semiconductor transistor.
BACKGROUND TO THE INVENTION
One of the well-known problems of silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) is the low effective channel mobility due to high SiC/gate oxide (Si02) interface trap density. Compared to planar MOSFETs, the trench MOSFETs show lower specific on-resistance because of higher channel density and relative higher effective channel mobility. The most important issue of trench MOSFETs is the high electric field at the bottom corner of gate trench under reverse bias, which results in long term gate oxide reliability issues.
To solve this problem, a grounded p-well was introduced at the bottom of the gate trench [1-2]. However, the p-wells were formed using self-aligned implantation and were grounded via neighbour cells. This is not an efficient arrangement as it takes a significant space in the chip area. Furthermore, the p-wells re-introduce a JFET constriction at the bottom end of the MOSFET channel [3] and a relatively high grounding resistance. This is important for ruggedness of the device but is relatively difficult to implement.
An effort was made to solve this problem by references [4-6], in which an additional trench with a p-well formed at the bottom was introduced to reduce the electric field at the bottom corner of gate trench. This arrangement is shown in Fig. 1. However, the electric field in gate oxide at the bottom corner of gate trench is still very high (>3MV/cm). The high electric field is shown in Fig. 2. It is understood that when the electric field is above 3MV/cm, the gate oxide of the transistor is no longer reliable.
Fig. 3 illustrates a prior art Silicon based IGBT proposed by Feng et al [8]. This device also has the problem of the high electric field at the corner of the trench gate.
It is an aim of the present invention to lower the electric field in gate oxide at the bottom corner of trench gate, preferably below 3 MV/cm.
SUMMARY
According to one aspect of the present invention, there is provided a wide band-gap high voltage trench transistor comprising: a semiconductor substrate; a semiconductor drift region of a second conductivity type disposed on the semiconductor substrate; a trench gate extending from a surface of the transistor to the semiconductor drift region; a body region of a first conductivity type, opposite the second conductivity type, located within the semiconductor drift region and by a side of the trench gate; a source region of the second conductivity type located within the body region and by the side of the trench gate, wherein the trench gate is configured to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region; a source connection placed above and in contact with the source region; a base region of the first conductivity type located within the drift region, and a base connection placed above and in contact with the base region, wherein the base region is located at least partially under the trench gate.
The base region and the base connection enable to help reducing electric field at the bottom corner of the trench gate. This is because the base region under the trench helps to shield electric field from the corner of the trench gate. Furthermore, since the base region can be grounded using the base connection, it is efficient in terms of saving area in the wafer.
The source connection and the base connection may be discrete connections. The source connection and the base connection may be electrically connected to one another. The trench gate may be located between the base connection and the source connection. The base connection may be laterally spaced from the trench gate.
The base region may be operatively in contact with the trench gate. The base region generally overlaps with the trench gate region. The base region and trench gate are generally spaced by the gate oxide. The base region may be electrically grounded using the base connection.
The transistor may further comprise a highly doped semiconductor region of the first conductivity type within the body region and adjacent the source region, wherein the source connection is in contact with the highly doped semiconductor region.
The trench gate may comprise a first bottom corner distant from the base connection and a second bottom corner adjacent the base connection. The base region may extend to the first corner of the trench region.
The base region may be off-set from the first corner by a predetermined distance. The predetermined distance may be about 0.5 pm. This distance may be adjusted as per the performance optimisation of the device.
The base region may be vertically spaced from the body region.
The transistor may further comprise a first semiconductor region (or JFET region) of the second conductivity type within the drift region, the first semiconductor region being located underneath the body region and located at least partially at the side of the trench gate. The first semiconductor region may also be at least partially underneath the trench gate.
The first semiconductor region may comprise a higher doping concentration than the drift region and comprises a lower doping concentration than the body region and base region. The first semiconductor region is configured to reduce a junction field effect transistor (JFET) effect during an on-state operation of the transistor. The semiconductor substrate, the source region, the body region and the base region each may comprise a higher doping concentration than the drift region.
The trench gate may be formed using a sidewall spacer technology. The transistor may be a single trench transistor. This means that there is generally only one trench per cell in the transistor.
The drift region, the body region, the source region and the base region may each are epitaxial layers which are doped area formed by an epitaxial growth process. These areas are doped (uniformly) during the epitaxial prcess. These regions are generally not formed by diffusion technique.
The semiconductor substrate may be of the second conductivity type. The transistor may be a metal oxide semiconductor field effect transistor (MOSFET).
The semiconductor substrate may be of the first conductivity type. The transistor may be an insulated gate bipolar transistor (IGBT).
The wide band gap material may comprise one or more of 3-step cubic silicon carbide (3C-SiC), 4-step hexagonal silicon carbide (4H-SiC) and 6-step hexagonal silicon carbide (6H-SiC). Other wide bandgap materials such as gallium nitride or diamond may also be used.
According to a further aspect of the present invention, there is provided a method of manufacturing a wide band-gap high voltage trench transistor, the method comprising: forming a semiconductor substrate; forming a semiconductor drift region of a second conductivity type on the semiconductor substrate; forming a trench gate extending from a surface of the transistor to the semiconductor drift region; forming a body region of a first conductivity type, opposite the second conductivity type, within the semiconductor drift region and by a side of the trench gate; forming a source region of the second conductivity type within the body region and by the side of the trench gate, wherein the trench gate controls charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region: forming a source connection above and in contact with the source region: forming a base region of the first conductivity type within the drift region, and forming a base connection placed above and in contact with the base region, wherein the base region is located at least partially under the trench gate.
The forming of the semiconductor drift region may comprise forming a drift epitaxial layer on a silicon face of an off-axis 4H-SiC substrate.
The method may further comprise forming a first epitaxial layer with a doping concentration of about 5e15cm'^ to 1e17cm'^, wherein the first epitaxial layer is a junction field effect transistor (JFET) region.
The forming of the body region may comprise forming body epitaxial layer comprising doping concentration of about 5e16 cm'^to 1e18cm'^.
The forming of the source region may comprise selectively implanting nitrogen to form the source region.
The forming of the trench gate may comprise etching the source region, body region, and first epitaxial layer to a depth of about 1 pm. Other depths are also possible.
The method may further comprise forming a side wall spacer for an off-set between the base layer and the trench gate.
The forming of the base layer may comprise implanting the base layer followed by oxide removal and activation.
The method may further comprise forming a gate oxide with a thickness of about 50 nm. Other thicknesses are also possible.
The method may further comprise forming a poly silicon side wall spacer.
The method may further comprise depositing an oxide and etching a contact.
The method may further comprise forming an ohmic contact.
The method may further comprise depositing a thick aluminium deposition on a topside of the transistor and depositing tri-metal on a backside of the transistor.
BRIEF DESCRIPTION OF THE DRAWINGS
The present disclosure will be understood more fully from the detailed description that follows and from the accompanying drawings, which however, should not be taken to limit the invention to the specific embodiments shown, but are for explanation and understanding only.
Fig. 1 is a schematic illustration of a prior art transistor;
Fig. 2 illustrates simulated off-state characteristics of the transistor of Fig. 1;
Fig. 3 is a schematic illustration of a further prior art transistor;
Fig. 4 is a schematic illustration of SiC based high voltage transistor according to one embodiment of the present invention;
Fig. 5 illustrates simulated off-state characteristics of the transistor of Fig. 4;
Fig. 6 illustrates a comparison of reverse transfer capacitance between the proposed transistor and the transistor of reference [4]; and
Fig. 7 (a) and Fig. 7 (b) illustrate manufacturing steps of the transistor of Fig. 4.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Fig. 4 illustrates a SiC based high voltage transistor 400 according to one embodiment of the present invention. In this example, the transistor 400 is an n-type transistor. The transistor 400 includes a semiconductor substrate 410. A drain (or collector) contact 405 is placed in contact with the substrate 410. Thus the substrate forms a drain region (or collector) of the transistor. A lightly doped n-type drift region 420 is epitaxially grown or formed on the substrate 410. The drift region 420 can have a doping concentration from about 5e13cm'^ to about 2e16 cm'^, depending on device voltage ratings. The transistor 400 also includes a p-type body region 430 formed within the drift region 420. The transistor 400 includes a trench gate 460. The trench gate 460 incudes a side wall and a surface resulting in a recessed structure. The recessed structure is filled with a polysilicon material 480. A bottom corner 465 is formed where the side wall and surface intersects. The bottom corner 465 is the sensitive area where electric field should be reduced.
In Fig. 4, the body region 430 is formed at a side of the side wall of the trench gate 460. A highly doped n-type source region 440 is formed within the body region 430 and at the same side of the side wall of the trench gate 460. A source Ohmic contact 470 is placed in (direct) contact with the source region 440. The transistor 400 also includes a p+ type region 445 within the body region 430. The p+ type region 445 is adjacent the N+ source region 440. The source connection 470 is also in contact with the p+ region 445 such that n+ source 440 and p+ region 445 are shorted. This arrangement improves Ohmic connection of the device. A p-type base region 500 is formed at least partially underneath the surface of the trench gate 460 within the drift region 420. The base region 500 includes higher doping concentration than the drift region 420. A base connection 490 is also provided in contact with and above the base region 500. In one example, the base connection 490 and source connection 470 are discrete connections. The trench gate structure 460 is generally placed between the base connection 490 and source connection 470. The base connection 490 can be generally spaced from the trench gate 460. The base connection 490 and source connection 470 are electrically connected to one another. The base connection is used to electrically ground the base region 500, which helps to reduce peak electric field at the bottom corner 465 of the trench gate 460.
The doping concentration of the p-type base region 500 is from about 1e17 cm'^ to about 2e19 cm'^. The base region 500 can be extended all the way to the bottom corner 465. Alternatively, the base region 500 can be off-set (or spaced) from the bottom corner 465 of the trench gate 460. In one example, the distance between the bottom corner 465 and the base region 500 can be about 0.5 pm. It would be appreciated that other distances can also be applicable.
In the example of Fig. 4, the drift region 420 also includes an n-type doped region (or the first semiconductor region or the JFET region) 450. The n-type doped region 450 is placed underneath the body region 430 and located at least partially at the side wall of the trench gate 460 and located at least partially underneath the surface of the trench gate 465. The n-type doped region 450 is configured to remove the JFET effect. When there is no n-type doped region 450 in the drift region 420, in the on-state of the transistor 400, current would spread around the drift region which would increase the on-state resistance. This would result in a JFET effect within the transistor. With the doped region 450 underneath the body region 430, the current does not spread as much in the drift region and therefore improves the on-resistance performance during on-state of the transistor and reduces (removes) the JFET effect from the transistor. The doping concentration of the doped region 450 is from about 5e15 cm'^ to about 1e17 cm'^.
The transistor 400 can be a MOSFET or an IGBT. For a MOSFET, the substrate 410 generally has an n doping type. For an IGBT, the substrate 410 generally has a p doping type. The material for the transistor 400 can be any wide bandgap material, such as 3C-SiC, 4H-SiC and/or 6H-SiC.
The proposed device structure, shown in Fig. 4, features the trench gate 460 which is formed by sidewall spacer technology after the trench is formed and a grounded p-base region formed at the trench bottom. The grounded p-base region 500 reduces the electric field in the gate oxide at the bottom corner 465 of the trench gate 460 to lower than 3 MV/cm. An offset (e.g. 0.5 pm) between the P-base region 500 and the gate trench corner 465 is optionally introduced to optimise the on-state performance.
To demonstrate effectiveness of the present invention, the performances of the transistor of the present invention are compared to the double trench MOSFET of reference [4] by simulations. For both of the structures of the present invention and reference [4], the following parameters are used in the simulations. In this example, the doping concentration of drift epitaxial layer is 7.5e15 cm'^. The gate oxide thickness is 50 nm and cell pitch is 6 pm. The thickness of drift epitaxial layer and depth of the trenches are 7 pm and 1.0 pm, respectively. The doped region (JFET removal/reduction region) doping is adjusted to be with the depth of about 1.5 pm and doping concentration of about 4e16 cm'^. The channel mobility is set to be about 11 cm^/V-s.
The performances of the present invention and reference [4] devices are comparatively shown in Table I.
Table I. Comparatively shown key performances.
Fig. 5 shows the simulation results during an off-state for the transistor according to one embodiment of the present invention. As shown in Fig. 5 (in inset), the potential lines at the corner of the trench gate is relatively relaxed (or less dense) compared to the potential lines in the inset of Fig. 2. The less dense potential lines result in a relatively less peak electric field. For example, it is observed from the simulation results (not shown here), the peak electric field of the structure at the corner of the gate trench bottom under 600 V is no more than about 2.2 MV/cm, which is much lower than that of reference [4] (3.8 MV/cm). This is because the P-base region 500 at the bottom of the trench gate shields the electric field from the trench corner 465.
Fig. 6 illustrates a comparison of reverse transfer capacitance between the proposed transistor and the transistor of reference [4], The reverse transfer capacitance of the proposed structure is represented as graph 610 and the reverse transfer capacitance of reference [4] is represented as graph 620. As can be seen from Fig. 6, the reverse transfer capacitance of the proposed device at Vds = 600 V is only 43% of that of that of reference [4].
Fig. 7 (a) and Fig. 7 (b) illustrate manufacturing steps of the transistor of Fig. 4.
In step (a), form an n-drift epitaxial layer on the Silicon-face of the 4° off-axis 4H-SiC substrate (wafer).
In step (b), form an n-type epitaxial layer (or the JFET region) with doping concentration of 5e15 cm ^to 1e17 cm'®. The JFET region is generally formed using implantation process, particularly (but not limiting to) by ion implantation followed by activation process.
In step (c), form p-type epitaxial body layer (or the body region) with doping concentration of lei7 to 2e19 cm'^.
In step (d), selectively perform nitrogen implantation to form n+ source region and aluminium implantation to form P+ region. The doping concentration of the source region is about 1e19 cm'^ to 5e20 cm'^. The doping concentration of the p+ region is about 5e18 to 1e20 cm'^.
In step (e), perform gate trench etching in a depth of about 1 pm.
In step (f), form silicon dioxide (Si02) sidewall spacer for offset between the P-base and gate trench.
In step (g), perform P-base implantation followed with oxide removing and activation. The doping concentration of the P-base region is generally about 1e17 cm'^to 2e19 cm'^.
In step (h), perform gate oxide growth to a thickness of about 50 nm.
In step (i), form poly silicon sidewall spacer using sidewall spacer technology.
In step 0, perform oxide deposition and contact etching.
In step (k), perform ohmic contact formation.
In step (I), deposit thick Al on the topside of the transistor and tri-metal on the backside of the transistor.
It will also be appreciated that terms such as "top" and "bottom", "above" and "below", "lateral" and "vertical", and “under” and “over”, “front” and “behind”, “underlying”, etc. may be used in this specification by convention and that no particular physical orientation of the device as a whole is implied.
It will be noted that the term “first conductivity type” can refer to a p-type doping polarity and the term “second conductivity” can refer to a n-type doping polarity. However, these terms are not restrictive. It will be appreciated that all doping polarities mentioned above could be reversed, the resulting devices still being in accordance with the present invention. It will be appreciated that the source (emitter), drain (collector) and gate could be arranged to be out-of-plane or to be differently aligned so that the direction of the carriers is not exactly as described above, the resulting devices still being in accordance with the present invention.
Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.
References: [1] Tan, Jian, J. A. Cooper Jr, and Mr R. Melloch. "High-voltage accumulation-layer UMOSFET's in 4H-SiC." Electron Device Letters, IEEE 19.12 (1998): 487-489.
[2] Tanaka, Ryo, et al. "Impact of grounding the bottom oxide protection layer on the short-circuit ruggedness of 4H-SiC trench MOSFETs." Power Semiconductor Devices & IC's (ISPSD), 2014 IEEE 26th International Symposium on. IEEE, 2014.
[3] T. Kimoto, J.A. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices, and Applications, IEEE Wiley, Singapore, 2014.
[4] Nakamura, T., Y. Nakano, M. Aketa, R. Nakamura, S. Mitani, H. Sakairi, and Y. Yokotsuji. "High performance SiC trench devices with ultra-low ron." In 2011 International Electron Devices Meeting. 2011.
[5] http://www.semiconductof-todav.com/news items/2015/iun/rohm 04061 S.shtml “Rohm starts mass production of first trench-type SiC MOSFET”, 2015.
[6] US7910439, Super Self-Aligned Trench MOSFET Devices, Methods, and Systems, 2011 [7] Dethard Peters, Processing issues in SiC devices technology. Tutorial of ICSCRM 2015, 2015.
[8] Feng, Hao, Wentao Yang, Yuichi Onozawa, Takashi Yoshimura, Akira Tamenori, and Johnny Sin. "A New Fin P-body Insulated Gate Bipolar Transistor with Low Miller Capacitance." Electron Device Letter, (2015).

Claims (40)

CLAIMS:
1. A wide band-gap high voltage trench transistor comprising: a semiconductor substrate; a semiconductor drift region of a second conductivity type disposed on the semiconductor substrate; a trench gate extending from a surface of the transistor to the semiconductor drift region; a body region of a first conductivity type, opposite the second conductivity type, located within the semiconductor drift region and by a side of the trench gate; a source region of the second conductivity type located within the body region and by the side of the trench gate, wherein the trench gate is configured to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region; a source connection placed above and in contact with the source region; a base region of the first conductivity type located within the drift region, and a base connection placed above and in contact with the base region, wherein the base region is located at least partially under the trench gate.
2. A transistor according to claim 1, wherein the source connection and the base connection are discrete connections.
3. A transistor according to claim 1 or 2, wherein the source connection and the base connection are electrically connected to one another.
4. A transistor according to any preceding claim, wherein the trench gate is located between the base connection and the source connection.
5. A transistor according to any preceding claim, wherein the base connection is laterally spaced from the trench gate.
6. A transistor according to any preceding claim, wherein the base region is operatively in contact with the trench gate.
7. A transistor according to any preceding claim, wherein the base region is electrically grounded using the base connection.
8. A transistor according to any preceding claim, wherein the trench gate comprises a first bottom corner distant from the base connection and a second bottom corner adjacent the base connection.
9. A transistor according to claim 8, wherein the base region extends to the first corner of the trench region.
10. A transistor according to claim 8, wherein the base region is off-set from the first corner by a predetermined distance.
11. A transistor according to 10, wherein the predetermined distance is about 0.5 pm.
12. A transistor according to any preceding claim, wherein the base region is vertically spaced from the body region.
13. A transistor according to any preceding claim, further comprising a first semiconductor region of the second conductivity type within the drift region, the first semiconductor region being located underneath the body region and located at least partially at the side of the trench gate.
14. A transistor according to claim 13, wherein the first semiconductor region comprises a higher doping concentration than the drift region and comprises a lower doping concentration than the body region and base region.
15. A transistor according to claim 13 or 14, wherein the first semiconductor region is configured to reduce a junction field effect transistor (JFET) effect during an on-state operation of the transistor.
16. A transistor according to any preceding claim, wherein the semiconductor substrate, the source region, the body region and the base region each comprise a higher doping concentration than the drift region.
17. A transistor according to any preceding claim, wherein the trench gate is formed using a sidewall spacer technology.
18. A transistor according to any preceding claim, wherein the transistor is a single trench transistor.
19. A transistor according to any preceding claim, wherein the drift region, the body region, the source region and the base region each are epitaxial layers which are doped during an epitaxial growth process.
20. A transistor according to any preceding claim, wherein the semiconductor substrate is of the second conductivity type.
21. A transistor according to claim 20, wherein the transistor is a metal oxide semiconductor field effect transistor (MOSFET).
22. A transistor according to any one of claims 1 to 19, wherein the semiconductor substrate is of the first conductivity type.
23. A transistor according to claim 22, wherein the transistor is an insulated gate bipolar transistor (IGBT)
24. A transistor according to any preceding claim, wherein the wide band gap material comprises one or more of 3-step cubic silicon carbide (3C-SiC), 4-step hexagonal silicon carbide (4H-SiC) and 6-step hexagonal silicon carbide (6H-SiC).
25. A transistor according to any preceding claim, further comprising a highly doped semiconductor region of the first conductivity type within the body region and adjacent the source region, wherein the source connection is in contact with the highly doped semiconductor region.
26. A method of manufacturing a wide band-gap high voltage trench transistor, the method comprising: forming a semiconductor substrate; forming a semiconductor drift region of a second conductivity type on the semiconductor substrate; forming a trench gate extending from a surface of the transistor to the semiconductor drift region; forming a body region of a first conductivity type, opposite the second conductivity type, within the semiconductor drift region and by a side of the trench gate; forming a source region of the second conductivity type within the body region and by the side of the trench gate, wherein the trench gate controls charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region; forming a source connection above and in contact with the source region; forming a base region of the first conductivity type within the drift region, and forming a base connection placed above and in contact with the base region, wherein the base region is located at least partially under the trench gate.
27. A method according to claim 26, wherein forming the semiconductor drift region comprises forming a drift epitaxy on a silicon face of an off-axis 4H-SiC substrate.
28. A method according to claim 27, further comprising forming a first epitaxial layer with a doping concentration of about 5e15 cm'^ to 1e17 cm'^, wherein the first epitaxial layer is a junction field effect transistor (JFET) region.
29. A method according to claim 28, wherein forming the body region comprises forming body epitaxial layer comprising doping concentration of about 5e16cm’^ to 1e18cm·^.
30. A method according to claim 29, wherein forming the source region comprises selectively implanting nitrogen to form the source region.
31. A method according claim 30, further comprising forming a highly doped region of the first conductivity type adjacent the source region, wherein the highly doped region comprises doping concentration of about 5e18 cm'^ to 1e20 cm'^.
32. A method according to claim 31, wherein forming the trench gate comprises etching the source region, body region, and first epitaxial layer to a depth of about 1 pm.
33. A method according to claim 32, further comprising forming a side wall spacer for an off-set between the base layer and the trench gate.
34. A method according to claim 33, wherein forming the base layer comprises implanting the base layer followed by oxide removal and activation.
35. A method according to claim 34, further comprising forming a gate oxide with a thickness of about 50 nm.
36. A method according to claim 35, further comprising forming a poly silicon side wall spacer.
37. A method according to claim 36, further comprising depositing an oxide and etching a contact.
38. A method according to claim 37, further comprising forming an ohmic contact.
39. A method according to claim 38, further comprising depositing a thick aluminium deposition on a topside of the transistor and depositing tri-metal on a backside of the transistor.
40. A wide band-gap high voltage trench transistor and a method for manufacturing the wide band-gap high voltage trench transistor, substantially as hereinbefore described with reference to and as illustrated, in the accompanying drawings.
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