GB2491186A - A combined analogue and digital interface for the envelope path of an envelope-tracking amplifier - Google Patents
A combined analogue and digital interface for the envelope path of an envelope-tracking amplifier Download PDFInfo
- Publication number
- GB2491186A GB2491186A GB1108969.5A GB201108969A GB2491186A GB 2491186 A GB2491186 A GB 2491186A GB 201108969 A GB201108969 A GB 201108969A GB 2491186 A GB2491186 A GB 2491186A
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- United Kingdom
- Prior art keywords
- digital
- signal
- analogue
- envelope signal
- envelope
- Prior art date
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- 238000003199 nucleic acid amplification method Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 17
- 238000001914 filtration Methods 0.000 claims description 5
- 230000003111 delayed effect Effects 0.000 description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 3
- 238000010295 mobile communication Methods 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
- H03F1/0244—Stepped control
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
- H03F1/0216—Continuous control
- H03F1/0222—Continuous control by using a signal derived from the input signal
- H03F1/0227—Continuous control by using a signal derived from the input signal using supply converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/102—A non-specified detector of a signal envelope being used in an amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/321—Use of a microprocessor in an amplifier circuit or its control circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/351—Pulse width modulation being used in an amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/511—Many discrete supply voltages or currents or voltage levels can be chosen by a control signal in an IC-block amplifier circuit
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
A baseband controller 228 receives a digital envelope signal 110 and provides digital 234 and analogue 244 output signals to modulated power supply 246. An asynchronous pulse width modulator 206 provides a digital signal 234 to select one of set of voltages for output from the switched mode power supply 214. The combiner 220 provides a supply to the RF amplifier 142 under control of error amplifier 216 which receives an analogue version of the digital envelope signal from DAC 212. The implementation of the controller 230 in the digital domain reduces power consumption and provides predictable and repeatable control. The digital processor 202 provides a desired frequency response for the switched supply path.
Description
ENVELOPE PATH PROCESSING FOR ENVELOPE TRACKING AMPLIFICATION
STAGE
BACKGROUND TO THE INVENTION
Field of the Invention:
The present invention relates to an amplification stage in which an envelope tracking (ET) modulator is utilised to provide a power supply to an RF amplifier.
Description of the Related Art:
With reference to Figure 1 there is illustrated components of an exemplary known RF amplification architecture in which an envelope tracking (ET) modulator is used to provide a power supply to a radio frequency (RF) power amplifier.
The exemplary known RE amplification architecture 100 receives a baseband input signal on line 108, which forms an input to an envelope signal generator 104 and an I & Q signal generator 106 of a signal generation block 102. The envelope signal generator 104 generates an envelope signal ENV on line 110 representing the envelope of the input baseband signal on line 108. The I & Q signal generator 106 generates I & Q signals respectively on lines 112 and 114, representing the I & Q components of the input baseband signal on line 108.
A set of digital-to-analogue converters (DACs) 116, 118 and 120 respectively convert the envelope signal ENV on line 116, the I signal on line 112, and the Q signal on line 114 into analogue signals on respective signal lines 117, 119 and 121.
The signal lines 117, 119 and 121 each carry analogue signals, and represent an analogue interface, as denoted by dashed line 150, between a digital baseband signal generation stage and an RE' amplifier with an envelope tracking power supply stage. The signal line 117 is an analogue interface between the digital baseband system and an envelope tracking power supply (as described below), and the signal lines 119 and 121 are an analogue interface between the digital baseband signal generation and the input to an RE' amplifier (as described below) The I and Q signals on lines 119 and 121 are provided as inputs to respective I and Q filters 124 and 126. The I and Q filtered signals at the outputs of the respective I and Q filters 124 and 126 are provided as inputs to a vector modulator 152. The vector modulator 152 includes a multiplier 128 for receiving at a first input the filtered I signal, and a multiplier 134 for receiving at a first input the filtered Q signal. The multipliers 128 and 130 respectively receive signals on lines 132 and 134 at second inputs. The vector modulator 152 further comprises a combiner 136 for receiving the outputs of the multipliers 128 and 130, and providing a combined output to a variable gain amplifier 138.
The output of the variable gain amplifier 138 is filtered by an optional inter-stage filter 140, which provides an input signal on line 141 to an RE' power amplifier 142. The RE' power amplifier 142 provides an amplified RE' output signal on line 146. The amplified RF output signal may provide a transmission signal to an antenna.
The analogue envelope signal on line 117 is provided as an input to an envelope filter 122. The envelope filtered signal at the output of the envelope filter 122 is provided as an input to a modulated power supply 144. The modulated power supply 144 generates a modulated power supply on line 148 to the power supply terminal of the RF amplifier 142.
In general the RE amplification stage 100 of Figure 1 comprises an RE or input signal path between the I & Q signal generator 106 and the input to the RE amplifier 142, and an envelope signal path between the envelope signal generator 104 and the power supply line 148 to the RE amplifier.
The modulated power supply 144 in the envelope signal path may be implemented in a number of ways. In a known preferred arrangement, the modulated power supply is implemented as a low frequency switched mode power supply in combination with a high frequency error tracking stage. The low frequency switched mode power supply selects one of a plurality of power supply voltages in dependence on the instantaneous magnitude of the envelope signal. The high frequency error tracking stage compares the signal generated by the switched mode power supply to a reference signal (a replica of the envelope signal), to determine an error in the generated signal and that error is then removed from the generated signal to provide a modulated power supply to the RE amplifier which more efficiently tracks the envelope.
It is an aim of the present invention to provide an improved technique for controlling the envelope path.
SUMMARY OF THE INVENTION:
-
In one aspect the invention provides an apparatus comprising: a baseband controller arranged to receive a digital envelope signal, the baseband controller comprising: a digital-to-analogue converter for converting the digital envelope signal into an analogue envelope signal; and a digital controller for generating a digital control signal for a switching stage in dependence on the digital envelope signal, a modulated supply stage comprising: a switching stage for receiving the digital control signal and for selecting one of a plurality of supply voltages in dependence on the digital control signal; a combiner for combining the selected supply voltage with an error signal, and for providing a power supply signal; and an error amplifier for receiving the analogue input signal and the output of the combiner and for generating the error signal; an analogue interface for connecting the analogue input signal from the baseband controller to the modulated stage; and a digital interface for connecting the digital control signal from the baseband controller to the modulated supply stage.
The baseband controller may comprise a digital delay stage for delaying the input to the digital to analogue converter.
The digital controller may include a delay stage for delaying the digital envelope signal.
The digital controller may comprise a signal processor for modifying the digital envelope signal. The digital controller may comprise a loop filter for the switching stage for filtering the digital envelope signal. The digital controller may comprise an asynchronous pulse width modulator adapted to receive an input from the digital envelope signal.
The asynchronous pulse width modulator may be adapted to include a balance loop.
An amplification stage may comprise an amplifier and an apparatus as defined, the apparatus being adapted to provide a power supply to the power amplifier.
The amplification stage may be arranged to amplify a signal from which the digital envelope signal is derived.
The amplification stage may comprise a further analogue interface, the signal for the power amplifier to amplify being provided on the further analogue interface.
In a further aspect the invention may provide a method of controlling an amplification stage including an amplifier and an envelope tracking power supply for the amplifier, comprising: receiving a digital envelope signal; converting the digital envelope signal into an analogue envelope signal; providing the analogue envelope signal on an analogue interface; generating a digital control signal in dependence on the digital envelope signal; providing the digital control signal to a power supply switching stage on a digital interface; connecting one of a plurality of power supply voltages to an output of the switching stage in dependence on the digital control signal; combining the connected power supply voltage and an error signal to generate the supply voltage for the amplifier; and amplifying the difference between the supply voltage for the amplifier and the analogue envelope signal to generate the error signal.
The method may further comprise delaying the input to the digital to analogue converter. The method may further comprise delaying the digital envelope signal. The method may further comprise signal processing for modifying the digital envelope signal to achieve a determined switcher path frequency response. The method may further comprise loop filtering the digital envelope signal. The method may further comprise asynchronously pulse width modulating the digital envelope signal to provide the digital control signal.
The method may further comprise providing a power supply to the power amplifier.
The method may further comprise amplifying a signal from which the digital envelope signal is derived.
BRIEF DESCRIPTION OF THE FIGURES:
The invention will now be described by way of example with reference to the accompanying Figures in which: Figure 1 illustrates an RE amplification stage as known in the art; and Figure 2 illustrates an improved RF amplification stage in accordance with an embodiment of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS:
The invention will now be described with further reference to the exemplary RI amplification architecture of Figure 2, which represents the RF amplification architecture of Figure 1 modified in accordance with an exemplary embodiment of the invention. The invention, and its embodiments, is not however limited in its applicability to the exemplary architecture and implementation as illustrated in Figure 2.
The RF or input signal path of Figure 1, comprising the path from the I & Q signal generator 106 to the input of the RF amplifier 142, is not shown in Figure 2 to simplify the illustration. It will be understood that in a preferred embodiment, the input to the RF amplifier 142 on line 141 is provided in Figure 2 in the same way as illustrated in Figure 1.
A baseband controller 228 includes a digital controller 230 for generating a digital control signal for a switching stage on line 234, and an analogue converter stage 232 for generating an analogue control signal. The envelope signal EN\J on line 110 from the envelope signal generator 104 is provided as an input to the digital controller 230 and the analogue converter stage 232.
In the described embodiment, the envelope signal generator 104 may, for example, include a look-up table to provide shaping of the envelope signal. Such shaping may be based on a pre-characterisation of the amplifier 142 for certain operating conditions.
The analogue converter stage 232 includes a delay stage 210 for receiving the digital envelope signal on line 110, and a digital-to-analogue converter 212 adapted to receive the delayed envelope signal and generate a delayed analogue envelope signal on line 244. The application of a delay in delay stage 210 is well-known in the art, the delay serving to help align signals in the amplification stage to improve the efficiency of operation.
The digital controller 230 includes an optional delay stage 200 for the envelope signal on line 110. The delay stage 200, where provided, operates similar to the delay stage 210 to help align the signals in the amplification stage.
The delayed envelope signal from delay block 200 is provided as an input to a signal processor (or signal compensation stage) 202. The signal processor 202 includes filtering and delay elements which are designed mainly with the aim of getting the correct switcher path frequency response from the input of the signal processor 202 through to an output 222 or 148 (described below) The output of the signal processor 202 is provided as an input to a switched mode power supply loop filter 204.
The switched mode power supply loop filter 204 provides an input to an asynchronous pulse width modulator 206. The asynchronous pulse width modulator 206 may be optionally connected to a balance loop 208. The asynchronous pulse width modulator (APWM) 206 generates a digital control signal on line 234. In dependence on the input signal provided to it, the APWM generates a pulse width modulated signal for the switched mode power supply 214.
The switched mcde power supply 214 is purely a set of power switches for switching between supply voltages. No determination of the signals which control the switching of the power switches in block 214 is made after generation of the pulse width modulated output from block 206.
The implementation of the digital controller 230 as described above and illustrated in Figure 2 is exemplary.
Various implementations may be envisaged. In general the digital controller 230 is arranged to receive as an input the digital envelope signal and generate as an output a digital control signal for switching a switched mode power supply. In the described embodiment, the digital envelope signal is converted into an analogue signal for use by an error correction means acting on the output of the switched mode power supply.
In a preferred implementation, the digital controller 230 in combination with the switched mode power supply provides a low-level digital-to-analogue converter. Whilst this may be achieved utilising the elements shown in Figure 2, this is only an exemplary arrangement.
A modulated power supply stage 246 receives the analogue envelope signal on line 244 and the digital control signal on line 234. Thus there is provided a digital interface 224 in the envelope signal path between the baseband controller and modulated supply, and an analogue interface in the envelope signal path between the baseband controller and the modulated supply.
The modulated power supply stage, in a preferred implementation, comprises the switched mode power supply 214, an error amplifier 216, and a combiner 220.
The switched mode power supply 214 receives the digital control signal on line 234, and in dependence thereon power supplies are selected to be connected to an output line 222 of the switched mode power supply 214 to form a first input to the combiner 220. The error amplifier 216 receives as one input the analogue envelope signal on line 244, and as a second input the output of the combiner 220. The error amplifier amplifies the difference between the analogue envelope signal and the output of the combiner, and the amplified output is provided as the second input to the combiner 220. The output of the combiner additionally provides the power supply voltage to the RF amplifier 142 on line 148.
Thus in accordance with the invention the baseband controller in the digital domain is adapted to include processing circuitry and functionality associated with the switched mode power supply of the analogue domain, such that the final control signal for the switched mode power supply is generated entirely in the digital domain.
The implementation of this circuitry and functionality in the digital domain reduces the power consumption in comparison to implementing the circuitry and functionality in the analogue domain. A digital interface is then provided from the baseband controller solely to drive the switches of the switched mode power supply. In addition, an analogue interface is maintained to provide an analogue envelope signal for error correction at the output of the switched mode power supply. ii
The amplification stage incorporating an envelope tracking modulated power supply as described herein is broadly applicable. A preferred implementation is for a power amplifier such as a radio frequency (RF) amplifier. An RB' amplifier may be a component of a communication system, such as mobile communication device or an infrastructure device. A mobile communication device, such as a mobile telephone, may thus incorporate the architecture as described herein. In a mobile telephone implementation, a plurality of RF power amplifiers, such as amplifiers 142, may be provided. In a particular arrangement, only one of the plurality of RB' power amplifiers is active at any one time, and whilst the other RB' power amplifiers are inactive they nevertheless load the power supply connection on line 148 with additional capacitance. The present invention has particular advantages in such an implementation.
Another advantage of the implementation in the digital domain is that the implementation itself becomes very well controlled, predictable and repeatable in comparison with an analogue implementation.
The invention is described herein with reference to particular examples and embodiments, which are useful for understanding the invention and understanding a preferred implementation of the invention. The invention is not, however, limited to the specifics of any given embodiment, nor are the details of any embodiment mutually exclusive. The scope of the invention is defined by the appended claims.
Claims (18)
- Claims 1. An apparatus comprising: a baseband controller arranged to receive a digital envelope signal, the baseband controller comprising: a digital-to-analogue converter for converting the digital envelope signal into an analogue envelope signal; and a digital controller for generating a digital control signal for a switching stage in dependence on the digital envelope signal, a modulated supply stage comprising: a switching stage for receiving the digital control signal and for selecting one of a plurality of supply voltages in dependence on the digital control signal; a combiner for combining the selected supply voltage with an error signal, and for providing a power supply signal; and an error amplifier for receiving the analogue input signal and the output of the combiner and for generating the error signal; an analogue interface for connecting the analogue input signal from the baseband controller to the modulated stage; and a digital interface for connecting the digital control signal from the baseband controller to the modulated supply stage.
- 2. The apparatus of claim 1 wherein the baseband controller comprises a digital delay stage for delaying the input to the digital to analogue converter.
- 3. The apparatus of claim 1 or claim 2 wherein the digital controller includes a delay stage for delaying the digital envelope signal.
- 4. The apparatus of any one of claims 1 to 3 wherein the digital controller comprises a signal processor for modifying the digital envelope signal.
- 5. The apparatus of any one of claims 1 to 4 wherein the digital controller comprises a loop filter for the switching stage for filtering the digital envelope signal.
- 6. The apparatus of any one of claims 1 to 5 wherein the digital controller comprises an asynchronous pulse width modulator adapted to provide the digital control signal.
- 7. The apparatus of claim 6 wherein the asynchronous pulse width modulator is adapted to include a balance loop.
- 8. An amplification stage comprising a power amplifier and an apparatus according to any one of claims 1 to 7, the apparatus being adapted to provide a power supply to the power amplifier.
- 9. The amplification stage of claim 8 wherein the power amplifier is arranged to amplify a signal from which the digital envelope signal is derived.
- 10. The amplification stage of claim 9 comprising a further analogue interface, the signal for the power amplifier to amplify being provided on the further analogue interface.
- 11. A method of controlling an amplification stage including an amplifier and an envelope tracking power supply for the amplifier, comprising: receiving a digital envelope signal; converting the digital envelope signal into an analogue envelope signal; providing the analogue envelope signal on an analogue interface; generating a digital control signal in dependence on the digital envelope signal; providing the digital control signal to a power supply switching stage on a digital interface; connecting one of a plurality of power supply voltages to an output of the switching stage in dependence on the digital control signal; combining the connected power supply voltage and an error signal to generate the supply voltage for the amplifier; and --amplifying the difference between the supply voltage for the amplifier and the analogue envelope signal to generate the error signal.
- 12. The method of claim 11 further comprising delaying the input to the digital to analogue converter.
- 13. The method of claim 11 or claim 12 further comprising delaying the digital envelope signal.
- 14. The method of any one of claims 11 to 13 further comprising signal processing for modifying the digital envelope signal to achieve a determined switcher path frequency response.
- 15. The method of any one of claims 11 to 14 further comprising loop filtering the digital envelope signal.
- 16. The method of any one of claims 11 to 15 further -comprising asynchronously pulse width modulating the digital envelope signal to provide the digital control signal.
- 17. The method according to any one of claims 11 to 16 further comprising providing a power supply to the power amplifier.
- 18. The method of claim 17 further comprising amplifying a signal from which the digital envelope signal is derived.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1108969.5A GB2491186A (en) | 2011-05-27 | 2011-05-27 | A combined analogue and digital interface for the envelope path of an envelope-tracking amplifier |
| PCT/EP2012/059936 WO2012163875A1 (en) | 2011-05-27 | 2012-05-28 | Envelope path processing for envelope tracking amplification stage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1108969.5A GB2491186A (en) | 2011-05-27 | 2011-05-27 | A combined analogue and digital interface for the envelope path of an envelope-tracking amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB201108969D0 GB201108969D0 (en) | 2011-07-13 |
| GB2491186A true GB2491186A (en) | 2012-11-28 |
Family
ID=44310523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB1108969.5A Withdrawn GB2491186A (en) | 2011-05-27 | 2011-05-27 | A combined analogue and digital interface for the envelope path of an envelope-tracking amplifier |
Country Status (2)
| Country | Link |
|---|---|
| GB (1) | GB2491186A (en) |
| WO (1) | WO2012163875A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2510395A (en) * | 2013-02-01 | 2014-08-06 | Nujira Ltd | Voltage supply stage for an envelope tracking modulated power supply |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2398648A (en) * | 2003-02-19 | 2004-08-25 | Nujira Ltd | Amplifier power supply whose voltage tracks a signal envelope |
| US6788151B2 (en) * | 2002-02-06 | 2004-09-07 | Lucent Technologies Inc. | Variable output power supply |
| EP1492227A1 (en) * | 2003-06-24 | 2004-12-29 | Northrop Grumman Corporation | Multi-mode amplifier system |
| US7715811B2 (en) * | 2005-03-07 | 2010-05-11 | Andrew Llc | Integrated transceiver with envelope tracking |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8301088B2 (en) * | 2007-10-26 | 2012-10-30 | Panasonic Corporation | Polar modulation transmitter with envelope modulator path switching |
| US8014735B2 (en) * | 2007-11-06 | 2011-09-06 | Quantance, Inc. | RF power amplifier controlled by estimated distortion level of output signal of power amplifier |
-
2011
- 2011-05-27 GB GB1108969.5A patent/GB2491186A/en not_active Withdrawn
-
2012
- 2012-05-28 WO PCT/EP2012/059936 patent/WO2012163875A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6788151B2 (en) * | 2002-02-06 | 2004-09-07 | Lucent Technologies Inc. | Variable output power supply |
| GB2398648A (en) * | 2003-02-19 | 2004-08-25 | Nujira Ltd | Amplifier power supply whose voltage tracks a signal envelope |
| EP1492227A1 (en) * | 2003-06-24 | 2004-12-29 | Northrop Grumman Corporation | Multi-mode amplifier system |
| US7715811B2 (en) * | 2005-03-07 | 2010-05-11 | Andrew Llc | Integrated transceiver with envelope tracking |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2012163875A1 (en) | 2012-12-06 |
| GB201108969D0 (en) | 2011-07-13 |
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| 732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) |
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| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |