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GB2453115A - HBT and FET BiFET hetrostructure and substrate with etch stop layers - Google Patents

HBT and FET BiFET hetrostructure and substrate with etch stop layers Download PDF

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Publication number
GB2453115A
GB2453115A GB0718676A GB0718676A GB2453115A GB 2453115 A GB2453115 A GB 2453115A GB 0718676 A GB0718676 A GB 0718676A GB 0718676 A GB0718676 A GB 0718676A GB 2453115 A GB2453115 A GB 2453115A
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United Kingdom
Prior art keywords
layer
multilayer semiconductor
etch stop
fet
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
GB0718676A
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GB0718676D0 (en
Inventor
John Stephen Atherton
Matthew Francis O'keefe
Michael Charles Clausen
Robert Grey
Richard Alun Davies
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RFMD UK Ltd
Original Assignee
Filtronic Compound Semiconductors Ltd
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Application filed by Filtronic Compound Semiconductors Ltd filed Critical Filtronic Compound Semiconductors Ltd
Priority to GB0718676A priority Critical patent/GB2453115A/en
Publication of GB0718676D0 publication Critical patent/GB0718676D0/en
Priority to PCT/GB2008/003216 priority patent/WO2009040509A1/en
Publication of GB2453115A publication Critical patent/GB2453115A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A multi layer semiconductor structure divided into HBT, heterojunction bipolar transistor (2) and FET, field effect transistor (3) portions with a first epitaxial structure (4) shared by the HBT and FET portions, the epitaxial structure contain layers suitable for forming the layers of a FET beneath a FET gate (5); a first etch stop layer (13) on the first epitaxial structure shared by the HBT and FET portions; a cap layer (14) on the first etch stop layer shared by the HBT and FET portions; the FET portion with an aperture (15) extending through the cap layer (14) and first etch stop layer to the first epitaxial structure; a second etch stop layer on the HBT portion of the cap layer; and a second epitaxial structure (19) on the second etch stop layer (18). The second epitaxial structure includes layers suitable for forming a portion of a HBT and can contain subcollector (20), collector (21), base (22) and emitter (24). The base can include a AlInP cover layer (23). The etch stop layers 13, 18 can be made of a AlInP in a AlxIN1-xP composition where x is in the range of 0.05 to 0.95 or 0.4 to 0.6 or have the value of 0.5. By using a material which includes both Aluminum and Phosphorous the etch stop layer can be used for both dry and wet etch fabrication methods. The FET can be a MESFET or a pseudomorphic HEMT, pHEMT with a Schottky barrier layer.

Description

1 2453115 A MULTILAYER SEMICONDUCTOR STRUCTURE, A BFET INCLUDING SUCH A STRUCTURE, AND A MULTILAYER SEMICONDUCTOR
SUBSTRATE
The present invention relates to a multilayer semiconductor structure, a BIFET including such a structure and also to a multilayer semiconductor substrate for the manufacture of such a structure. More particularly, but not exclusively, the present invention relates to a BiFET in which the sub-collector layer of the HBT is a different layer to the cap layer of the FET.
The integration of field effect transistors (FETs) and heterojunction bipolar transistor (HBTs) into a single structure (a BIFET) is attractive as it enables a number of design possibilities. These include bias enabled switching, stage bypassing, adaptive gate switching and integration of amplifier and switch.
US 7015519 (ANADIGICS INC) discloses an integrated FETIHBT device. The integrated device comprises a contact layer shared by the FET and HBT. Within the FET the contact layer acts as a cap layer on the FET. Within the HBT the contact layer acts a *.*., 20 sub-collector layer.
This sharing of a common layer increases the compactness of the integrated device.
* However, this tends to result in thermal runaway of the device. In addition, the HBT and FET optimally require different thickness of contact layer so resulting in a design trade ::. 25 off in the final design.
The multilayer semiconductor structure according to the invention seeks to overcome these problems.
Accordingly, in a first aspect, the present invention provides a multilayer semiconductor structure divided into HBT and FET portions comprising a first epitaxial structure shared by the J-LBT and FET portions, the epitaxial structure comprising layers suitable for forming the layers of a FET beneath a FET gate; a first etch stop layer on the first epitaxial structure shared by the HBT and FET portions; a cap layer on the first etch stop layer shared by the HBT and FET portions; the FET portion comprising an aperture extending through the cap layer and first etch stop layer to the first epitaxial structure; a second etch stop layer on the HBT portion of the cap layer; and a second epitaxial structure on the second etch stop layer, the second epitaxial structure comprising layers suitable for forming a portion of a HBT.
By connecting appropriate contacts to the multilayer semiconductor structure it acts as a BIFET. As the second epitaxial structure is separated from the cap layer, rather than :... sharing a layer, the resulting BiFET does not suffer from thermal runaway. In addition, a...
no design comprise is necessary for the thickness of the cap layer. S...
Preferably the multilayer semiconductor structure further comprises a metal gate contact *.Sa..
* on the first epitaxial structure within the aperture. 5* 55 * . S * .
The multilayer semiconductor structure can further comprise an ohmic metal source contact and an ohmic metal drain contact arranged on the cap layer on opposite sides of the aperture.
The first etch stop layer can be AlInP.
The second etch stop layer can be AIInP.
The cap layer can be GaAs.
Preferably, the composition of the AIInP layer is AlIn1P, wherein x is in the range 0.05 to 0.95, more preferably 0.4 to 0.6, more preferably 0.5.
The first epitaxial structure can comprise a buffer layer, preferably an AlCiaAs or GaAs buffer layer.
The first epitaxial structure can comprise a set of MESFET epitaxial layers.
The MESFET layer can comprise an undoped spacer layer and a doped channel layer.
The spacer layer and channel layer can be GaAs layers.
Alternatively, the first epitaxial structure comprises a set of pHEMT layers.
The pHEMT layers can comprise a barrier layer, a channel layer and a Schottky barrier : ... layer. I... * * *.
The barrier layer can be GaAs. The barrier layer can be AIGaAs. The barrier layer can be AlInAs or InGaP.
*. S0*, * I The Schottky barrier layer can be AIGaAs or InGaP. The Schottky barrier layer can be *:*. AlinAs.
The channel layer can be InGaAs.
The second epitaxial layer can comprise a sub-collector layer, a collector layer, a base layer and an emitter layer.
The base layer can comprise a GaAs layer.
The base layer can further comprise an AIInP cover layer on the GaAs layer.
The collector layer can comprise a GaAs layer.
The sub-collector layer can comprise a GaAs layer.
In a further aspect of the invention there is provided a BiFET comprising a multilayer semiconductor structure divided into HBT and FET portions comprising a first epitaxial structure shared by the HBT and FET portions, the epitaxial structure comprising layers suitable for forming the layers of a FET beneath a FE1' gate; a first etch stop layer on the first epitaxial structure shared by the HBT and FET portions; a cap layer on the first etch stop layer shared by the HBT and FET portions; :... the FET portion comprising an aperture extending through the cap layer and first etch S...
stop layer to the first epitaxial structure; a second etch Stop layer on the HBT portion of the cap layer; and *5*SS* * I * a second epitaxial structure on the second etch stop layer, the second epitaxial structure *:*. comprising layers suitable for forming a portion of a 1- IBT In a further aspect of the invention there is provided a multilayer semiconductor substrate for manufacture of a combined FET and HBT, the substrate comprising a first epitaxial structure comprising layers suitable for forming the layers of a FET beneath a FET gate; an etch stop layer on the first epitaxial structure; a cap layer on the first etch stop layer; a second etch stop layer on the cap layer; and a second epitaxial structure on the second etch stop layer, the second epitaxial structure comprising layers suitable for forming a portion of a HBT.
The first etch stop layer can be AlInP.
The second etch stop layer can be AlInP.
Preferably, the composition of the AlInP layer is Al1ni..P, wherein x is in the range 0.05 to 0.95, preferably in the range 0.4 to 0.6, more preferably 0.5.
Preferably, the first epitaxial layer comprises a buffer layer, preferably an AIGaAs or : ... GaAs buffer layer. * S 5._S
The first epitaxial structure can comprise a set of MESFET epitaxial layers. S...
S *
* The set of MESFET layers can comprise an undoped spacer layer and a doped channel layer. * I S * *.
The spacer layer and channel layer can be GaAs layers.
Alternatively, the first epitaxial structure comprises a set of pHEMT layers.
The pHEMT layers can comprise a barrier layer, a channel layer and a Schottky barrier layer.
The barrier layer can be GaAs or AlGaAs. The barrier layer can be AlinAs or inGaP.
The channel layer can be InGaAs.
The Schottky barrier layer can be AIGaAs or InGaP. The Schottky barrier layer can be AlinAs.
The cap layer can be GaAs.
Preferably, the second epitaxial structure comprises a sub-collector layer, a collector layer, a base layer and an emitter layer.
The base layer can comprise a GaAs layer.
The collector layer can comprise a GaAs layer.
The sub-collector layer can comprise a GaAs layer.
s..' The present invention will now be described by way of example only, and not in any limitative sense with reference to the accompanying drawings in which * Figure 1 shows a BiFET according to the invention in cross section; and *. S. * . S * . Figure 2 shows a multilayer semiconductor substrate according to the invention in cross section.
Shown in figure 1 is a BiFET I according to the invention in cross section, The BiFET I comprises a multilayer semiconductor structure divided into HBT and FET portions 2,3.
The multilayer semiconductor structure comprises a first epitaxial structure 4 shared by the FET and HBT portions 2,3. The first epitaxial structure 4 comprises layers suitable for forming layers of a FET beneath a FET gate 5. In particular, the first epitaxial structure 4 comprises a buffer layer 6. The buffer layer 6 is typically GaAs or AlGaAs.
Arranged on the buffer layer 6 are a set of pHEMT layers 7. The pHEMT layers 7 comprise a barrier layer 8. This is typically GaAs or AIGaAs. The barrier layer 8 could also be InAlAs or InGaP. Above the barrier layer 8 is a Schottky barrier layer 9. This is typically AJGaAs or InGaP. A further alternative is AlInAs. Sandwiched between the barrier layer 8 and Schottky barrier layer 9 is a channel layer 10 typically an InGaAs layer. At least one of the barrier layer 8 and the Schottky layer 9 comprises at least one silicon layer 11 which act as electron donor layers for the channel layer 10. Arranged on the Schottky barrier layer 9 is a GaAs cover layer 12. The operation of a pHEMT is well known and will not be described in detail.
Arranged on the first epitaxial structure 4 is an AIInP first etch stop layer 13 shared between the FET and HBT regions 2,3. Arranged on the first etch stop layer 13 is a GaAs cap layer 14 shared between HB1' and FET regions 2,3.
An aperture 15 extends through the cap layer 14 and first etch stop layer 13 to the first epitaxial structure 4 in the FET region 3. Arranged in the aperture 15 on the first epitaxial structure 4 is the metal gate contact 5. Arranged on the cap layer 14 on either side of the metal gate 5 contact are ohmic metal source and drain contacts 16,17.
ii: Arranged on the cap layer 14 in the HBT region 2 is a second AIInP etch stop layer 18.
Arranged on the second etch stop layer 18 is a second epita.xial structure 19 comprising r:* layers suitable for forming a portion of a HBT. In particular the second epitaxial structure 19 comprises a GaAs sub-collector layer 20 arranged on the second etch stop layer 18. Arranged on the sub-collector layer 20 is a GaAs collector layer 21. Arranged on the collector layer 21 is a GaAs base layer 22. The base layer 22 is covered by an optional AIInP cover layer 23 to reduce recombination current in the HBT. Arranged on the cover layer 23 is a GaAs emitter layer 24. Finally, on the emitter layer 24 is an lnGaAs contact layer 25.
Arranged on the sub-collector layer 20 is an ohmic metal collector contact 26. Arranged on the cover layer 23 is a metal base contact 27. Finally, arranged on the contact layer 25 is a metal emitter contact 28. The operation of a HBT is known and will not be described in detail.
The FET portion 3 and the HBT portion 2 are electrically isolated from each other by an isolation portion 29 formed by implant isolation of a section through the multilayer semiconductor structure.
The BiFET I of the invention has separate sub-collector and cap layers 20,14 separated by an etch stop layer 18. Accordingly, in contrast to known B1FETs, the BIFET 1 of the invention does not suffer from thermal runaway.
The etch stop layers 13,18 are AlInP. More Particularly, the composition of the etch stop layers is Al1n1.P wherein x is in the range 0.05 to 0.95, preferably 0.4 to 0.6, more preferably 0.5.
In an alterative aspect of the invention (not shown) the first epitaxial structure 4 comprises a set of MESFET layers. The MESFET layers comprise an undoped GaAs spacer layer and a doped GaAs channel layer. Again, the operation of the MESFET is :.: well known and will not be described in detail.
. Shown in figure 2 is a multilayer semiconductor substrate 30 according to the invention.
The substrate 30 comprises a first epitaxial structure 4 comprising layers suitable for forming the layers of a FET beneath a FET gate. The first epitaxial structure 4 has been described in detail with reference to figure 1.
Arranged on the first epitaxial structure 4 is a first AlInP etch stop layer 12. Arranged on the first etch stop layer 12 is a GaAs cap layer 14. Arranged on the cap layer 14 is a second AIInP etch stop layer 18. Finally, arranged on the second etch stop layer 18 is a second epitaxial structure 19 comprising a sub-collector, collector, base and emitter layers (not shown). The second epitaxial structure 19 has been described in detail with reference to figure 1.
The multilayer semiconductor substrate 30 according to the invention can be used to manufacture a BiFET similar to that of figure 1 although lacking the optional cover layer 23 and contact layer 25. In further embodiments of the invention (not shown), the multilayer semiconductor substrate 30 further comprises one or both of these optional layers.
The method of manufacture of a BIFET I according to the invention from a multilayer semiconductor substrate 30 as shown in figure 2 would be a relatively straightforward matter for one skilled in the art of device fabrication and will not be described in detail.
An important feature of a preferred embodiment of the multilayer semiconductor substrate 30 of the current invention is that the etch stop layers 12,18 comprise both Aluminium and Phosphorous (preferably AlInP). This enables etching by both wet and dry routes. This enables the manufacture of a BiFET I having either vertical or shaped structures so allowing for greater flexibility in the design of the BiFET 1.
The above description includes references to layers comprising three components, including AIInP, AlGaAs, AIInAs, InGaP and InGaAs. More generally, these may be written as AB1.C. With the exception of AIInP specific compositional ranges of x have not been specified. Suitable ranges for x are well known to one skilled in the art of device manufacture and are defined by the desired device characteristics and also by the requirement to keep the difference in lattice spacing between adjacent layers within acceptable ranges to reduce device stress. As a specific example, x is typically in the range 0.05 to 0.95, more preferably 0.4 to 0.6, more preferably 0.5.

Claims (49)

1. A multilayer semiconductor structure divided into HUT and FET portions comprising a first epitaxial structure shared by the HBT and FET portions, the epitaxial structure comprising layers suitable for forming the layers of a FET beneath a FET gate; a first etch stop layer on the first epitaxial structure shared by the HBT and FET portions; a cap layer on the first etch stop layer shared by the HBT and FET portions; the FET portion comprising an aperture extending through the cap layer and first etch stop layer to the first epitaxial structure; a second etch stop layer on the HUT portion of the cap layer; and a second epitaxial structure on the second etch stop layer, the second epitaxial structure comprising layers suitable for forming a portion of a HUT. *.S. * . * *S.
2. A multilayer semiconductor structure as claimed in claim 1, further comprising a * ** metal gate contact on the first epitaxial structure within the aperture.
S
* * .5S* * *
3. A multilayer semiconductor structure as claimed in either of claims I or 2, further comprising an ohmic metal source contact and an ohmic metal drain contact * arranged on the cap layer on opposite sides of the aperture.
4. A multilayer semiconductor structure as claimed in any one of claims 1 to 3, wherein the first etch stop layer is AIInP.
5. A multilayer semiconductor structure as claimed in any one of claims I to 4, wherein the second etch stop layer is AlInP.
6. A multilayer semiconductor structure as claimed in either of claims 4 or 5, wherein the composition of the AlInP layer is AllniP, wherein x is in the range 0.05 to 0.95, more preferably 0.4 to 0.6, more preferably 0.5.
7. A multilayer semiconductor structure as claimed in any one of claims 1 to 6, wherein the cap layer is GaAs.
8. A multilayer semiconductor structure as claimed in any one of claims 1 to 7, wherein the first epitaxial structure comprises a buffer layer, preferably an AIGaAs or GaAs buffer layer.
9. A multilayer semiconductor structure as claimed in any one of claims I to 8, wherein the first epitaxial structure comprises a set of MESFET epitaxial layers.
10. A multilayer semiconductor structure as claimed in claim 9, wherein the MESFET layer comprises an undoped spacer layer and a doped channel layer.
:
ii. A multilayer semiconductor structure as claimed in claim 10, wherein the spacer layer and channel layer are GaAs layers. S... * S S...
12. A multilayer semiconductor structure as claimed in any one of claims I to 8 *5**** wherein the first epitaxial structure comprises a set of pHEMT layers.
13. A multilayer semiconductor structure as claimed in claim 12, wherein the pHEMT layers comprise a barrier layer, a channel layer and a Schottky barrier layer.
14. A multilayer semiconductor structure as claimed in claim 13, wherein the barrier layer is GaAs or AIGaAs.
15. A multilayer semiconductor structure as claimed in claim 13, wherein the barrier layer is AIGaAs.
16. A multilayer semiconductor structure as claimed in claim 13, wherein the barrier layer is AlinAs or InGaP.
17. A multilayer semiconductor structure as claimed in any one of claims 13 to 16, wherein the Schottky barrier layer is AIGaAs or InGaP.
18. A multilayer semiconductor structure as claimed in any one of claims 13 to 16, wherein the Schottky barrier layer is AlinAs.
19. A multilayer semiconductor structure as claimed in any one of claims 13 to 18, wherein the channel layer is InGaAs.
20. A multilayer semiconductor structure as claimed in any one of claims I to 19, wherein the second epitaxial layer comprises a sub-collector layer, a collector layer, a base layer and an emitter layer.
21. A multilayer semiconductor Structure as claimed in claim 20, wherein the base layer comprises a GaAs layer. S... * * *...
22. A multilayer semiconductor structure as claimed in claim 21, wherein the base layer further comprises a AllnP cover layer on the GaAs layer. 1 ** * S * * S
23. A multilayer semiconductor structure as claimed in claim 20, wherein the collector layer comprises a GaAs layer.
24. A multilayer semiconductor structure as claimed in claim 20, wherein the sub-collector layer comprises a GaAs layer.
25. A BiFET comprising a semiconductor structure as claimed in any one of claims 1 to 24.
26. A multilayer semiconductor substrate for manufacture of a combined FET and HBT, the substrate comprising a first epitaxial structure comprising layers suitable for forming the layers of a FET beneath a FET gate; an etch stop layer on the first epitaxial structure; a cap layer on the first etch stop layer; a second etch stop layer on the cap layer; and a second epitaxial structure on the second etch stop layer, the second epitaxial structure comprising layers suitable for forming a portion of a HBT.
27. A multilayer semiconductor substrate as claimed in claim 26, wherein the first etch stop layer is AIInP. * S * *e*
28. A multilayer semiconductor substrate as claimed in either of claims 26 or 27, S...
* wherein the second etch stop layer is AIInP. * .
29. A multilayer semiconductor substrate as claimed in either of claims 27 or 28, wherein the composition of the AIInP layer is AlInjP, wherein x is in the range 0.05 to 0.95, preferably in the range 0.4 to 0.6, more preferably 0.5.
30. A multilayer semiconductor substrate as claimed in any one of claims 26 to 29, wherein the first epitaxial layer comprises a buffer layer, preferably an AIGaAs or GaAs buffer layer.
31. A multilayer semiconductor substrate as claimed in any one of claims 26 to 30, wherein the first epitaxial structure comprises a set of MESFET epitaxial layers.
32. A multilayer semiconductor substrate as claimed in claim 31, wherein the set of MESFET layers comprises an undoped spacer layer and a doped channel layer.
33. A multilayer semiconductor substrate as claimed in claim 32, wherein the spacer layer and channel layer are GaAs layers.
34. A multilayer semiconductor substrate as claimed in any one of claims 26 to 30, wherein the first epitaxial structure comprises a set of pHEMT layers.
35. A multilayer semiconductor substrate as claimed in claim 34, wherein the pHEMT layers comprise a barrier layer, a channel layer and a Schottky barrier layer. S.
36. A multilayer semiconductor substrate as claimed in claim 35 wherein the barrier layer is GaAs * S
37. A multilayer semiconductor substrate as claimed in claim 35, wherein the ban-icr r layer is AlGaAs.
38. A multilayer semiconductor wafer as claimed in claim 35, wherein the barrier layer is AlInAs or InGaP.
39. A mullilayer semiconductor substrate as claimed in any one of claims 35 to 38, wherein the channel layer is InGaAs.
40. A multilayer semiconductor substrate as claimed in any one of claims 35 to 39, wherein the Schottky barrier layer is AIGaAs or InGaP.
41. A multilayer semiconductor substrate as claimed in any one of claims 35 to 39, wherein the Schottky barrier layer is AlInAs.
42. A multilayer semiconductor substrate as claimed in any one of claims 26 to 41, wherein the cap layer is GaAs.
43. A multilayer semiconductor substrate as claimed in any one of claims 26 to 42, wherein the second epitaxial structure comprises a sub-collector layer, a collector layer, a base layer and an emitter layer.
44. A multilayer semiconductor substrate as claimed in claim 43, wherein the base layer comprises a GaAs layer.
45. A multilayer semiconductor substrate as claimed in either of claims 43 or 44, wherein the collector layer comprises a GaAs layer. S.
46. A multilayer semiconductor substrate as claimed in any one of claims 43 to 45 S...
* wherein the sub-collector layer comprises a GaAs layer. * . *.
47. A multilayer semiconductor structure substantially as hereinbefore described.
48. A multilayer semiconductor substrate substantially as hereinbefore described.
49. A BiFET substantially as hereinbefore described.
GB0718676A 2007-09-25 2007-09-25 HBT and FET BiFET hetrostructure and substrate with etch stop layers Withdrawn GB2453115A (en)

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PCT/GB2008/003216 WO2009040509A1 (en) 2007-09-25 2008-09-23 A multilayer semiconductor structure, a bifet includin such a structure, and a multilayer semiconductor substrate

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US9679869B2 (en) 2011-09-02 2017-06-13 Skyworks Solutions, Inc. Transmission line for high performance radio frequency applications
KR102250612B1 (en) 2012-06-14 2021-05-10 스카이워크스 솔루션즈, 인코포레이티드 Power amplifier modules with harmonic termination circuit and related systems, devices, and methods

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