GB2329748A

GB2329748A - Capstan motor control

Info

Publication number: GB2329748A
Application number: GB9813102A
Authority: GB
Inventors: Kyong-Chul Yu
Original assignee: Daewoo Electronics Co Ltd
Current assignee: WiniaDaewoo Co Ltd
Priority date: 1997-09-24
Filing date: 1998-06-17
Publication date: 1999-03-31
Also published as: KR19990026311A; GB9813102D0; KR100255546B1; JPH1196620A

Abstract

Disclosed is a method of controlling the operation of a capstan motor in a video cassette recorder (VCR). Based on a capstan frequency generator pulse signal generated by a capstan frequency generator (CFG) it is decided whether a capstan slip has occurred. If so, a playback radio frequency (RF) signal envelope is received. If the level of the envelope is equal to or less than a predetermined threshold value then operation of the capstan motor is controlled by correcting the capstan motor driving time.

Description

METHOD AND APPARATUS FOR CONTROLLING THE OPERATION OF A CAPSTAN MOTOR IN A VIDEO CASSETTE RECORDER The present invention relates to a video cassette recorder (VCR); and, more particularly, to a method and apparatus for effectively controlling the operation of a capstan motor contained in the VCR in a special playback mode such as a fine-slow playback mode.

In a magnetic recording and reproducing apparatus which records and reproduces a video signal onto and from tracks which are obliquely formed on a magnetic tape, recording positions of a vertical synchronization signal must be aligned at end parts of the oblique and parallel recording tracks upon recording. Upon reproduction, rotary heads must accurately scan over the above recording tracks. Hence, in the so-called helical scan type magnetic recording and reproducing apparatus, generally, a head servo circuit and a capstan servo circuit are provided to satisfy the requirements. The head servo circuit comprises a speed control loop for controlling the rotational speed of rotary heads and a phase control loop for controlling the rotational phase of the rotary heads. The capstan servo circuit controls the rotational speed and the rotational phase of a capstan which drives the magnetic tape to travel.

One of various schemes for controlling the operation of the capstan motor in a specific playback mode such as a fineslow mode , still mode and so on is disclosed in, e.g., U.S.

Pat. No. 5,327,249 issued to Lee. Specifically, in Lee's patent, a control pulse is detected from a video tape and is applied to a servo control device. And then, at an envelop detector, a playback radio frequency (RF) signal is received; and an envelop level of the DC component of the received signal is detected.

In a microcomputer, the detected envelop level is first sampled in intervals of a head switching signal of the front and rear of the control pulse in a slow playback interval.

Thereafter, control data for controlling the capstan motor is obtained by comparing the sample values with each other. The control data is applied to the servo control device to control a shift of the control pulse, wherein the control pulse is shifted in a positive or negative direction based on the comparison result.

Since, however, the prior art capstan servo control device controls the operation of the capstan motor without taking account of the characteristics of a deck mechanism in a capstan motor driving system of the VCR, the capstan motor is not accurately stopped at a time when it should be stopped in case the characteristics of the deck mechanism is to be changed, resulting in a malfunction in the capstan motor driving system.

It is, therefore, a primary object of the present invention to provide a method and apparatus capable of providing an optimum capstan servo control scheme which takes account of the characteristics of a deck mechanism in a special playback mode such as a fine-slow playback mode.

In accordance with one aspect of the invention, there is provided a method for controlling the operation of a capstan motor contained in a video cassette recorder (VCR), the method comprising the steps: (a) receiving a capstan frequency generator (CFG) pulse signal generated by a CFG pulse signal in the VCR and deciding whether or not a capstan slip has occurred based on the CFG pulse signal, wherein the capstan slip is a phenomenon in which there occurs a malfunction in a capstan driving system contained in the VCR; (b) if it is decided that the capstan slip has occurred, receiving a playback radio frequency (RF) signal and detecting an envelop of the playback RF signal; and (c) deciding if a level of the envelop detected equals to or less than a first predetermined value and, if so, controlling the operation of the capstan motor by correcting a capstan motor driving time to be used in controlling the operation of the capstan motor.

In accordance with another aspect of the invention, there is provided a capstan motor control apparatus for controlling the operation of a capstan motor contained in a video cassette recorder (VCR), the apparatus comprising: pulse signal generator for generating a capstan frequency generator (CFG) pulse signal when the capstan motor rotates; first control means for deciding whether or not a capstan slip has occurred based on the CFG pulse signal, wherein the capstan slip is a phenomenon in which there occurs a malfunction in a capstan driving system contained in the VCR; envelop detector, if it is decided that the capstan slip has occurred, for receiving a playback radio frequency (RF) signal and detecting an envelop of the playback RF signal; and signal converter for converting the detected envelop to a digital value corresponding thereto; second control means for deciding whether the digital value of the envelop equals to or less than a first predetermined value and, if so, controlling the operation of the capstan motor by correcting a capstan motor driving time to be used in the controlling the operation of the capstan motor.

The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which: Fig. 1 shows a schematic block diagram of a VCR incorporating therein a servo control device for controlling the operation of a capstan motor in accordance with the present invention; Figs. 2A to 2C are waveform diagrams to be used in controlling the operation of the capstan motor in a fine-slow playback mode; and Figs. 3A to 3E illustrate flow charts for explaining a method for controlling the operation of the capstan motor in accordance with the present invention.

Referring to Fig. 1, there is shown a functional block diagram of a VCR 100 incorporating therein a servo control device 40 for controlling the operation of a capstan motor 60 in a special playback mode such as a fine-slow mode, still mode, and so on in accordance with the present invention. The VCR 100 comprises a key matrix 10, an envelop detector 20, an ADC 30, the servo control device 40, a capstan motor driver 50, the capstan motor 60, a CFG pulse signal generator 70 and an on screen display (OSD) 80, wherein the servo control device 40 includes a controller 41, four counters 42-45 and three memories 46-48.

When a special playback mode, e.g., a fine-slow playback mode, is selected by a user of the VCR, the servo control device 40 of the invention controls the operation of the capstan motor 60 so that the VCR will be operated in the fineslow playback mode. Specifically, when a signal for setting the fine-slow playback mode is supplied from the key matrix 10 to the controller 41 of the servo control device 40, it first decides whether a capstan slip has occurred or not. The capstan slip, as is known in the art, is a phenomenon in which there occurs a malfunction in a capstan driving system (not shown) due to, e.g., an aging of a rubber belt located around a capstan (not shown) which is installed within the VCR 100.

To decide whether the capstan slip has occurred or not, a CFG pulse signal, as illustrated in Fig. 2B, is first received by the controller 41. The CFG pulse signal whose frequency is proportional to the rotation speed of the capstan motor 60 is generated by the CFG pulse signal generator 70 from the capstan motor 60 when it is operated in the fine-slow playback mode. As is well known, the CFG pulse signal generator 70 is mounted on a capstan rotation shaft (not shown) which is driven by the capstan motor 60. Subsequently, the controller 41 decides whether the capstan slip has occurred or not on the basis of the CFG pulse signal. If it is decided that there has occurred the capstan slip, then the controller 41 receives a DC value corresponding to an envelop level of a playback RF signal from the ADC 30. The envelop level of the playback RF signal is detected from the playback RF signal at the envelop detector 20.

Thereafter, the controller 41 compares the DC value from the ADC 30 with a first predetermined value TH1 which is prestored in the first memory 46. From the comparison, if the DC value is greater than TH1, the controller 41 initiates an inventive process to correct a capstan driving time to be used to control the operation of the capstan motor 60. The four counters 42-45 and the three memories 46-48 are advantageously used in correcting the capstan driving time. Details of the capstan driving time correction process will be provided with reference to Figs. 1, 2A, 2B, and 3A-3E hereinafter.

With reference to Figs. 3A-3E, there are depicted flow charts for explaining the method for correcting a capstan driving time to be used in controlling the operation of the capstan motor 60 in accordance with the present invention.

As illustrated in Fig. 3A, the inventive method is initiated at step S110 by checking whether the fine-slow playback mode is set or not. If it is decided that the fineslow playback mode is not set, the inventive process repeatedly performs the checking operation at step S110; and, if otherwise, the inventive process goes to step S120.

At step S120, the controller 41 first receives a capstan control pulse signal, as illustrated in Fig. 2A, read by a control head from a control track on a magnetic tape (not shown); and then executes a first interrupt routine which performs processes of steps S122, S130 and S140 shown in Fig.

3B when a part of the capstan control pulse signal, e.g., a falling edge 111 thereof, is applied to the controller 41.

At step S122, initialization is carried out, wherein the first counter 42 is initialized under the control of the controller 41. At a following step S130, a second interrupt routine is executed when a part of the CFG pulse signal, e.g., a falling edge 113 thereof, as illustrated in Fig. 2B, is received by the controller 41. A detailed description of the second interrupt routine will be given with reference to Fig. 3C hereinafter.

Turning now to Fig. 3C, there are provided details of the second interrupt routine shown in Fig. 3B. At step S132, the controller 41 receives the CFG pulse signal and provides a first counter control signal CCS1 together with the CFG pulse signal to the first counter 42. In response to the signal CCS1, the first counter 42 counts the number of pulses of the CFG pulse signal being issued after the falling edge 113 shown in Fig. 2B. It should be emphasized that the counter value of the first counter 42 is increased by 1 whenever a falling edge is applied thereto after issuance of the falling edge 113 shown in Fig. 2B.

At a next step S134, the controller 41 compares the number of pulses of the CFG pulse signal counted at the first counter 42 with a second predetermined value TH2, wherein TH2 has a value which corresponds to a duration t as illustrated in Fig. 2B. If the counted number of pulses of the CFG pulse signal is greater than TH2, meaning that the duration t has elapsed, the process follows to step S136 where the controller 41 sets a CFG over flag to 1; and, if otherwise, the process goes to step S138 wherein the controller 41 resets the CFG over flag to 0. After processing the step S136 or S138, the second interrupt routine is stopped; and then the process proceeds to step S140 shown in Fig. 3B.

Referring back to Fig. 3B, at step S140 the controller 41 executes a third interrupt routine which carries out processes of steps shown in Fig. 3D.

When the duration t has elapsed, i.e., when a rising edge 114 of the CFG pulse signal shown in Fig. 2B is applied to the controller 41, at step S142 of Fig. 3D, it checks whether the CFG over flag is set to 1 or not. If it is checked that the CFG over flag is set to 1, the process goes to step S144, wherein the controller 41 issues a second counter control signal CCS2 to the second counter 43 to increase a counter value thereof by 1. It should be noted that the counter value of the second counter 43 is increased by 1 whenever the duration t elapses within a predetermined time period. However, if otherwise, the process follows to step S146.

After processing the step S144, the process goes to step S148, wherein the increased counter value at the second counter 42 is compared with a first predetermined maximum value V1 which is prestored in the second memory 47. If the increased counter value is less than V1MU, the process directly follows to step S158 without proceeding to step S152; and, if otherwise, the process goes to step S152 where the controller 41 sets a capstan over flag to 1, meaning that the capstan slip has occurred in the capstan driving system; and then the process proceeds to step S158.

In the meanwhile, the same process as described in step S144 is carried out at step S146; and then the process goes to step S150. At step S150, the controller 41 compares the increased counter value at step S146 with a first predetermined minimum value V1MIN which is also prestored in the second memory 47. If the increased counter value is not less than V1MIN, the process directly goes to step S158 without proceeding to step S154 and, if otherwise, the process goes to step S154 wherein the controller 41 resets the capstan over flag to 0, meaning that the capstan slip has not occurred within the capstan driving system. After resetting the capstan over flag at step S154, the process goes to step S156, wherein the controller 41 issues the second counter control signal CCS2 to the second counter 43 so that the counter value thereof can be cleared to 0; and then the process follows to step S158.

At step S158, the controller 41 controls processing flows incorporated therein to prevent the second interrupt routine from operating and issues the first counter control signal CCS1 to the first counter 42 for initialization thereof; and the third interrupt routine process is stopped.

The purpose of the control of the processing flows in the controller 41 is to prevent a malfunction which can be caused due to, e.g., noises in the CFG pulse signal.

Referring back to Fig. 3A, at step S162 the controller 41 checks whether the capstan over flag is set to 1 or not.

If it is checked that the capstan over flag is not set to 1, the process follows to step S164 where the controller 41 issues a third and a fourth counter control signals CCS3 and CCS4 to the third and the fourth counters 44 and 45, respectively, for initialization thereof. However, if otherwise, the process proceeds to step S168 where the controller 41 receives the DC value of the envelop level of the playback RF signal from the ADC 30 and compares same with the first predetermined value TH1. If the DC value of the envelop level equals to or is less than TH1, the process also goes to step S164 at which the controller 41 initializes the third and the forth counters 44 and 45 and then the process stops; and, if otherwise, the process follows to step S170.

At step S170, the controller 41 issues the third counter control signal CCS3 to the third counter 44 to read a counter value thereof and compares same with a second predetermined maximum value V2B , which is prestored in the second memory 47. The second predetermined maximum value V2, is a maximum limit value which may be derived by adding a certain value to the duration t; and is decided based on the required performance of the capstan servo control in the VCR 100. From the comparison at step S170, if the third counter value is not greater than V2,,, the process goes to step S174 shown in Fig.

3E via a tap A; and, if otherwise, the process goes to-step S172 shown in Fig. 3E via a tap B.

At step S172, the controller 41 issues the fourth counter control signal CCS4 to the fourth counter 45 to read a counter value therefrom and compares same with a second predetermined minimum value V2 MiN which is also prestored in the second memory 47. The second predetermined minimum value V2 MIN is a minimum limit value which may be derived by subtracting a certain value from the duration t; and is decided based on the required performance of the capstan servo control in the VCR 100. If the fourth counter value is greater than V2MN, then the process goes to step S176; and, if otherwise, the process goes to step S178. At step S178, the controller provides the OSD 80 with a message containing contents that no correction can carried out in the inventive servo control device, to thereby visually display the message.

On the other hand, at step S174, the controller 41 reads and increases a capstan driving time stored in the third memory 48 by a preset time period, e.g., 1H, and provides a capstan motor control signal corresponding to the capstan driving time increased, as illustrated in Fig. 2C, to the capstan motor driver 50. The controller 41, at step S174, also increases the counter value of the third counter 44 by 1 to use at step S170 shown in Fig. 3A until the counter value of the third counter 44 becomes larger than V2Mx; and the process is stopped. Similarly, at step S176, the controller 41 issues a fourth control signal CCS4 to the fourth counter 45 to read and decrease the capstan driving time by 1H, provides the capstan motor control signal corresponding to the capstan driving time decreased to the capstan motor driver 50 and also decrease the fourth counter value by 1 to use it at step S172 shown in Fig. 3E until the counter value of the fourth counter 45 becomes less than V2MIN; and the whole process in the controller 41 is stopped. The capstan motor control signal derived at the controller 41 is then applied to the capstan motor driver 50 which generates a signal to be used to drive the capstan motor 60. As shown above, therefore, the present invention is capable of effectively controlling the operation of capstan motor by correcting the capstan driving time by employing the inventive capstan motor control scheme which analyzes the characteristics of the deck mechanism in the VCR 100 by detecting the occurrence of the capstan slip and further checking a level of the playback RF signal.

While the present invention has been shown and described with respect to the particular embodiment, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from the scope of the invention as defined in the appended claims.

Claims

Claims: 1. A method for controlling the operation of a capstan motor contained in a video cassette recorder (VCR), the method comprising the steps of: (a) receiving a capstan frequency generator (CFG) pulse signal generated by a CFG pulse signal in the VCR and deciding whether or not a capstan slip has occurred based on the CFG pulse signal, wherein the capstan slip is a phenomenon in which there occurs a malfunction in a capstan driving system contained in the VCR; (b) if it is decided that the capstan slip has occurred, receiving a playback radio frequency (RF) signal and detecting an envelop of the playback RF signal; and (c) deciding if a level of the envelop detected equals to or less than a first predetermined value and, if so, controlling the operation of the capstan motor by correcting a capstan motor driving time to be used in controlling the operation of the capstan motor.
2. The method of claim 1, wherein the capstan motor is controlled in a fine-slow playback mode.
3. The method of claim 1, wherein the step (a) includes the steps of: (al) receiving the CFG pulse signal and counting the number of pulses of the CFG pulse signal within a first predetermined time period; (a2) comparing the counted number of the pulses of the CFG pulse signal with a second predetermined value and, if the counted number of the pulses of the CFG pulse signal is greater than the second predetermined value, setting a capstan over flag of the CFG pulse signal to a first logic level; (a3) counting the number of the capstan over flag of the first logic level within a second predetermined time period; and (a4) comparing the counted number of the capstan over flag of the first logic level with a third predetermined value to decide whether the capstan slip has occurred or not, wherein it is decided that the capstan slip has occurred if the counted number of the capstan over flag of the first logic level is larger than the third predetermined value.
4. The method of claim 3, wherein at the step (a) the number of pulses of the CFG pulse signal is counted whenever a first falling edge of the CFG pulse signal within the first predetermined time period is received.
5. The method of claim 4, wherein the step (c) includes the steps of: (cl) if it is decided that the envelop level of the playback RF signal is less than the first predetermined value, comparing a counted value read from a first counter with a predetermined maximum value; (c2) if the counted value is less than or equals to the predetermined maximum value, controlling the operation of the capstan motor by increasing the capstan driving time by a third predetermined time period, and adding 1 to the counted value of the first counter to use it at step (cl) until the counted value becomes greater than the predetermined maximum value; (c3) if the counted value is greater than the predetermined maximum value, comparing a counted value read from a second counter with a predetermined minimum value; and (c4) if the counted value is smaller than the predetermined minimum value, controlling the operation of the capstan motor by decreasing the capstan driving time by the third predetermined time period, and subtracting 1 from the counted value to use it at step (c3) until the counted value becomes equal to or less than the predetermined minimum value.
6. The method of claim 5, wherein the step (c) further includes a step (c5) of displaying a message indicating the correction failure of the capstan slip on an on screen display (OSD) of the VCR if the counted value at the second counter is less than the predetermined minimum value.
7. The method of claim 1, after the step (b), further comprising a step (bl) of converting the envelop level of the playback RF signal to a digital value corresponding thereto.
8. A capstan motor control apparatus for controlling the operation of a capstan motor contained in a video cassette recorder (VCR), the apparatus comprising: pulse signal generator for generating a capstan frequency generator (CFG) pulse signal when the capstan motor rotates; first control means for deciding whether or not a capstan slip has occurred based on the CFG pulse signal, wherein the capstan slip is a phenomenon in which there occurs a malfunction in a capstan driving system contained in the VCR; envelop detector, if it is decided that the capstan slip has occurred, for receiving a playback radio frequency (RF) signal and detecting an envelop of the playback RF signal; signal converter for converting the detected envelop to a digital value corresponding thereto; and second control means for deciding whether the digital value of the envelop equals to or is less than a first predetermined value and, if so, controlling the operation of the capstan motor by correcting a capstan motor driving time to be used in the controlling the operation of the capstan motor.
9. The apparatus of claim 8, wherein the capstan motor is controlled in a fine-slow playback mode.
10. The apparatus of claim 8, wherein the first control means includes: means for receiving the CFG pulse signal and counting the number of pulses of the CFG pulse signal within a first predetermined time period; means for comparing the counted number of the pulses of the CFG pulse signal with a second predetermined value and, if the counted number of the pulses of the CFG pulse signal is greater than the second predetermined value, setting a capstan over flag of the CFG pulse signal to a first logic level; means for counting the number of the capstan over flag of the first logic level within a second predetermined time period; and means for comparing the counted number of the capstan over flag of the first logic level with a third predetermined value to decide whether the capstan slip has occurred or not, wherein it is decided that the capstan slip has occurred if the counted number of the capstan over flag of the first logic level is larger than the third predetermined value.
11. The apparatus of claim 10, wherein the number of pulses of the CFG pulse signal is counted whenever a first falling edge of the CFG pulse signal within the first predetermined time period is received.
12. The apparatus of claim 11, wherein the second control means includes: first comparison means, if it is decided that the envelop level of the playback RF signal is less than the first predetermined value, for comparing a counted value read from a first counter with a predetermined maximum value; means, if the counted value is less than or equals to the predetermined maximum value, for controlling the operation of the capstan motor by increasing the capstan driving time by a third predetermined time period, and adding 1 to the counted value of the first counter to use it at the first comparison means until the counted value becomes greater than the predetermined maximum value; second comparison means, if the counted value is greater than the predetermined maximum value, for comparing a counted value read from a second counter with a predetermined minimum value; and means, if the counted value is smaller than the predetermined minimum value, for controlling the operation of the capstan motor by decreasing the capstan driving time by the third predetermined time period, and subtracting 1 from the counted value to use it at the second comparison means until the counted value becomes equal to or less than the predetermined minimum value.
13. The apparatus of claim 12, wherein the second control means further includes means for displaying a message indicating the correction failure of the capstan slip on an on screen display (OSD) of the VCR if the counted value at the second counter is less than the predetermined minimum value.
14. A capstan motor driving control apparatus constructed and arranged substantially as herein described with reference to or as shown in Figs. 1, 2A-2C, and 3A-3E of the accompanying drawings.
15. A method for controlling the operation of a capstan motor substantially as herein described with reference to or as shown in Figs. 1, 2A-2C and 3A-3E of the accompanying drawings.