GB2326282A - Shallow trench isolation - Google Patents
Shallow trench isolation Download PDFInfo
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- GB2326282A GB2326282A GB9812639A GB9812639A GB2326282A GB 2326282 A GB2326282 A GB 2326282A GB 9812639 A GB9812639 A GB 9812639A GB 9812639 A GB9812639 A GB 9812639A GB 2326282 A GB2326282 A GB 2326282A
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- 238000002955 isolation Methods 0.000 title claims description 58
- 238000000034 method Methods 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims description 60
- 239000004065 semiconductor Substances 0.000 claims description 57
- 239000000758 substrate Substances 0.000 claims description 49
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 42
- 238000004519 manufacturing process Methods 0.000 claims description 29
- 238000005229 chemical vapour deposition Methods 0.000 claims description 17
- 238000001039 wet etching Methods 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 12
- 238000005498 polishing Methods 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 239000012212 insulator Substances 0.000 abstract 3
- 238000000151 deposition Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 238000005755 formation reaction Methods 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000010420 art technique Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Sidewall insulator portions 7a are formed on the sidewalls of a trench oxide structure 6a prior to a planarization process. The sidewall insulator portions prevent overetching of the trench oxide corner portions when the trench oxide and the pad oxide 2 are etched back and planarized using an isotropic wet etch. In an alternative arrangement sidewall insulator portions are not used which leads to the formation of recesses at the corner portions of the trench oxide - the recessed portions are refilled by depositing a planarized oxide layer with a subsequent etchback (see figures 5e-g).
Description
METHOD FOR PRODUClNG A SEMI CONDUCTOR DEVICE
This invention relates to a method for producing a semiconductor device. Mo More particularly, it relates to a method for forming a shallow trench isolation (STI).
Fig.6 illustrates an example of a conventional trench device isolation forming method, and is a cross-sectional view of a semiconductor substrate for schematically showing the production process step-by-step.
First, a silicon oxide film 17 is formed by thermal oxidation on a silicon substrate 16 to a film thickness of 300
A (30 nm). On the silicon oxide film 17, there is formed, as a stdp film 18 for chemical mechanical polishing (CMP), a silicon nitride film, having a polishing rate by CMP lower than that of an insulating film used for device isolation (silicon oxide film), to a film thickness of 1000 (100 nm) by chemical vapor deposition (CVD).
The role of the initially formed silicon oxide film 17 is to relieve the stress between tlic silicon nitride film as the stop film 18 and the silicon substrate 16.
Then, a mask 19 is selectively formed by a well known photolithographic technique in an area which is later converted to a diffusion layer (active region).
Then, n area not covered by the mask 19, that is the stop film 18 and the silicon oxide film 17 of the isolation regions, is removed by anisotropic etching. The silicon substrate 16 is also anisotropically etched to a depth of 3000 (300 nm) to form a trench 20 in the isolation region.
After forming the trench 20, the mask 19 is removed and a silicon oxide film as an insulating film is formed on the entire surface of the semiconductor substrate to a film thickness of 4500 (450 nm) by CVD to fill the trcnch 20.
Then, planarization is carried out by CMP until the stop film 8 on the diffusion layer (active region) is completely exposed, as shown in Fig.6c. After CMP, the stop film 18 has a film thickness is of the order of 600 A (60 nm), having been slightly polished.
As a matter of course, the upper surface of the insulating film on the isolation regions is of substantially the same height as the upper surface of the stop film 18.
Then, the stop film 18 is removed by etching, as shown in
Fig.6d.- For etching, wet etching by phosphoric acid, having a high etching selectivity of the stop film (nitride film) as compared to the silicon oxidc film, is usually employed.
The result is that an insulating film 21a, protruded approximately 600 A (60 nm) from the wafer surfacc, is produced in the isolation regions.
Thcn, the silicon oxide film 17 of a film thickness of 300 A (30 nm) is wet-etched for removing the silicon oxide film. For this wet etching, a hydrofluoric acid or a hydrofluoric acid-containing liquid, affecting the underlayer to a lesser extent, is used.
Since the insulating film 21a also is a silicon oxide film, it is also etched at this time. However, the silicon oxide film by CVD is coarser than the silicon oxide film formed by thermal oxidation, with the etching rate by wet etching being typically faster by a factor of approximately three times by CVD than that by thermal oxidation.
Thus, there is -formed a divot 22 with a radius of 300 A (30 nm) around the insulating film 21a of the isolation regions to expose the sidewall of the trench 20.
The process of formation of the divot (recess) 22 is explained with reference to Fig.7, which is a cross-sectional view showing the rim of the trench device isolating area of
Fig.6d to an enlarged scale.
If the silicon oxide film 17 with the film thickness of
300 (30 nm) by the thermal oxidation is wet-etchcd, the insulating film 21a, which is the silicon oxide film by CVD, is etched by approximately 900 (90 nm), so that the height of the upper surface is equal to that of the silicon substrate 16.
However, since the wet etching is Isotropic, it proceeds from a brokcn line 1 to a broken I inc 3 in Fig.7, around the
rim of the isolation regions, until the divot 22 is ultimately
formed, as shown in Fig.6e.
If a gate oxide film and a gate electrode are formed in
this state for fabricating a transistor, there is formed unintentionally a transistor, on the trench sidewall of the diffusion layer (active region) and in particular at a corner where the electrical field is concentrated as discussed by
Andres Bryant in a thesis ("Characteristics of CMDS Device
Isolation for the ULSI Age" IDEM Tech. Dig., p.671, 1994),
thus producing adverse effects, known as humps or kinks, on
inherent transistor characteristics.
There are also occasions where, in etching the gate electrode, the gate electrode material- is left in the divot in the form of side walls due to sharp step difference by the divot to give rise to shorting across gate electrodes.
As discussed above, since a divot is produced around the
isolation region with the conventional trench device isolation
forming method, there is unintentionally formed a transistor
in the trench sidewall of the diffusion layer (active region),
in particular at a corner where the electrical field is concentrated, thus giving rise to adversc effects termed humps or kinks on the inherent transistor characteristics.
There are also occasions wherein, in gate etching, the gate electrode material is left in the divot in the form of
sidewalls due to sharp step difference by the divot to give rise to shorting across gate electrodes.
In view of the above-described problems of the prior art,
embodiments of the present invention aim to provide a method for producing a semiconductor device in which, in wet etching the silicon oxide film on the semiconductor substrate during formation of the shallow trench isolation (STI), the first insulating layer of the isolation region is prevented from being etched to produce a divot at the isolation end region to improve the yield, reliability and productivity of the semiconductor device.
.Further aims will become apparent in the entire
disclosure.
For accomplishing the above object, the present invention generally resides in selectively forming an insulating film in a trench rim portion where a divot is likely to be produced for preventing the divot from being produced, or in forming a divot and subsequently selectively forming an insulating film in this divot for eliminating the divot prior to formation of the gate oxide film.
One aspect of the present invention
provides a method for producing a semiconductor device including (a) forming a stop film for planarization over a semiconductor substrate, (b) removing the stop film of isolation regions by etching and further etching the semiconductor substrate to form a trench, (c) forming a first
insulating filmon the semiconductor substrate to fill the
trench, (d) removing the first insulating film on the stop
film by planarization, (e) removing the stop film, (f)
forming a second insulating film after removing the stop
film and before forming a gate oxide film and (g) etching the
second insulating film.
First and second insulating films may be formed by chemical vapor deposition (CVD).
Planarization may be achieved by chemical mechanical polishing (CMP).
Etching of the second insulating film may be carried out by isotropic etching. Preferably, the etching is wet etching.
The second insulating film may be a silicon oxide film.
The invention may be carried into practice in various ways, but embodiments will now be described by way of example only, with reference to the accompanying drawings, in which:
Figs. la to 1d are cross-sectional process views for illustrating the manufacturing method of a first embodiment of the present invention.
Figs.2e to 2g are cross-sectional process views for illustrating the manufacturing method of the first embodiment of the present invent ion.
Fig.3 is a cross - sectional view of a semiconductor substrate showing an isolation elld port ion.
Figs. 4a to 4d are cross - sect iona 1 process views for illustrating the manufacturing method of a second embodiment of the present invention.
Figs. Se to 5g are cross-sectional process views for illustrating the manufacturing method of the second embodiment of the present invention.
Figs. 6a to 6e are cross-sectional process views for illustrating the manufacturing method for known shallow trench isolation (STI).
Fig.7 is a cross-sectional view of a semiconductor substrate showing the isolation end portion to an enlarged scale.
Preferred embodiments of the present invention are hereinafter explained. In its preferred form, there is provided a method for producing a semiconductor device in which a first insulating film is buried in a trench provided in a semiconductor substrate and a shallow trench isolation region is formed by planarization. In this method, after planarizat ion and removing a stop film for planarization, and before forming a gate elect rodc, a second insulating film is formed, and wherein this second insulating film is etched to selectively leave the second insulating film around thc sidewall of the first insulating film protruded from the substrate surface of the shallow trench insulation rcgion in a fashion to prevent a divot from being formed around the shallow trench isolation region during the next following etching process.
More specifically, there is provided a method for producing a semiconductor device. The method comprises: (a) a step for forming a stop film for planarization (3 of Fig.1) over a semiconductor substrate (1 of Fig.1) via a silicon oxide film (2 of Fig.1) as a stress-relieving insulating film see Fig.1a), (b) a step for removing the stop film (3 of Fig.1) and the silicon oxide film (2 of Fig.1) in isolation regions by etching and further etching the semiconductor substrate (1 of Fig.1) to form a trench (5 of Fig.1), and forming a first insulating film (6 of Fig.1) on the semiconductor substrate to fill the trench (see Fig.lb). The method further comprises: (c) a step of removing the first insulating film (6 of Fig.1) on the stop film (3 of Fig.1) by planarization (see Fig.lc), (d) a step of removing the stop film (see Fig.ld), (e) a step of forming a second insulating film (7 of Fig. 2) after removing the stop film and before forming a gate oxide film (see Fig.2e), (f) a step of removing the second insulating film by etching (see Fig.2f), and (g) a step of removing the silicon oxide film (2 of Fig.1) on etching (see Fig.2g).
Also, there is provided a method for producing a semiconductor device in which a first insulating film is buried in a trench provided in a semiconductor substrate and a shallow trench isolation region is formed by planarizat ion.
In this method, after planarization, an insulating film for stress relieving between the semiconductor substrate and the stop film is removed by etching after removing a stop film for planarization, and before forming a gate electrode, and subsequently a second insulating film is formed to fill a divot around the shallow trench isolation region formed at the time of removal of the stress-relieving insulating film -by etching to prevent a divot from being formed around the shallow trench isolation region during the subsequent etching process.
More specifically, there is provided a method for producing a semiconductor device comprising: (a) a step for forming a stop film for planarization (10 of
Fig.4) over a semiconductor substrate (8 of Fig.4) via a stress-relieving silicon oxide fi]m (9 of Fig.4) (see
Fig.4a), (b) a step for removing the stop film and the stressrelieving insulating film in a isolation regions by etching, and ctching the semiconductor substrate to form a trench (12 of Fig.4), and forming a first insulating film over the semiconductor substrate lo fill the trench (see Fig.4b) (c) a step of removing the first insulating film on the stop
film by planarization (see Fig.4c),
(d) a step of removing the stop film (see Fig.4d),
(e) removing the silicon oxide film (9 of Fig.4) by etching after removing the stop film (see Fig.Se),
(f) forming a second insulating film (15 of Fig.5) to cover
the divot around the trench produced by the step (e) ( Fig.Sf), and (g) removing the second insulating film by etching (Fig.Sg).
In the embodiments of the present invent ion, the first and second insulating films are formed preferably by CVD, while planarization is performed by CQP (chemical mechanical polishing). The second insulating film is preferably etched by wet etching.
In the embodiments of the present invention, since the divot around the shallow trench isolation region is eliminated before forming the gate oxide film, it is possible to eliminate humps in transistor characteristics or residual step difference at the time of etching the gate electrode.
DETAILED DESCRIPTION OF THE EMBODIMENTS
Referring to the drawings, preferred embodiments of the present invention will be explained in detail.
First Embodiment
Referring to the drawings, a first embodiment of the present invention is explained. Figs .1 and 2 illustrate the manufacturing method of the first embodiment of the present invention and are cross - sectional process views of the semiconductor substrate step-by-step. Figs 1 and 2 are divided simply for convenience in preparing the drawings.
Referring first to Fig.la, a silicon oxide film 2 is formed to a film thickness of 300 A (30 nm) by thermal oxidation on a silicon substrate 1. On the silicon oxide film 2, a silicon nitride film, as a stop film for CMP 3, having a polishing rate by CMP smaller than that of the insulating film used for device isolation (silicon oxide film in the present embodiment) is formed by CVD to a film thickness of 1000 (100 nm). The role of the initially formed silicon oxide film 2 is to relieve the stress between the silicon nitride film as the stop film 3 and the silicon substrate 1.
Then, by a well-known photolithographic technique, a mask 4 is selectively formed in an area which later serves as a diffusion layer (active region).
The portions of the stop film 3 and the -silicon oxide film 2 not covered by the mask 4, that is in the device isolating area, are then removed by anisotropic etching. The portion of the silicon substrate 1 in the device isolating area is then anisotropically etched to a depth of 3000 A (300 nm) to form a trench 5 in the isolation region.
After forming the trench 5, the mask 4 is removed, and a silicon oxide film as a first insulating film 6 is formed on the entire surface of the semiconductor substrate to a film thickness of 4500 A (450 nm) by CVD to fill the trench 5.
Then, planarization by CMP is carried out until the stop film 4 on the diffusion layer (active region) is exposed completely, as shown in Fig.1c.
Through the CMP, the stop film 3 is also polished to a film thickness equal to 600 A (60 nm). As a matter of fact, the upper surface of the first insulating film 6a on the isolation region is substantially of the same height level as the upper surface of the stop film 3.
Then, the stop film 3 is removed by etching, as shown in Fig.ld. This etching is usually wet etching by phosphoric acid which has a high selection ratio relative to the silicon oxide film.
The result is that a first insulating film 6a, protruded by a height of 600 A (60 nm) from the wafer (substrate) surface, is formed in the isolation region.
Then, a silicon oxide film as a second insulating film 7 is formed to a film thickness of 600 A (60 nm) on the semiconductor substrate.
The second insulating film 7, with the film thickness of 600 A (60 nm), is removed by etching, as shown in Fig.2f. As
the etching technique, wet etching by a hydrofluoric acidbascd etching solution, which damages the under layer to a lesser extent, is used in the present embodiment.
Thus, in the planar portion, the second insulating film 7 is eliminated, while only the first silicon oxide film 2 is left. However, on the end of the isolation region (sidewall section of the first insulating film 6a), an insulating film 7a is left on the silicon oxide film 2.
This process is explained with reference to Fig.3 showing the end of the isolation region of Fig.2e to an enlarged scale.
In a planar portion, excluding the initially formed silicon oxide film 2, there is formed the second insulating film 7 to a film thickness of 600 (60 nm), while the second insulating film 7 of (4;2)x 850 (85 nm) is formed at an angle of 45 degrees from the horizontal from a corner at the end of the isolation regions.
If wet etching is carried out with 600 (60 nm), the second insulating film 7 on the planar portion is eliminated.
However, at an angle of the end of the isolation regions, the insulating film 7a of ( r2) x 600 - 600 A i 250 A (25 nm) is left at the corner of the end of the isolation regions.
The silicon oxide film 2 is then removed by etching, as shown in Fig. 2g. Although the first insulating film 6a is etched by 600 A (60 nm), the divot of the first insulating film 6a is of the order of 50 A (50 nm) in radius so that it raises no problem.
Therefore, even if subsequently the gate oxidation or format ion of a gate electrode is performed, there is raised no problem such as humps in transistor characteristics or residual gate electrode material.
In the present embodiment, the second insulating film 7a is transiently left at the end of the isolation regions and subsequently the silicon oxide film 2 is removed. This, however, is merely for convenience in explanation. That is, in the present embodiment, the second insulating film 7 also is an oxide film, such that, in actual fabrication, there is of course, no essential difference if the two etching operations are carried out at a time.
Second Embodiment
The second embodiment of the present invention is now explained with reference to the drawings. Figs.4 and S are cross-sectional views of a semiconductor substrate schematically showing the process for fabricating the semiconductor substrate step-by-step. Figs.4 and 5 are split only for convenience in drawing.
First, as shown in Fig.4a, a silicon oxide film 9 is formed to a film thickness of 300 A (30 nm) by thermal oxidation on a silicon substrate 8, whereas a silicon nitride film, having a CMP polishing rate lower than that of the insulating film used for device isolation (silicon oxide film in the present embodiment) is formed by CMP as a CMP stop film 10 on the silicon oxide film 9. The role of the initially formed silicon oxide film 9 is to relieve the stress between the silicon nitride film as the stop film 10 and the silicon substrate 8.
Then, by a well-known photolithographic technique, a mask 11 is selectively formed in an area which late serves as a diffusion layer (active region).
The portions of the stop film 10 and the silicon oxide film 9 not covered by the mask 11, that is in the isolation regions, are then removed by anisotropic etching. The portion of the silicon substrate 1 in the isolation regions is then anisotropically etched to a depth of 3000 A (300 nm) to form a trench 12 in the isolation region.
After forming the trench 12, the mask 11 is removed, and a silicon oxide film as a first insulating film 13 is formed on the entire surface of the semiconductor substrate to a film thickness of 4500 A (450 nm) by CVD to fill the trench 5.
Then, planarization by CMP is carried out until the stop film 10 on the diffusion layer (active region) is exposed completely. Through CMP, the stop film 10 is also polished so that its film thickness is equal to 600 A (60 nm). As a matter of fact, the upper surface of the first insulating film 13a in the isolation regions is substantially of the same height level as the upper surface of the stop film 10.
Then, the stop film 10 is removed by etching, as shown in
Fig.4d. This etching is usually wet etching by phosphoric acid which has a high selection ratio relative to the silicon oxide film. The result is that a first insulating film 13a, protruded by a height of 600 (60 nm) from the wafer (substrate) surface, is formed in the isolation regions.
Then, wet etching by 300 (30 nm) is carried out to remove the silicon oxide film 9, as shown in Fig.Se.
Thus, there is formed a divot 14 with a radius of 300 (30 nm) around the first insulating film 13a of the isolation regions to expose the sidewall sect ion of the trench, as explained with reference to the prior art technique.
Then, as shown in Fig.5f, preferably a silicon oxide film is formed as a second insulating film 15 by CVD to a film thickness of 1000 A (100 nm) to fill the divot.
The second insulating film 15, with the film thickness of 1000 (100 nm), is removed by etching, as shown in Fig.Sf. As the etching technique, wet etching by a hydrofluoric acid based etching solution, which damages the under layer to a lesser extent, is used in the present embodiment.
In the rim of the first insulating film 13a of the isolation region where there was the divot 14, the second insulating film 15a remains, thus realizing divot-free shallow trench isolation (STI). Thus, in the present embodiment, it is also possible to prevent humps or residual steps of the fate electrode.
According to the present invention, since the divot at the rim of the shallow trench isolation region is removed, it is possible to prevent adverse effects, such as humps or kinks, from affecting the electrical characteristics of the transistor. In addition, etching residues in the form of sidewalls otherwise produced at the time of gate etching can be eliminated to improve yield and reliability.
Claims (14)
1. A method for producing a semiconductor device
comprising:
(a) forming a stop film for planarization over a semiconductor substrate;
(b) removing said stop film of isolation regions by etching
and further etching said semiconductor substrate to form a
trench;
(c) forming a first insulating film on said semiconductor
substrate to fill said trench;
(d) Temoving said first insulating film on said stop film by planarizat ion; (e) removing said stop film;
(f) forming a second insulating film after removing said stop
film and before forming a gate oxide film; and
(g) etching said second insulating film.
2. The method for producing a semiconductor device as defined
in claim 1 wherein said first and second insulating films are
formed by chemical vapor deposition (CVD).
3. The method for producing a semiconductor device as defined
in claim 1 or claim 2 wherein said planarization is achieved
by chemical mechanical polishing (CMP).
4. The method for producing a semiconductor device as defined
in claim 2 wherein etching of said second insulating film is
carried out by isotropic etching.
5. The method for producing a serniconductor device as defined in claim 3 wherein said etching is wet etching.
6. The method for producing a semiconductor device as defined in claim 4 wherein said second insulating film is a silicon oxide film.
7. A method for producing a semiconductor device in which a first insulating film is buried in a trench provided in a semiconductor substrate and a trench isolation regions is formed by planarization,
wherein, after planarizat ion and removing a stop film for planarizat ion, and before forming a gate electrode, a second insulating film is formed, and
wherein this second insulating film is etched to selectively leave said second insulating film around the sidewall of the first insulating film protruded from the substrate surface of the trench device insulating area, in a fashion to prevent a divot from being formed around the trench isolation region during the next following etching process.
8. A method for producing a semiconductor device in which a first insulating film is buried in a trench provided in a semiconductor substrate and a trench isolation regions is formed by planarization,
wherein, after planarization and removing a stop film for planar iza t ion, and before forming a gate electrode, an insulating filin for stress relieving between the semiconductor substrate and said stop film is removed by etching, and
wherein subsequently a second insulating film is formed to fill a divot around the shallow trench isolation (STI) area formed at the time of removal of the stress-relieving insulating film by etching in a fashion to prevent a divot from being formed around the trench isolation region during the next following etching process.
9. A method for producing a semiconductor device comprising: (a) forming a stop film for planar izat ion over a semiconductor substrate via a stress-relieving insulating film; (b) removing said stop film and the stress-relieving insulating film in a isolation regions by etching and further etching said semiconductor substratc to form a trench; (c) forming a first insulating film over said semiconductor substrate to fill said trench; (d) removing said first insulating film on said stop film by planarization; (e) removing said stop film; (f) forming a second insulating film after removing said stop film and before forming a gate oxide film; (g) removing said second insulating film by etching in a fashion to leave part of said second insulating film at a corner of the first insulating film at an end of the isolation regions; and (h) removing the stress-relieving insulating film on etching.
10. A method for producing a semiconductor device comprising: (a) forming a stop film for planarization over a semiconductor substrate via a stress-relieving insulating film; (b) removing said stop film and the stress-relieving insulating film of a isolation regions by etching and further etching said semiconductor substrate to form a trench; (c) forming a first insulating film over said semiconductor substrate to fill said trench; (d) removing said first insulating film on said stop film by planarizat ion; (c) removing said stop film; (f) removing said stress-relieving insulating film by etching after removing said stop film; (g) forming a second insulating film on an cntire substrate surface to fill the divot at the end of the isolation region; aiid (h) removing the second insulating film by etching.
11. The method for producing a semiconductor device as defined in any one of claims 7 to 10 wherein said first and second insulating ti lnis are formed by chemical vapor deposition (CVD) method.
12. The method for producing a semiconductor device as defined in any one of claims 7 to 10 wherein said planarization is by chemical mechanical polishing (CMP).
13. The method for producing a semiconductor device as - defined in any one of claims 7 to 10 wherein said etching of the second insulating film is performed by wet etching.
14. A method for producing a semiconductor device, the method being substantially as herein described, with reference to
Figures 1 to 5 and 7 of the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0002618A GB2344465B (en) | 1997-06-13 | 1998-06-11 | Method for producing a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9172866A JP3063686B2 (en) | 1997-06-13 | 1997-06-13 | Method for manufacturing semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9812639D0 GB9812639D0 (en) | 1998-08-12 |
| GB2326282A true GB2326282A (en) | 1998-12-16 |
| GB2326282B GB2326282B (en) | 2001-01-31 |
Family
ID=15949761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9812639A Expired - Fee Related GB2326282B (en) | 1997-06-13 | 1998-06-11 | Method for producing a semiconductor device |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6197657B1 (en) |
| JP (1) | JP3063686B2 (en) |
| KR (1) | KR100307651B1 (en) |
| CN (1) | CN100334707C (en) |
| GB (1) | GB2326282B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2351842A (en) * | 1999-05-14 | 2001-01-10 | Nec Corp | Method of forming a shallow trench isolation structure without divots in a semiconductor substrate |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7291884B2 (en) * | 2001-07-03 | 2007-11-06 | Siliconix Incorporated | Trench MIS device having implanted drain-drift region and thick bottom oxide |
| US20060038223A1 (en) * | 2001-07-03 | 2006-02-23 | Siliconix Incorporated | Trench MOSFET having drain-drift region comprising stack of implanted regions |
| US7009247B2 (en) * | 2001-07-03 | 2006-03-07 | Siliconix Incorporated | Trench MIS device with thick oxide layer in bottom of gate contact trench |
| US7033876B2 (en) * | 2001-07-03 | 2006-04-25 | Siliconix Incorporated | Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same |
| KR100489525B1 (en) * | 2002-04-16 | 2005-05-16 | 동부아남반도체 주식회사 | Method for preventing divot form a time spacer formation |
| KR100476934B1 (en) * | 2002-10-10 | 2005-03-16 | 삼성전자주식회사 | Method of forming semiconductor device having trench device isolation layer |
| US7037794B2 (en) * | 2004-06-09 | 2006-05-02 | International Business Machines Corporation | Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain |
| CN102148181B (en) * | 2010-02-10 | 2014-10-22 | 上海华虹宏力半导体制造有限公司 | Method for forming shallow trench isolation structure |
| DE102011005719A1 (en) * | 2011-03-17 | 2012-09-20 | Globalfoundries Dresden Module One Llc & Co. Kg | Increased integrity of large ε metal gate stacks by reducing STI settlements by depositing a filler after STI fabrication |
| JP2014063895A (en) * | 2012-09-21 | 2014-04-10 | Asahi Kasei Electronics Co Ltd | Method for manufacturing semiconductor device |
| CN104362097A (en) * | 2014-11-05 | 2015-02-18 | 上海华力微电子有限公司 | Manufacturing method of fin field-effect transistor |
| CN104347427A (en) * | 2014-11-05 | 2015-02-11 | 上海华力微电子有限公司 | Method for manufacturing fin field effect transistor (FET) |
| CN104332410B (en) * | 2014-11-05 | 2017-12-22 | 上海华力微电子有限公司 | A kind of manufacture method of fin formula field effect transistor |
| CN105869991B (en) * | 2015-01-23 | 2018-05-11 | 上海华力微电子有限公司 | Method and system for the uniformity for improving SiGe thickness |
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| US5433794A (en) * | 1992-12-10 | 1995-07-18 | Micron Technology, Inc. | Spacers used to form isolation trenches with improved corners |
| US5506168A (en) * | 1992-10-27 | 1996-04-09 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device |
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| EP0055521B1 (en) * | 1980-11-29 | 1985-05-22 | Kabushiki Kaisha Toshiba | Method of filling a groove in a semiconductor substrate |
| US5229316A (en) * | 1992-04-16 | 1993-07-20 | Micron Technology, Inc. | Semiconductor processing method for forming substrate isolation trenches |
| US5358891A (en) | 1993-06-29 | 1994-10-25 | Intel Corporation | Trench isolation with planar topography and method of fabrication |
| US5387540A (en) * | 1993-09-30 | 1995-02-07 | Motorola Inc. | Method of forming trench isolation structure in an integrated circuit |
| JPH07176607A (en) | 1993-12-21 | 1995-07-14 | Toshiba Corp | Fabrication of semiconductor device |
| JPH08330410A (en) | 1995-05-31 | 1996-12-13 | Sony Corp | Element isolating method, element isolating structure and semiconductor device |
| US5933748A (en) | 1996-01-22 | 1999-08-03 | United Microelectronics Corp. | Shallow trench isolation process |
| KR100216267B1 (en) * | 1996-12-26 | 1999-08-16 | 구본준 | Method for manufacturing semiconductor device using shallow trench isolation |
| JPH118295A (en) | 1997-06-16 | 1999-01-12 | Nec Corp | Semiconductor device and its manufacture |
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- 1997-06-13 JP JP9172866A patent/JP3063686B2/en not_active Expired - Fee Related
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- 1998-06-03 CN CNB981022162A patent/CN100334707C/en not_active Expired - Fee Related
- 1998-06-11 US US09/095,497 patent/US6197657B1/en not_active Expired - Lifetime
- 1998-06-11 KR KR1019980021618A patent/KR100307651B1/en not_active IP Right Cessation
- 1998-06-11 GB GB9812639A patent/GB2326282B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US5506168A (en) * | 1992-10-27 | 1996-04-09 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device |
| US5433794A (en) * | 1992-12-10 | 1995-07-18 | Micron Technology, Inc. | Spacers used to form isolation trenches with improved corners |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2351842A (en) * | 1999-05-14 | 2001-01-10 | Nec Corp | Method of forming a shallow trench isolation structure without divots in a semiconductor substrate |
| US6372602B1 (en) | 1999-05-14 | 2002-04-16 | Nec Corporation | Method of forming a shallow trench isolation structure in a semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9812639D0 (en) | 1998-08-12 |
| CN1202726A (en) | 1998-12-23 |
| US6197657B1 (en) | 2001-03-06 |
| CN100334707C (en) | 2007-08-29 |
| JPH118296A (en) | 1999-01-12 |
| GB2326282B (en) | 2001-01-31 |
| KR100307651B1 (en) | 2001-11-30 |
| KR19990006860A (en) | 1999-01-25 |
| JP3063686B2 (en) | 2000-07-12 |
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| Date | Code | Title | Description |
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| 732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20040611 |