GB2325120A

GB2325120A - Communications systems

Info

Publication number: GB2325120A
Application number: GB8216662A
Authority: GB
Inventors: Christopher James Rigden
Original assignee: UK Secretary of State for Defence
Current assignee: UK Secretary of State for Defence
Priority date: 1981-06-30
Filing date: 1982-06-09
Publication date: 1998-11-11
Anticipated expiration: 2002-06-09
Also published as: GB2325120B; GB8216662D0; GB8120186D0; DE3224401C1

Abstract

A slow data rate digital communications signal (2) is multiplexed with a two-tone frequency shift keyed (FSK) primary communications signal (1) by modulation of at least one of the FSK frequencies. Preferably, the slow data channel operates at a frequency of 1 baud and modulates the primary signal by applying a 1 Hz frequency shift to both tones of the primary signal. In the transmitter a reference frequency signal (3) is applied to a frequency synthesiser (7-10, 15) to produce the four frequencies required, and to provide the necessary signals for timing gates (13, 14) to ensure that the slow data is added to the primary data with phase coherence. The receiver (fig. 2, not shown) includes a local oscillator (21) tuned to one of the two primary communications tones. After detection (16-19) the received signals and the locally generated signal are compared in a phase comparator (20) and then filtered (22) to separate the two communications channels (24, 25).

Description

The invention relates to very low frequency (VLF) and low frequency (IF) communications systems and in particular to the provision of a slow data rate channel for operation at these frequencies.

The very low frequency (ELF) and low frequency (LF) bands of radio frequencies cover the range from 3 kRz to 300 kHz. - These frequencies are used for long range communication and navigation because of their stable and relatively predictable propagation. These frequencies also represent the lowest which can be transmitted without having aerials of colossal proportions. The Rugby transmitter radiating at 16 kHz, for example, has an aerial consisting of several masts each 840 feet high.

A common method of data transmission on VIF and EF transmitters is two tone frequency shift keying (FSK). The carrier is switched between two frequencies, usually 50 Hz apart, one frequency denoting a mark and the other frequency a space.

There remains a need, however, for increased range performance particularly when applied to communication with submerged submarines.

The object of the present invention is to provide a second slow data rate channel which can run concurrently with a conventional VLF or IF communications channel to provide an increased range of communication without affecting the conventional VLF or IF operation.

In a first respect the invention consists of a communications transmitter comprising a means to encode a first signal using two discrete frequencies for transmission at a first rate, means to encode a second signal for transmission at a second slower rate, the ratio of the two rates being an integer, and means to combine the first and second signals with posse coherence whereby at least one of the two discrete frequencies of the first signal is modulated by the second signal, Thus by adding a second slow data channel to a conventional communications channel the narrower bandwidth of the second channel produces a consequent range increase for the same transmitted power. In addition where a conventional 50/75 baud FSit8ystem is used to communicate with a submarine the addition of a slow data channel improves the depth performance, Preferably both of the discrete frequencies are modulated by the second signal. this meets the phase coherence requirements of VLF transmitters and also means that the second signal will be present all the time rather than Just 50% of the time if only one of the two discrete frequencies were modulated.

The modulation of the two discrete frequencies by the second slow data channel preferably involves a shift of frequency of both of the discrete frequencies. In an alternative form the modulation may involve a phase shift.

Advantageously the first signal is frequency shift keyed with one of the discrete frequencies representing a mark and the other frequency representing a space in the encoded first signal, and the second signal is a modulation of the first signal such that a mark is represented by an equal change of the two discrete frequencies. Thus there will be four frequencies produced by the transmitter. Preferably a single reference frequency source is used to generate the frequencies for transmission of the two signals and to generate switching signals for the coherent modulation. In a convenient arrangement the reference frequency is used to drive two bi-stable circuits at the respective frequencies of data transmission of the first signal and the second signal, the outputs from the two bi-stable circuits being used to produce the switching signals.

Advantageously the four frequencies are produced by connecting the reference frequency to a phase locked loop, connecting the output from the phase locked loop to a programmable divider and selectably programming the divider to produce an appropriate one of the four frequencies. In the preferred arrangement the first signal is transmitted at 50 baud and the second slow data signal is transmitted at 7 bad.

In a further aspect the invention consists of a communications receiver for receiving a first signal transmitted at a first rate on two discrete frequencies and a second signal transmitted as a slower rate second modulation of the first signal comprising circuit means to detect the transmitted signals, means to generate an electrical output signal at one of the two discrete frequencies, comparator means to compare the detected signals with the generated signal and produce a difference output, and filter means to seParate the first and second signals from the difference output. Advantageously the detector means is an r.f. amplifier which may include a band-pass filter to improve the sensitivity of the receiver.

Preferably the received signals and the generated signal are compared in a phase comparator. Advantageously the r.f. amplifier includes a limiter to reduce the amplitude sensitivity of the receiver.

The invention will now be described by way of example only with reference to the following drawings of which: Figure 1 is a block diagram of a transmitter according to the invention; Figure 2 is a block diagram of a receiver according to the invention; Figures x and 4ii(;iiare detailed circuit diagrams of the transmitter shorn in Figure 1; and Figures 4 to 7 are detailed circuit diagrams of the receiver shown in Figure 2.

In a typical frequency shift keyed (FSK) modulation system the transmitted signal is switched between a first tone (A tone) and a second tone (Z tone).

It is necessary that switching from one tone to the other is done in phase so that large transient currents and voltages are not produced in the transmitter output circuits. This is done by ensuring that each bit is an exact whole number of cycles in length. In the Rugby FSK system for example, the A tone is 16 kEz, the Z tone is 15,950 Hz, and each bit is 20 ms in length corres- ponding to 320 cycles of A tone or 319 cycles of Z tone, ie data is transmitted at a rate of 50 baud.

In the arrangement of the invention shown in in Figure 1, a first FSK encoded communications signal at a data rate of 50 baud is connected to an input 1 to a transnitter to determine the switching between the A tone and the Z tone as in a conventional FSK transmission signal. A second encoded signal for tranmission at a slow data rate is connected to an input 2 to produce a 1 Sz shift on both components of the first FSK signal. The slow data rate input is switched once a second corresponding to a 1 baud data rate. A programmable frequency synthe siser is used to generate the necessary frequencies 16,000 Hz (A tone) 16,001 Hz, 15,950 Hz (Z tone) and 15,951 Hz. A 16 kHz frequency standard signal 3 is connected via an input buffer 4 to a divide-by-32 circuit 5.

The 500 Hz output 6 is provided as an input to a phase locked loop (PPL) 7. The output from the PPL 7 is amplified by an amplifier 8 and connected to a divide-by-n circuit 9. The divide-by-n circuit 9 controls the frequency of the phase locked loop such that the output signal after passing through a divide-by-500 circuit is selectably equal to ne of tb. four required frequencies. The 500Hz signal at the output 6 is passed through a divide-by-l0 circuit 11 and a divide-by-50 circuit 12 to respectively provide a 50 Hz control signal for a timing control gate 13 for the FSK data input 7 and a 1 Hz control signal for a timing control gate 14 for the slow data input 2.

The FSK signal and the slow data signal are thus synchronised by their respective timing control gates to the 16 kHz frequency standard. These two synchronised signals are passed through a divider control circuit 15 to the divide-by-n circuit 9 such that the appropriate frequency is produced at the signal output from the PPL 7.

A receiver for demodulating the transmitted signal is shown in Figure 2.

A signal received by the aerial 16 is passed through an adjustable attenuator 17 which provides up to 40 db attenuation. The signal is then amplified by a radio frequency (r. f.) amplifier 78 which includes a sensitive FET input first stage amplifier, and a second stage amplifier and limiter. A band-pass (BP) filter 19 can be switched into the r.f. amplifier 18 between the first and second amplifier stages. The 3P filter 19 is arranged to be tunable over the range 14.5 kHz to 20 kEz and the Q of the filter is adjustable. A Q of 200 has been found to be suitable. The output from the r.f. amplifier 18 is connected to one input of a phase comparator 20. A frequency synthesiser 21 is connected to a second input of the phase comparator 20 whereby a frequency standard can be compared with the received r.f. signal. The frequency synthesiser 21 provides a 16 kEz output signal, the same basic frequency as the transmitter, which is compared with the received r.f. signal in the phase comparator 20.

A square wave output is produced by the phase comparator 20 at the sum frequency of the two inputs. The mark/space ratio of the square wave varies according to the phase relationship. The square wave output is filtered by a filter circuit 22 to provide three outputs: an unfiltered output 23, a low pass output 24 filtered at about 100 Hz and an output 25 filtered at about 1 Hz.

Thus the conventional 50 baud signal is provided at the output 24 and the low data rate 1 baud signal is provided at the output 25.

Figures 3 and 4(i)-4(iii) show detailed circuit diagrams of the transmitter shown in Figure 1 with like reference numerals used to indicate like integers, and with the reference letters a - f representing the break points made in the circuits for clarity. The blocks shown in the figures represent co-nercially available integrated circuits. The 16 kHz reference sine-wave signal input 3 is connected to a Schmitt trigger buffer input circuit 4 which has a 22 nF external timing capacitor 26.

The Schmitt trigger converts the input reference signal into a digital output which is connected to the divide-by-32 circuit 5. The division is done by means of four stages of divide-by-2 in the circuit 27 and a further divideby-2 in the circuit 28. The 500 Hz signal at the output 6 is used as an input 29 for generating the four frequencies required by the FSK and slow data rate signals, and for controlling the signal timing gates to synchronise the signals. The 50 Hz timing signal 30 is obtained from the 500 Hz signal as in Figure 1 by the decade counter 11, and further division by 50 by the decade counters 31 and 32 produces the 1 Hz timing signal 33. The 50 Hz timing signal 30 is connected via a Schmitt trigger 34 to a first input 35 of a JK flip-flop in an integrated circuit 36 comprising two JK flip-flops. An external resistor 37 and a capacitor 38 connected to the Schmitt trigger 34 are selected to give an output pulse length which is narrow compared with the pulse length of the 1 Hz timing signal 33. The 1 Hz timing signal 33 is connected to a second input 39 to the second JK flip-flop of the integrated circuit 36. Thus the two flip-flops are made to oscillate respectively at 50 Hz and 1 Hz. The 50 baud signal and its complement are respectively connected from the input 1 to the inputs 40 and 41 of the circuit 36 after amplification and shaping by an amplifier 42.

An inverter 43 produces the complement signal at the input 41. The slow data signal is connected from the input 2 via a switch 44 to the input 45 of the circuit 36. An inverter 46 connects the complement of the slow data signal to a further input 47 of the circuit 36. Programming output signals are produced at the outputs 48 - 50 of the flip-flop circuit 36 for connection to the programmable divider so as to produce the appropriate frequencies for transmission as will be described later. Light emitting diodes 51 - 53 are connected to outputs 48 - 50 and a diode 54 is connected to the output 55 to enable the 50 baud and slow data signals to be monitored. Thus the two flipflops in the circuit 36 change the signals at outputs 48 - 50 in dependence on the 50 baud and 1 baud slow data input signals with the output changes being synchronised in dependence on the timing signals 33 and 35. The mark and space in the 50 baud signal are respectively represented by the diodes 53 and 52 while the diodes 51 and 54 indicate the slow data mark and space.

The operation of the timing gates and programmable divider control can be understood with reference to the Table below which gives the binary numbers required by the programmable divider to give the necessary output frequencies for a given inp-tit freuency. The columns each represent the required state 0 or 1 of rn an output ut to zoo the divider to give one of the frequencies in the firs column. The inputs where no change of state is required to switch between the four frequencies, that is, those in groups E and C, are wired to 0 volts for TABLE

data bit frequency (Hz) 215 214 213 212 211 210 29 28 27 26 25 24 2 2 2 1 A 16000 0 1 1 1 1 | 1 | 1 0 1 0 0 0 0| 0 0 0 Ao 16001 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 Z 15950 0 1 1 1 1 1 1 0 0 1 0 0 1 1 1 0 Zo 15951 0 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 E D C B A a zero and +5 volts for a one. A change from an A or Ao to a Z or Zo is accomplished by changing the state of inputs in groups D and B to their complement. Similarly a change from A or Z to Ao or Zo is made by changing the state of the input in group A from 0 to 1. To synchronise the timing pulses for the frequency changes the 1 Hz and 50 Hz timing signals 33 and 35 are used to clock the two JK flip-flops on the integrated circuit 36 as described earlier. One JK flip-flop is thus clocked at 50 Hz for the A to Z or Ao to Zo switching and the other JK flip-flop is clocked at 1 Hz for the A to Ao or Z to Zo changes. The integrated circuit 36 has complementary Q and Q outputs from the flip-flops and thus Q of one flip-flop (output 49) is connected to 21 22 23 26 and Q (output 50) is connected to 27 while Q (output 48) of the other flip-flop is connected eo 20. The direction of switching is controlled by presetting the J and K inputs of the flip-flops.

If K is held high and J low then after clocking Q goes to zero, and vise versa. Thus data can be presented to these inputs at any time between clocking pulses but switching occurs only when clocking or timing pulses are received.

The 500 Hz reference signal at input 29 in Figure 4 is connected via a resistor 56 and a capacitor 57 to a phase comparator input 58 of the integrated circuit phase-locked loop 7. The signal at the output 59 from the phase-locked loop 7 is multiplied to about & 8 MHz from which the four output frequencies 16000, 16001, 15950 and 15951 can be derived by division by a divide-by-500 circuit 60. Fine tuning of the phase-locked loop 7 is accomplished by means of a beehive trimmer 61. The gain of the loop 7 is reduced by a 560 ohm resistor 62 across the low pass filter terminals 63, 64 of the loop 7. The output 59 from the phase locked loop 7 is passed through a buffer monostable circuit 65 before connection to the programmable divider 15 and to the divide-by-500 circuit 60.

The programniable divider 15 comprises four binary synchronous counters 66 - 69 serially connected together. The output signal from the buffer monostabie 65 is connected to the clock input 70 of each of the counters 66 - 69 arranged such that counting by any one counter requires a simultaneous logical one ( 5v) on the counter enable ( (CE) ) input 71 and the counter input (CI) 720 The first count 66 has both inputs 71 and 72 connected to + 5V and the counts all the clock pulses For every 16vh clock pulse an output pulse is connected from the counter output (CO) 73 to the CE inputs 71 of the folliwing counters 67 - 69. The second counter 67 has + 5V connected to its CI input 72 and it therefore counts every 16 th clock pulse. The CI inputs 72 of the finel two counters 68 and 69 are respectively connected to the CO outputs 73 of the preceding counters Thus the counters 56 - 69 count clock pulses up to r16.

The binary number representing the instantaneous count is sampled by taking outputs 74 - 77 from the four stages of each counter and connecting them to respective first inputs of four two-input exclusive nor gates included on respective integrated circuits 78 - 81. The second inputs 82 - 85 of the exclusive nor gates on each integrated circuit 78 - 81 are connected to a logical one (+ 5v) or a logical zero (earth). The exclusive nor gates are open collector wired so that their outputs 86 - 89, which are all connected together, are low unless the counter output and the binary programming input represented on the inputs 82 - 85 are equal in which case a pulse at the common output 90 is applied via an inverter 91 to the resetting inputs of the counters 66 - 69 and they start to count again from zero. The pulse at the output 90 is also the 500 Hz signal required to complete the phase locked loop and it is connected via a second inverter 92 and a monostable 93 converting the signal to an equal mark space square wave, to the second input 94 to the phase comparator in the phase locked loop 7. The programming signals at the outputs 48 - 50 from the JK flip-flops 36 (Figure 3) are connected to the appropriate inputs 82 - 85 whereby the division ratio of the divider 15 can be selectively set at 16000, 16001, 15950 or 15951 depending upon whether the outputs 48 - 50 are high (+ 5V) or low (zero). The phase locked loop 7 then acts to produce an output signal at the output 59 which is 500 times the division ratio. The signal at the output 95 from the -thrce decade counters 96 - 98 which form the divide-by-500 circuit 60 is thus 16000, 160011 15950 or 15951 Hz coded according to the 50 band FSK input and the slow data input.

The signal at the output 95 is a square wave which is passed through a low pass active filter 99, producing a sine wave output signal , to an emitter follower buffer circuit 100 to provide the transmitter drive, The transmitter output may be taken as an unbalanced signal at output 101 or as a balanced signal at the outputs 102 and 103 from a Balum transformer 104.

A detailed receiver for decoding the 50 band FSK and slow data signals is shown in Figures 5, 6 and 7U The received radio frequency (r. f.) signal after being selectively attenuated is connected to the input 105 of an r.f. amplifier.

The attenuation level is selected so that the amplitude sensitive receiver is not over-driven, which could lead to spurious results from intermodulation products. The r.f. amplifier has an FET 106 input stage providing a high input Impendance. The output from the FET 106 is coriected via an as resistor amplifier 107 to the output 608 of the first stage of the r.f. amplifier.

The first stage has a voltage gain of over 200 with the circuit values chosen to optimise its operation in the VLF band. A band-pass filter 109, tun@@le for example over the range 14.5 kHz to 20 kHz may be connected via a @@@tch to the output 108 to improve the noise rejection of the receiver. The output 108, with or without band pass filtering, is connected to the inverting input 110 of an operational amplifier 111. A resistor 112 connecting the output from the amplifier 111 to the non-inverting input has an adjustable tap to which a - 12V supply voltage is connected to set the zero level of the amplifier. The output from the amplifier 111 is limited by connection to a first input 113 of a comparator 114 with the second input 115 being connected to a potentiometer 116 for setting the comparator threshold. The output 117 from the comparator 114 carries a square wave signal when driven by the amplifier 111.

The amplified and limited received r.f. signal is compared in a coherent system with the output of a local oscillator cf the same fundamental frequency1 16 kHz, as the transmitter. Figure 6 shows a frequency synthesiser for producing the local 16 kHz standard frequency derived from a 1 MHz scurce.

A 1 MHz signal from a frequency-reference source available on submarines is connected to the input 118. The input signal is buffered by a Schmitt trigger 119 and then divided by 1000 by three decade counters 120 - 122 to produce a 1 kHz signal, The 1 iSHz signal is connected to the reference input 123 to the phase comparator of a phase locked loop integrated circuit 124. keen the circuit 124 is locked the internal voltage controlled oscillator operates at 32 kHz. The output 125 from the phase locked loop is divided by two to give the required 16 kHz reference signal at an output 126 of a binary divider circuit 127 and then divided by sixteen to give a 1 kHz signal at an output 128 for connection to the second phase comparator input 129 of the phase locked loop 124.

The r.f. signal input 117 and the 16 kFz reference signal input 126 are mixed in the phase comparator section of a phase locked loop 130 shown in Figure 7.

The output 131 from the phase locked loop 130 is a varying mark-space ratio square wave. This output signal is then integrated to produce a resulting signal which is proportional to the phase of the received signal. Three outputs 132 - 134 are derived from the phase locked loop 130. The first output 132 gives the 1 boundslow data signal. The output 131 is connected to an active low pass (LP) filter 135 designed to pass only the 1 Hz slow data signal.

The output from the LP filter 135 is connected to the 1 Hz output 132 via a voltage follower buffer circuit 136. The phase locked loop output 131 is also connected to the second output 133 which gives the 50 band FSK signal after being low pass fitered at about 100 Hz by ab active LP filter 137 and buffered by the voltage-follower circuit 138. The third output 134 is a test facility which is unfiltered and is connected to the output 137 from the phase locked loop 130 via a voltage-follower circuit 139. A further test terminal 140 is connected to the buffered output 125 from the 16 kHz frequency synthesiser.

The present invention thus rrovides a complementary second channel to a conventional 50 baud FSK communications system. The second channel carrying slow data traffic greatly extends the range of the communications system.

Since the timing signals for multiplexing the two channels and the transmission frequencies are all derived from a single basic transmission reference frequency, the stability of the system is then dependent on the reference frequency stability. Although the invention has been described in relation to a slow data channel which results from applying a 1 Hz frequency modulation simultaneously to both tones of the existing FSK channel, it will be apparent to those skilled in the art that the principles of the invention explained above can be put into effect in alternative emoodiments.

For example, the add'tion of a second slow data rate channel at say 7 Hz to a conventional 75 bits per sec telegraph circuit (and similarly for 110 bits per sec or highe4ratcs) would provide a contSauous order wire facility or other service not related to t'ne traffic being carried on the primary data channel.

The second channel can adopt phase modulation in place of frequency modulation. The two FSK tones may be phase shifted forwards 3600 during transmission of a slow data mark, and then phase shifted backwards 3600 at the next mark. This system would not affect the total number of cycles transmitted during an extended period.

Claims

Claims 1. A digital communications transmitter comprising means to encode a first communications signal, means to transmit the encoded signal at a first data rate using two discrete frequency transmissions, means to encode a second signal for transmission at a second slower data rate such that the ratio of the two rates is an integer, and means to combine the two encoded signals with phase coherence whereby at least one of the two discrete frequency transmissions of the first communications signal is modulated by the second signal.
2. A digital communications transmitter as claimed in claim 1 wherein the second signal modulateS both of the two discrete frequency transmissions.
3. A digital communications transmitter as claimed in claim 1 or 2 wherein the second signal frequency modulates the encoded first signal.
4. A digital communications transmitter as claimed in claim 3 wherein the first signal is frequency shift keyed with one of the discrete frequencies representing a mark and the other discrete frequency representing a Space in the encoded first signal, and the second signal is a modulation of the first encoded signal such that a mark is represented by an equal change in frequency of the two discrete frequencies.
5. A digital communications transmitter as claimed in any one preceding claim wherein a single reference frequency source is used to generate the frequencies for transmission of the two communications signals and to generate switching signals to ensure the phase coherence of the modulation.
6. A digital communications transmitter as claimed in claim 5 wherein the reference frequency source is used to drive two bi-stable circuits at the respective rates of data transmission of the first and second communications signals, the outputs fron the two bi-stable circuits being used to produce the s X:itching signals.
7. A digital communications transmitter as claimed in claim 5 or 6 wherein' the first and second communications signals use discrete frequency transmissions, the discrete frequencies being produced by connecting the output from the reference frequency source via a phase-locked loop including a programmable divider which is selectably controlled to produce the appropriate output discrete frequency.
8. A digital communications receiver for receiving communications signals as transmitted by a transmitter as claimed in any one preceding claim comprising circuit means to detect the first and second communications signals, means to generate an electrical output signal at one of the two discrete frequencies of the first communications signal, a comparator means to compare the detected signals with the generated signal and to produce a difference output signal, and a filter means to separate the first and second signals from the difference output signal.
9. A digital communications receiver as claimed in claim 8 wherein the detector means includes an r.f. amplifier having a band-pass filter to improve the sensitivity.
10. A digital communications receiver as claimed in claim 9 wherein the r.f. amplifier includes a limiter to reduce the amplitude sensitivity of the receiver.
11. A digital communications receiver as claimed in any one of claims 8 to 10 wherein the comparator means is a phase comparator.
12. A digital communications transmitter substantially as described and claimed with respect to Figures 1, 3 and 4 of the accompanying Drawings.
13. A digital communications receiver substantially as described with respect to Figures 2, and 5 - 7 of the accompanying Drawings.

13. A digital communications receiver substantially as described and claimed with respect to Figures 2, and 5 - 7 of the accompanying Drawings.

Amendments to the claims have been filed as follows Claims 1. A digital communications transmitter comprising means to encode a first communications signal, means to transmit the encoded signal at a first data rate using two discrete frequency transmissions, means to encode a second communications signal for transmission at a second slower data rate such that the ratio of the two rates is an integer, and means to combine the two encoded signals with phase coherence whereby at least one of the two discrete frequency transmissions of the first communications signal is modulated by the second signal.

2. A digital communications transmitter as claimed in claim 1 wherein the second signal modulateS both of the two discrete frequency transmissions.

5. A digital communications transmitter as claimed in claim 1 or 2 wherein the second signal frequency modulates the encoded first signal.

4. A digital communications transmitter as claimed in claim 3 wherein the first signal is frequency shift keyed with one of the discrete frequencies representing a mark and the other discrete frequency representing a Space in the encoded first signal, and the second signal is a modulation of the first encoded signal such that a mark is represented by an equal change in frequency of the two discrete frequencies.

5. A digital communications transmitter as claimed in any one preceding claim wherein a single reference frequency source is used to generate the frequencies for transmission of the two communications signals and to generate switching signals to ensure the phase coherence of the modulation.

6. A digital communications transmitter as claimed in claim 5 wherein the reference frequency source is used to drive two bi-stable circuits at the respective rates of data transmission of the first and second communications signals, the outputs from the two bi-stable circuits being used to produce the switching signals.

7. A digital communications transmitter as claimed in claim 5 or 6 wherein the first and second communications signals use discrete frequency transmissions, the discrete frequencies being produced by connecting the output from the reference frequency source via a phase-locked loop including a programmable divider which is selectably controlled to produce the appropriate output discrete frequency.

8. A digital communications receiver for receiving communications signals as transmitted by a transmitter as claimed in any one preceding claim comprising circuit means to receive the first and second communications signals, means to generate an electrical output signal at one of the two discrete frequencies of the first communications signal, a comparator means to compare the detected signals with the generated signal and to produce a difference output signal, and a filter means to separate out the first and second signals from the difference output signal.

9. A digital communications receiver as claimed in claim 8 wherein the detector means includes an r.f. amplifier having a band-pass filter to improve the sensitivity.

10. A digital communications receiver as claimed in claim 9 wherein the r.f. amplifier includes a limiter to reduce the amplitude sensitivity of the receiver.

11. A digital communications receiver as claimed in any one of claims 8 to 10 wherein the comparator means is a phase comparator.

12. A digital communications transmitter substantially as described with respect to Figures 1, 3 and 4 of the accompanying Drawings.