GB2308516A - Microprocessor interface circuit and system - Google Patents

Abstract

A microprocessor interface circuit 100 includes an input/output port 101 for connection to a microprocessor input/output port 11, logic means 105, 106, 107, 108, 109 coupled to the interface I/O port, and positive and ground reference potentials coupled to the interface I/O port, wherein the logic means can detect either a positive, ground or intermediate potential on the interface I/O port 101. Manchester-coded signals may be output (figure 2). The intermediate potential is provided by resistors 115, 125 when the microprocessor output 11 is high-impedance.

Description

MICROPROCESSOR INTERFACE CECUll AND SYSTEM Field Of The Invention This invention relates to microprocessor interface circuits, and particularly but not exclusively to microprocessor interface circuits for interfacing between a microprocessor and a device, such as an actuator or sensor.

Background Of The Invention As is known, a typical input/output (I/O) port of a microprocessor such as a micro controller unit (MCU) has input and output modes. When in the output mode, the port is driven by an output driver which can be coupled to either a positive or a ground reference potential so as to assert either a logical 1 state or a logical 0 state respectively. The interface circuit, connected to the I/O port of the MCU is provided with a detector to detect which state has been asserted on the port.

In general, when an MCU is transmitting information via an I/O port in the output mode, there are two possible states 1 and 0 for the information, corresponding to logical 1 and logical 0. Thus, for example, if three pins are used, 8 variables can be transmitted, (23=8). For many applications, it is essential that the pin count for both the MCU and the interface circuit be kept to a minimum for reasons of cost and size.

The interface circuit coupled to the MCU must either include some circuitry for generating a clock signal, such as a phase locked loop or oscillator, or a pin must be dedicated to receiving a clock signal from the MCU. Both of these methods further increase the cost and size of the interface circuit.

Aepordingly, this invention seeks to provide a microprocessor interface circuit in which the above mentioned disadvantages are mitigated.

Brief Summarv Of The Invention According to a first aspect of the invention, there is provided a microprocessor interface circuit comprising an input/output port for connection to a microprocessor input/output port, logic means coupled to the interface I/O port, and positive and ground reference potentials coupled to the interface I/O port, wherein the logic means can detect either a positive, ground or intermediate potential on the interface I/O port.

According to a second aspect of the invention, there is provided a system comprising a microprocessor having an input/output port coupled, in an output state, to an output driver which is selectively coupled to either a positive or ground reference potential so as to assert the reference potential on the microprocessor input/output port as either the 1 or 0 states, and, in the input state, to an input driver which provides a high impedance on the microprocessor input/output port, the system further comprising a microprocessor interface circuit comprising an input/output port for connection to the microprocessor input/output port, logic means coupled to the interface I/O port, and positive and ground reference potentials coupled to the interface I/O port, wherein the logic means can detect either the 1 or 0 states when the microprocessor is in its output state, or an intermediate state when the microprocessor is coupled in its input state.

In a preferred embodiment, the logic means comprises a resistor network defining voltage thresholds, a comparator circuit for comparing the voltage on the interface I/O port with the voltage thresholds, and a logic circuit coupled to the comparator circuit to detennine which one of the 1, 0 or intermediate states is detected. Preferably, the logic means includes 1, 0 and intermediate state output lines for indicating which of the three states is detected.

In one embodiment, the system further includes a sampling circuit having a clock input coupled to the intermediate state output line and a data input coupled to either the 1 or 0 state output line of the logic means, the sampling circuit including a delay in the data input so that the data on the data input can be sampled when the sampling circuit is clocked from the clock input, thus providing asynchronous communication between the microprocessor and the interface circuit.

In a further preferred embodiment of the invention, the system further comprises a data register receiving the data sampled by the sampling circuit and a latch for receiving the data from the data register after a predetermined number of clock cycles.

Brief Descriotion of the Drawings A preferred embodiment of the present invention will now be more fully described, by way of example, with reference to the drawings, in which: FIG. 1 shows a schematic diagram of an MCU and an interface circuit according to a preferred embodiment of the present invention; FIG. 2 shows a timing diagram for data transferred between the MCU and the interface circuit of FIG. 1.

FIG.3 shows a bi-phase code according to one embodiment of the invention.

FIG.4 shows a timing diagram for data transferred according to the biphase code of FIG.3.

Detailed Description of a Preferred Embodiment Referring to FIG.1 there is shown a microprocessor system 5, comprising a micro controller unit (MCU) 10 and an interface circuit 100. The MCU 10 includes an I/O port 11 controlled by a data direction register (DDR) 20.

The interface circuit 100 includes a node 102 which is coupled to the I/O port 11 of the MCU 10. The node 102 is coupled via a first resistor 115 to a 5V supply voltage terminal 120, and via a second resistor 125 to a ground terminal 130. The first and second resistors 115 and 125 have a value of substantially 20is2. In this way, the node 102, in the absence of any signal applied by the I/O port 11, has a voltage of 2.5V The 5V supply voltage terminal 120 is also coupled to the ground terminal 130 via a potential divider arrangement of third, fourth and fifth resistors 135, 145 and 155 respectively. These resistors also have a value of substantially 20 kQ.

A first point of divided potential 103, between the third resistor 135 and the fourth resistor 145 has an associated voltage of approximately 3.33V. A second point of divided potential 104, between the fourth resistor 145 and the fifth resistor 155 has an associated voltage of approximately 1.67V. A first comparator 105 has a non-inverting input coupled to the first point of divided potential 103, an inverting input coupled to the node 102, and an output. A second comparator 106 has a non-inverting input coupled to the node 102, an inverting input coupled to the second point of divided potential 104, and an output.

A first inverter 107 is coupled to receive the output from the first comparator 105, for providing a first logic output 112. A second inverter 109 is coupled to receive the output from the second comparator 106, for providing a second logic output 110. An AND gate 108 is coupled to receive the outputs from the first and second comparators 105 and 106 respectively, for providing a third logic output 111.

The first logic output 112 is coupled to a delay circuit 113, which provides a delayed value of the first logic output 112. A D-type flip-flop 114 has a data input coupled to receive the delayed value of the first logic output from the delay circuit 113, a clock input coupled to the third logic output 111, and an output.

In operation, data to be communicated from the MCU 10 to the interface circuit 20 is arranged to be transferred serially using the I/O port 11. The DDR 20 can be set with a high or low logic state. With logic state high set, the I/O port 11 is set to send data from within the MCU 10 to the interface circuit 100. With logic state low set, the I/O port 11 is configured with a high impedance, normally arranged for receiving data from the interface circuit 100.

When the I/O port 11 is configured for output with the DDR 20 set to logical high, the low output impedance of the I/O port 11 causes the node 102 to have a voltage substantially equal to the logical level asserted by the I/O port 11.

If the I/O port is set to state one, the voltage at node 102 is very close to 5V.

The comparator 105 has a higher inverting input voltage (-5V) than the non-inverting input (-3.33V) and therefore has a zero output. The inverter 107 causes the first logic output 112 to be high. The comparator 106 has a higher non-inverting input voltage (-5V) than the inverting input (-1.67V) and therefore has a high output. The inverter 109 causes the second logic output 110 to be zero. Since one of the inputs to the AND gate 108 is zero, the third logic output 111 is also zero.

If the I/O port is set to state zero, the voltage at node 102 is very close to 0V.

The comparator 105 has a higher non-inverting input voltage (-3.33V) than the inverting input (-0V) and therefore has a high output. The inverter 107 causes the first logic output 112 to be zero. The comparator 106 has a higher inverting input voltage (-1.67V) than the non-inverting input (-0V) and therefore has a zero output. The inverter 109 causes the second logic output 110 to be high. Since one of the inputs to the AND gate 108 is zero, the third logic output 111 is again zero. In this way, when the logical high state or logical zero state is asserted at the I/O port 11, the first and the second logic outputs 112 and 110 respectively have logic high states.

If the I/O port 11 is configured for input with the DDR 20 set to logical zero, the high impedance of the I/O port 11 causes the node 102 to have a voltage substantially equal 2.5V.

In this case, the comparator 105 has a higher non-inverting input voltage (-3.33V) than the inverting input (-2.5V) and therefore has a high output.

The inverter 107 causes the first logic output 112 to be zero. The coIpparator 106 has a higher non-inverting input voltage (-2.5V) than the inverting input (-1.67V) and therefore has a high output. The inverter 109 causes the second logic output 110 to be zero. This time however both inputs to the AND gate 108 are high, causing the third logic output 111 to be high. Thus the third logic output 111 represents a third logic state. In this way the embodiment produces three variable states from one physical wire connection (the I/O port 11).

Referring now also to FIG.2, using appropriate bit encoding it is possible to use transitions from the high or low states to the third intermediate state as a clock output, for providing a clock to the interface circuit 100. Each alternate data bit 200, 201, 202 is set as a third state bit. Each remaining data bit 301, 302, 303 is used as a data transfer bit, to send meaningful data from the MCU 10 to the interface circuit 100. The D-type flip flop 114 is clocked using the low to high transition of the third logic output 111. The delay circuit 113 introduces a delay in the first logic output 112, such that a high data value (for example 300) is still present at the input to the flip flop 114, when the low to high transition on the third output (for example 201) occurs.

In this way asynchronous communication is provided between the MCU 10 and the interface circuit 100. At each occurrence of the third logic state 200, 201, 202, a clock signal 310 is generated therefrom. Therefore the need for a local oscillator and synchronisation circuit in the interface circuit 100, in order to generate a clock, is avoided.

Referring now also to FIG.3, a further application of the third state logic uses Manchester code or bi-phase code. The bi-phase code requires two time slots to specify data bit information. The bi-phase property requires that the two logical states set in the two time slots must have complementary logical state values. For instance when the logical state high is set in the first time slot and the logical state low is set in the second time slot a zero data bit 400 is defined. When the logical state low is set in the first time slot and the logical state high is set in the second time slot a 1 data bit 410 is defined. Every time the rules described above are not respected, the interface 100 may interpret this as a violation of the bi-phase coding and take appropriate actions. For instance these actions could be a sychronisation procedure, start of sequence for serial communication or set, reset, pre-set, store value, disable output, mode selection etc.

Referring now also to FIG.4, the bi-phase code is used to communicate between the MCU 10 and the interface circuit 100 when an open multiplexed bus network is used. In this case the MCU 10 always initiates a data transmission to the interface circuit 100 by sending three or four contiguous High to Intermediate state transitions 500 that violate the law of the bi-phase code. The violation alerts the interface circuit 100 that a message will be sent by the MCU 10. Data bits are then sent from the MCU 10 to the interface circuit 100 according to the bi-phase code. When completed, successive low to intermediate transitions are sent from the MCU 10, indicating that data transfer is complete, and that data transfer from the interface circuit 100 to the MCU 10 is enabled (via a secondary I/O port, not shown), whilst the clock signals continue to be derived from the low to intermediate transitions sent from the MCU 10 via the I/O port 11.

It will be appreciated that although only one particular embodiment of the invention has been described in detail, various modifications and improvements can be made by a person skilled in the art without departing from the scope of the present invention. For example, using two I/O ports and two interface circuits as described above, it is possible to produce an interface arrangement having a 9 state output (32). Further ports and interfaces could be used in a similar way, over an open multiplexed bus network.

The number of bits sent by the MCU 10 to the interface circuit 100 may vary and is determined by the need of the interface circuit 100 specified for one application. The length of the message is determined by the number of address-bits necessary to communicate- with all interfaces connected on the open multiplex bus network and by the number of data bits required in each interface.

Furthermore, the precise coding of the bi-phase code need not be as described above. The third logic output 111 could be used for purposes other than as a clock signal.

Claims (8)

Claims

1. A microprocessor interface circuit comprising: an input/output port for connection to a microprocessor input/output port; logic means coupled to the interface VO port, and; positive and ground reference potentials coupled to the interface I/O port, wherein the logic means can detect either a positive, ground or intermediate potential on the interface I/O port.

2. A system comprising a microprocessor having an input/output port coupled, in an output state, to an output driver which is selectively coupled to either a positive or ground reference potential so as to assert the reference potential on the microprocessor input/output port as either the 1 or 0 states, and, in the input state, to an input driver which provides a high impedance on the microprocessor input/output port, the system further comprising a microprocessor interface circuit comprising: an input/output port for connection to the microprocessor input/output port; logic means coupled to the interface I/O port, and; positive and ground reference potentials coupled to the interface I/O port, wherein the logic means can detect either the 1 or 0 states when the microprocessor is in its output state, or an intermediate state when the microprocessor is coupled in its input state.

3. The circuit or system of claim 1 or claim 2 respectively wherein the logic means comprises a resistor network defining voltage thresholds, a comparator circuit for comparing the voltage on the interface I/O port with the voltage thresholds, and a logic circuit coupled to the comparator circuit to determine which one of the 1, 0 or intermediate states is detected.

4. The circuit or system of any preceding claim wherein the logic means includes 1, 0 and intermediate state output lines for indicating which of the three states is detected.

5. The system of any of the above claims when dependent on claim 2 further including a sampling circuit having a clock input coupled to the intermediate state output line and a data input coupled to either the 1 or 0 state output line of the logic means, the sampling circuit including a delay in the data input so that the data on the data input can be sampled when the sampling circuit is clocked from the clock input, thus providing asynchronous communication between the microprocessor and the interface circuit.

6. The system of any one of claims 3 to 5 when dependent on claim 2 further comprising a data register receiving the data sampled by the sampling circuit and a latch for receiving the data from the data register after a predetermined number of clock cycles.

7. An interface circuit substantially as hereinbefore described and with reference to the drawings.

8. A system substantially as hereinbefore described and with reference to the drawings.