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GB2300970A - Method for fabricating a diffusion barrier metal layer - Google Patents

Method for fabricating a diffusion barrier metal layer Download PDF

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Publication number
GB2300970A
GB2300970A GB9610393A GB9610393A GB2300970A GB 2300970 A GB2300970 A GB 2300970A GB 9610393 A GB9610393 A GB 9610393A GB 9610393 A GB9610393 A GB 9610393A GB 2300970 A GB2300970 A GB 2300970A
Authority
GB
United Kingdom
Prior art keywords
barrier metal
diffusion barrier
layer
metal layer
oxygen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9610393A
Other versions
GB2300970B (en
GB9610393D0 (en
Inventor
Kyeong Keun Choi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of GB9610393D0 publication Critical patent/GB9610393D0/en
Publication of GB2300970A publication Critical patent/GB2300970A/en
Application granted granted Critical
Publication of GB2300970B publication Critical patent/GB2300970B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A method for fabricating a diffusion barrier metal layer (7) of a semiconductor device for preventing a material of a metal wiring of the semiconductor device from being diffused into a silicon layer under the metal wiring is disclosed including the steps of: exposing the surface of the silicon layer (1) to oxygen plasma, to prevent a silicide from being formed at the interface between the silicon layer and diffusion barrier metal layer; forming a first diffusion barrier metal layer (7) on the silicon layer; implanting oxygen ions into the first diffusion barrier metal layer; and forming a second diffusion barrier metal layer (9) on the first diffusion barrier metal layer. The metal layer may comprise RUTHENIUM OXIDE which may also be used as an adhesion layer between an electrode and the silicon surface.

Description

1 SEMICONDUCTOR DEVICE AND METHOD FOR rABRICATING A DIFFUSION BAMIER METAL
LAYER THEREIN The present invention relates to a semiconductor device and to a method for fabricating a diffusion barrier metal layer in a semiconductor device. The method Is particularly, through not exclusively, suitable for fabricating a diffusion barrier metal 'layer which can be used in a deep and narrow contact, and it minimises the likelihood of the substance of metal wiring from. being diffused into Its underlayer during the formation of the metal wiring of the semiconductor device.
Generally, a ruthenium oxide layer (Ru02) is used as a diffusion barrier metal layer In highly Integrated semiconductor devices above 256M DRAM, and as a glue layer for a metal wiring formed of aluminum, tungsten or copper. in previous proposals, the ruthenium oxide layer Is formed by the physical vapor deposition (PVD). or the chemical vapor deposition (CVD) method. In the case of the PVD methodr ruthenium and oxygen are compounded to form the ruthenium oxide layer. In the case of the WD method, ruthenium source gas and oxygen are compounded to form the ruthenium oxide layer using the metal organic chemical vapor deposition (MOCVD) method.
llowevert In cases in which theruthenium oxide layer Is formed by the CVD, method, Impurities are Introduced Into the ruthenium oxide layer. This Increases the resistance value of the layer. In cases In which the PVD method Is used, the step coverage of the ruthenium oxide layer Is poor, and a silicide layer may be formed by the reaction of the ruthenium oxide layer and silicon. Furthermore, during the deposition of the rutheniumoxide layer, the oxidation rate is too low to form a stable ruthenium oxide layer.
4.
:1 - 2 Features of arrangements to be described below, as examples, are the provision of a method for fabricating a diffusion barrier metal layer In a semiconductor device, which is capable of minimising the likelihood of the formation of a silicide layer at the interface between a ruthenium and a silicon layer, and the formation of a stable ruthenium oxide layer at a high temperature.
In a particular arrangement to be described below, as an exampler there is provided a method for fabricating a diffusion barrier metal layer In a semiconductor device for preventing a material of a metal wiring in said semiconductor device from being diffused into a silicon layer under said metal wiring, the method including the steps of: exposing the surface of said silicon layer to oxygen plasma, to prevent a silicide from being formed at the Interface between said silicon layer and diffusion barrier metal layer; forming a first diffusion barrier metal layer on said silicon layer; implanting oxygen ions Into said first diffusion barrier metal layer; and forming a second diffusion barrier metal layer on said first diffusion barrier metal layer.
An arrangement illustrative of the invention, will now be described, by way of example, with reference to the accompanying drawings, In which:
Figs. 1A to 1F are cross-sectional views showing processes L for forming a diffusion barrier metal layer.
0 A preferred embodiment of the prevent Invention will be described below referring to the accompanying drawings. Figs. 1A to 1F are crosssectional views showing processes for forming a rutheniumoxide layer as a diffusion barrier metal layer.
An shown lit Fig. 1A, art Insulating layer 3 is formed on a silicon substrate 1 avid a field oxide layer 2, and a conducting layer 4 in formed on the field oxide layer 2. Then, an Insulating layer 5 In formed on the overall surface of substrate 1, and the Insulating layers 3 and 5 are selectively removed to form a contact hole, thereby exposivig a predetermined portion of the silicon substrate 1 arid the conducting layer 4.
An shown In Fig. ID, the overall surface of the substrate 1 In exposed to 02 plasma 6. llere, the 02 plasma 6 adheres to the overall surface of tile substrate 1 oil which the conducting layer 4 and the Insulating layer 5 ere formed. Tire 02 plasma is formed at a low power of below Sow, arid at a gas flow of Ssccm to Soaccm In plasma enhanced chemical vapor deposition (PECVD) chamber. An described above, by carrying out lite 02 plasma treatment, It In possible to prevent a allicide from being formed at the interface of ruthenium arid silicon during the following heat treatment, and form a stable ruthenium oxide layer at a high temperature.
AS shown In Fig. 1C, a f Irst ruthenium layer 7 In formed to a thickness of 1001% to 500A lit PV0 sputter camber an the overall surface of the substrate 1 art which the conducting layer 4 and - 0 the insulating layer 5 are formed. Then, 02 In implanted Into the overall surface of the first ruthenium layer 7. Ifere, 0. implantation In carried out, considering the projection range Rp according to the thicktiess of the first ruthenium layer 7. For example, If the thickitesq of the first ruthenium layer in 2OoA, 02 In impla.vited at a dose of 1015 - 10191ons/C1n2 and at an energy level of SukeV.
An shown Irl Fig. 10, a secotid ruthenium layer 9 in formed under the same corlditicii as tlint for the first ruthenium layer 7. Then, the substrate 1, on which the first and second ruthenium layers 7 and 9 are formed, in heat-treated In a tube In which argon and oxygen, 'or nitrogen avid oxygen are mixed for one to five #tours. By doing so, as shown In Fig. 1E, an ultimate rutheniumoxide layer 10 Is formed. flere, the flow of argon/oxygen or nitrogen/oxygeri Introduced into the tube In approximately looncem/loncem to 20009ccm/3009ccm, avid the temperature in the tube in approximately 400e to 700C. As described above, 02 Is Implanted Into between the first avid second ruthenium layers avid a beet treatment in carried out lit the tube. so that the stable ruthenium oxide layer cart be formed. Fig. 1P In a cross-sectional view showing a device lit which a metal wiring 11 Is formed using rutheniumoxide layer 10 as a diffusion barrier. The metal wiring 11 Is formed of clumitium, tungsten or copper.
In the Illustrative arrangement described above, It is possible to prevent the silicide from being formed at the Interface between the ruthenium layer avid silicon layer. Thus, the stable ruthenium oxide layer cart be obtained. By using the stable ruthenium oxide layer as a diffusion barrier, It Is able to 41 - 5 prevent the substance of the metal wiring from being diffused, and form a metal plug having low resistance.
Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, within the scope of the protection sought by the accompanying claims.
L :1 9 00

Claims (11)

1 A method for fabricating a diffusion barrier metal layer In a semiconductor device, for minimising the likelihood of a material of a metal wiring in said semiconductor device from being diffused into a silicon layer under said metal wiring, said method including the steps of:
exposing the surface of raid silicon layer to oxygen plasma, to prevent a ellicide from beivig formed at the Interface between said silicon layer avid diffusion barrier metal layer; forming a first diffusion barrier metal layer on said silicon layers implanting oxygeti lons itito said first diffusion barrier metal layers and forming a second diffuslort barrier metal layer on said first: diffusion barrier metal layer.
2. The method In accordance with claim 1, wherein said first and necovid diffuslati barrier metal layers are ruthenium layer.
3. The method In accordance with claim 1, wherein said 02 plasma in formed at a low power of below SOW and a gas flow of Succm to SOncem In PECV0 chamber.
4. The method In accordavice with claim 2, wherein the density of said oxygen lovis Is a does of 1015 - 10191ang/CM2.
5. The method In accordavice with claim 2, wherein said first diffusion barrier metal layer Is formed at a thickness of 100A to 500A.
6. The method in accordance with claim 1, the step of forming said second diffusion barrier metal layer further comprises the step of oxidizing said first and second diffusion barrier metal layers.
7. The method In accordance with claim 6, wherein said oxidizing step Is heat treatment carried out In a tube, In which argon and oxygen, or nitrogen and oxygen are mixed, for one to five hours.
8. The method in accordance with claim 7, wherein the flow of said argon/oxygen or nitrogen/oxygen in said tube Is approximately 100sccm/10sccm to 2000sccm/300sccm.
9. The method in accordance with claim 8, wherein the temperature In said tube Is approximately 400C to 700C.
10. A method as claimed in claim 1, substantially as described herein with reference to the accompanying drawings.
11. A semiconductor device made by a method a one of the preceding claims.
s claimed in any
GB9610393A 1995-05-17 1996-05-17 Semiconductor device and method for fabricating a diffusion barrier metal layertherein Expired - Fee Related GB2300970B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950012306A KR0172772B1 (en) 1995-05-17 1995-05-17 Method of forming ruthenium oxide film for diffusion barrier of semiconductor device

Publications (3)

Publication Number Publication Date
GB9610393D0 GB9610393D0 (en) 1996-07-24
GB2300970A true GB2300970A (en) 1996-11-20
GB2300970B GB2300970B (en) 1999-10-13

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Family Applications (1)

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GB9610393A Expired - Fee Related GB2300970B (en) 1995-05-17 1996-05-17 Semiconductor device and method for fabricating a diffusion barrier metal layertherein

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US (1) US5637533A (en)
JP (1) JPH08316321A (en)
KR (1) KR0172772B1 (en)
CN (1) CN1048819C (en)
DE (1) DE19620022C2 (en)
GB (1) GB2300970B (en)
TW (1) TW301020B (en)

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3201061B2 (en) * 1993-03-05 2001-08-20 ソニー株式会社 Manufacturing method of wiring structure
US6080645A (en) 1996-10-29 2000-06-27 Micron Technology, Inc. Method of making a doped silicon diffusion barrier region
US5739064A (en) * 1996-11-27 1998-04-14 Micron Technology, Inc. Second implanted matrix for agglomeration control and thermal stability
KR100430683B1 (en) * 1996-12-31 2004-07-05 주식회사 하이닉스반도체 Metal wiring formation method of semiconductor device
US5926730A (en) * 1997-02-19 1999-07-20 Micron Technology, Inc. Conductor layer nitridation
US5940726A (en) * 1997-11-06 1999-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming an electrical contact for embedded memory
US6482734B1 (en) 1998-01-20 2002-11-19 Lg Semicon Co., Ltd. Diffusion barrier layer for semiconductor device and fabrication method thereof
KR100404649B1 (en) * 1998-02-23 2003-11-10 가부시끼가이샤 히다치 세이사꾸쇼 Semiconductor device and fabrication method thereof
US6846739B1 (en) * 1998-02-27 2005-01-25 Micron Technology, Inc. MOCVD process using ozone as a reactant to deposit a metal oxide barrier layer
US6077775A (en) * 1998-08-20 2000-06-20 The United States Of America As Represented By The Secretary Of The Navy Process for making a semiconductor device with barrier film formation using a metal halide and products thereof
WO2000011721A1 (en) * 1998-08-20 2000-03-02 The Government Of The United States Of America, Represented By The Secretary Of The Navy Electronic devices with barrier film and process for making same
US6144050A (en) * 1998-08-20 2000-11-07 The United States Of America As Represented By The Secretary Of The Navy Electronic devices with strontium barrier film and process for making same
US6188134B1 (en) 1998-08-20 2001-02-13 The United States Of America As Represented By The Secretary Of The Navy Electronic devices with rubidium barrier film and process for making same
US6720654B2 (en) 1998-08-20 2004-04-13 The United States Of America As Represented By The Secretary Of The Navy Electronic devices with cesium barrier film and process for making same
US6734558B2 (en) 1998-08-20 2004-05-11 The United States Of America As Represented By The Secretary Of The Navy Electronic devices with barium barrier film and process for making same
US6351036B1 (en) 1998-08-20 2002-02-26 The United States Of America As Represented By The Secretary Of The Navy Electronic devices with a barrier film and process for making same
US6291876B1 (en) 1998-08-20 2001-09-18 The United States Of America As Represented By The Secretary Of The Navy Electronic devices with composite atomic barrier film and process for making same
US6517616B2 (en) 1998-08-27 2003-02-11 Micron Technology, Inc. Solvated ruthenium precursors for direct liquid injection of ruthenium and ruthenium oxide
US6541067B1 (en) 1998-08-27 2003-04-01 Micron Technology, Inc. Solvated ruthenium precursors for direct liquid injection of ruthenium and ruthenium oxide and method of using same
US6063705A (en) * 1998-08-27 2000-05-16 Micron Technology, Inc. Precursor chemistries for chemical vapor deposition of ruthenium and ruthenium oxide
US6599829B2 (en) * 1998-11-25 2003-07-29 Texas Instruments Incorporated Method for photoresist strip, sidewall polymer removal and passivation for aluminum metallization
KR100389913B1 (en) * 1999-12-23 2003-07-04 삼성전자주식회사 Forming method of Ru film using chemical vapor deposition with changing process conditions and Ru film formed thereby
JP4034518B2 (en) * 2000-03-31 2008-01-16 株式会社日立国際電気 Manufacturing method of semiconductor device
US6465887B1 (en) 2000-05-03 2002-10-15 The United States Of America As Represented By The Secretary Of The Navy Electronic devices with diffusion barrier and process for making same
US7494927B2 (en) * 2000-05-15 2009-02-24 Asm International N.V. Method of growing electrical conductors
KR100414948B1 (en) * 2000-06-30 2004-01-14 주식회사 하이닉스반도체 Method of forming a capacitor in a semiconductor device
US6903005B1 (en) 2000-08-30 2005-06-07 Micron Technology, Inc. Method for the formation of RuSixOy-containing barrier layers for high-k dielectrics
US6461909B1 (en) 2000-08-30 2002-10-08 Micron Technology, Inc. Process for fabricating RuSixOy-containing adhesion layers
KR100434489B1 (en) 2001-03-22 2004-06-05 삼성전자주식회사 Method for depositing ruthenium layer having Ru02 seeding layer
KR100805843B1 (en) * 2001-12-28 2008-02-21 에이에스엠지니텍코리아 주식회사 Copper wiring forming method, semiconductor device and copper wiring forming system manufactured accordingly
US20030211711A1 (en) * 2002-03-28 2003-11-13 Hirofumi Seki Wafer processing method and ion implantation apparatus
KR100446300B1 (en) * 2002-05-30 2004-08-30 삼성전자주식회사 Method for forming metal interconnections of semiconductor device
US20080070405A1 (en) * 2002-05-30 2008-03-20 Park Jae-Hwa Methods of forming metal wiring layers for semiconductor devices
US7247554B2 (en) * 2002-07-02 2007-07-24 University Of North Texas Method of making integrated circuits using ruthenium and its oxides as a Cu diffusion barrier
US20050110142A1 (en) * 2003-11-26 2005-05-26 Lane Michael W. Diffusion barriers formed by low temperature deposition
US7892406B2 (en) * 2005-03-28 2011-02-22 Tokyo Electron Limited Ionized physical vapor deposition (iPVD) process
US20090321247A1 (en) * 2004-03-05 2009-12-31 Tokyo Electron Limited IONIZED PHYSICAL VAPOR DEPOSITION (iPVD) PROCESS
US8025922B2 (en) 2005-03-15 2011-09-27 Asm International N.V. Enhanced deposition of noble metals
US7666773B2 (en) 2005-03-15 2010-02-23 Asm International N.V. Selective deposition of noble metal thin films
US7713876B2 (en) * 2005-09-28 2010-05-11 Tokyo Electron Limited Method for integrating a ruthenium layer with bulk copper in copper metallization
US20070069383A1 (en) * 2005-09-28 2007-03-29 Tokyo Electron Limited Semiconductor device containing a ruthenium diffusion barrier and method of forming
KR101379015B1 (en) 2006-02-15 2014-03-28 한국에이에스엠지니텍 주식회사 METHOD OF DEPOSITING Ru FILM USING PEALD AND DENSE Ru FILM
US7588667B2 (en) * 2006-04-07 2009-09-15 Tokyo Electron Limited Depositing rhuthenium films using ionized physical vapor deposition (IPVD)
US20080124484A1 (en) * 2006-11-08 2008-05-29 Asm Japan K.K. Method of forming ru film and metal wiring structure
US20090072409A1 (en) 2007-09-14 2009-03-19 International Business Machines Corporation Interconnect Structures Incorporating Air-Gap Spacers
US20090075470A1 (en) * 2007-09-14 2009-03-19 International Business Machines Corporation Method for Manufacturing Interconnect Structures Incorporating Air-Gap Spacers
KR101544198B1 (en) 2007-10-17 2015-08-12 한국에이에스엠지니텍 주식회사 Ruthenium film formation method
US7655564B2 (en) * 2007-12-12 2010-02-02 Asm Japan, K.K. Method for forming Ta-Ru liner layer for Cu wiring
KR20090067505A (en) * 2007-12-21 2009-06-25 에이에스엠지니텍코리아 주식회사 Ruthenium film deposition method
US7799674B2 (en) * 2008-02-19 2010-09-21 Asm Japan K.K. Ruthenium alloy film for copper interconnects
US8084104B2 (en) * 2008-08-29 2011-12-27 Asm Japan K.K. Atomic composition controlled ruthenium alloy film formed by plasma-enhanced atomic layer deposition
US8133555B2 (en) 2008-10-14 2012-03-13 Asm Japan K.K. Method for forming metal film by ALD using beta-diketone metal complex
US9379011B2 (en) 2008-12-19 2016-06-28 Asm International N.V. Methods for depositing nickel films and for making nickel silicide and nickel germanide
US8329569B2 (en) * 2009-07-31 2012-12-11 Asm America, Inc. Deposition of ruthenium or ruthenium dioxide
US8871617B2 (en) 2011-04-22 2014-10-28 Asm Ip Holding B.V. Deposition and reduction of mixed metal oxide thin films
JP2015160963A (en) * 2014-02-26 2015-09-07 東京エレクトロン株式会社 Method and apparatus for depositing ruthenium film, and method for manufacturing semiconductor device
US9607842B1 (en) 2015-10-02 2017-03-28 Asm Ip Holding B.V. Methods of forming metal silicides
US10522549B2 (en) * 2018-02-17 2019-12-31 Varian Semiconductor Equipment Associates, Inc. Uniform gate dielectric for DRAM device
DE102020110480B4 (en) * 2019-09-30 2024-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Middle-of-line interconnect structure and manufacturing process
US11462471B2 (en) * 2019-09-30 2022-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Middle-of-line interconnect structure and manufacturing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4851895A (en) * 1985-05-06 1989-07-25 American Telephone And Telegraph Company, At&T Bell Laboratories Metallization for integrated devices

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61163264A (en) * 1985-01-11 1986-07-23 Hitachi Ltd Formation of oxide film of platinum group metal
JPH0779136B2 (en) * 1986-06-06 1995-08-23 株式会社日立製作所 Semiconductor device
US5183775A (en) * 1990-01-23 1993-02-02 Applied Materials, Inc. Method for forming capacitor in trench of semiconductor wafer by implantation of trench surfaces with oxygen
JPH04364759A (en) * 1991-06-12 1992-12-17 Kawasaki Steel Corp Semiconductor device and manufacture thereof
US5200360A (en) * 1991-11-12 1993-04-06 Hewlett-Packard Company Method for reducing selectivity loss in selective tungsten deposition
US5407855A (en) * 1993-06-07 1995-04-18 Motorola, Inc. Process for forming a semiconductor device having a reducing/oxidizing conductive material
GB2291264B (en) * 1994-07-07 1998-07-29 Hyundai Electronics Ind Method for forming a metallic barrier layer in semiconductor device and device made by the method
US5555486A (en) * 1994-12-29 1996-09-10 North Carolina State University Hybrid metal/metal oxide electrodes for ferroelectric capacitors
US5521121A (en) * 1995-04-03 1996-05-28 Taiwan Semiconductor Manufacturing Company Oxygen plasma etch process post contact layer etch back

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4851895A (en) * 1985-05-06 1989-07-25 American Telephone And Telegraph Company, At&T Bell Laboratories Metallization for integrated devices

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DE19620022A1 (en) 1996-11-21
CN1048819C (en) 2000-01-26
KR960042954A (en) 1996-12-21
JPH08316321A (en) 1996-11-29
CN1147145A (en) 1997-04-09
DE19620022C2 (en) 2002-09-19
GB2300970B (en) 1999-10-13
GB9610393D0 (en) 1996-07-24
TW301020B (en) 1997-03-21
US5637533A (en) 1997-06-10
KR0172772B1 (en) 1999-03-30

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