GB2368721A - Integrated circuit with damascene structure and capacitor - Google Patents
Integrated circuit with damascene structure and capacitor Download PDFInfo
- Publication number
- GB2368721A GB2368721A GB0114306A GB0114306A GB2368721A GB 2368721 A GB2368721 A GB 2368721A GB 0114306 A GB0114306 A GB 0114306A GB 0114306 A GB0114306 A GB 0114306A GB 2368721 A GB2368721 A GB 2368721A
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- GB
- United Kingdom
- Prior art keywords
- layer
- integrated circuit
- capacitor
- openings
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 54
- 239000004020 conductor Substances 0.000 claims abstract description 26
- 230000009977 dual effect Effects 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 description 32
- 239000000463 material Substances 0.000 description 14
- 238000005530 etching Methods 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 241000282461 Canis lupus Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910008807 WSiN Inorganic materials 0.000 description 1
- 239000004964 aerogel Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- -1 xerogels Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The circuit comprises a layer with a dual damascene structure and a capacitor with first and second conductors formed in the layer. The layer may include a stop layer and the damascene structure can include at least a groove and a via where the bottom portion of the groove includes at least a top portion of the stop layer. The stop layer may be formed between the first and second conductors.
Description
236872 1
AN INTEGRATED CIRCUIT INCLUDING A DUAL-DAMASCENE
STRUCTURE AND A CAPACITOR
Field of the Invention
The present invention relates generally to integrated circuits and, more 5 particularly, to dual damascene structures and capacitors in an integrated circuit.
Background of the Invention
Interdigitized or finger capacitors are being used more in integrated circuits as the height of metal lines in the integrated circuits become greater than the space between the metal lines. This occurs because device dimensions are decreasing 0 which results in a corresponding decrease in distance between metal lines. Interdigitized or finger capacitors employ sidewall capacitance, the capacitance produced between adjacent metal lines to form a capacitor.
One example of a finger capacitor is shown in U.S. Patent No. 6.037,621 entitled ON CHIP CAPACITOR STRUCTURE and issued to Wilson. This patent is 5 incorporated herein by reference. The concept of using sidewall capacitance to form capacitors is also discussed in a recent paper entitled Fractal Capacitors, H. Samavati, et al., 1998 ISSCC, Session 16, TD: Advanced Radio-Frequency Circuits, Paper FP 16.6, 256-57, which is incorporated herein by reference. The paper points out that sidewall or fringing capacitance yields a higher capacitance per unit area than conventional parallel 20 plate capacitors as the distance between the plates decreases.
In addition to device dimension decreases, there has been trend to use dual damascene structures instead of single damascene structures. Single damascene is an interconnection fabrication process for integrated circuits in which grooves are formed in an insulating layer and filled with a conductive material to form interconnects. Dual 25 damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, conductive contact (or via) openings are also formed in the insulating layer. A conductive material is formed in the grooves and conductive contact - 1
(or via) openings. The inventor has recognized the need to combine these trends to provide a sidewall capacitor in an integrated circuit also including a dual damascene structure. Summary of the Invention
s The present invention is directed to an integrated circuit including a metallization level that includes both a dual damascene structure and a capacitor. By including these structures in a metallization level, the addition of funkier processing steps may be avoided when forming these different structures. It is to be understood that both the foregoing general description and the following detailed description are exemplary,
0 but are not restrictive, of the invention.
Brief Description of the Drawing
The invention is best understood from the following detailed description
when read in connection with the accompanying drawing. It is emphasized that, according to common practice in the semiconductor industry, the various features of the 5 drawing are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Included in the drawing are the following figures: Fig. 1 is a flowchart diagram illustrating the process for manufacturing an integrated circuit according to an illustrative embodiment of the present invention; 20 Figs. 2-7 are schematic diagrams of an integrated circuit during successive stages of manufacture using the process of Fig. 1.
Fig. 8 is a top view of a partially fabricated integrated circuit including a finger capacitor and a dial damascene structure manufactured according to the process of Fig. 1; - 2
Fig. 9 is a flowchart diagram illustrating the process for manufacturing an integrated circuit according to another illustrative embodiment of the present invention; and Figs. 10-15 are schematic diagrams of an integrated circuit during 5 successive stages of manufacture using the process of Fig. 9.
Detailed Description of the Invention
The illustrative embodiment of the present invention is directed to a process for forming a dual damascene structure. The process includes forming a stack including insulating layers and a stop layer where two masks are formed above the stack.
0 One of the masks is used to form via or contact openings in the insulating layers and to form openings for a capacitor. The second mask is used to form grooves for interconnections in the insulating layers. By forming the openings for the capacitors when the grooves and vies for the dual damascene structure are formed, the number of processing steps and movement of the partially fabricated integrated circuit between 15 systems may be reduced.
Referring now to the drawing, wherein like reference numerals refer to like elements throughout, Fig. 1 is a flow chart diagram illustrating an exemplary embodiment of the present invention. Figs. 2-7 are schematic diagrams illustrating the successive stages of manufacture of an integrated circuit according to the flow chart 20 shown in Fig. 1.
At step 10, a first insulating layer 105 is formed on a substrate 100. The first insulating layer 105 is, for example, a dielectric such as a high-density deposited silicon oxide (e.g., SiO2). Alternatively, the first insulating layer may be a borophosphosilicate glass, a phosphosilicate glass, a glass formed from phosphorous 2s and/or borondoped tetraethyl orthosilicate, spin-on glass, xerogels, aerogels, or other low dielectric constant films such as a polymer, fluorinated oxide and hydrogen silsesquioxane. Further, the insulating layer may include multiple layers where at least one layer is a low dielectric constant material formed between other layers that may have a higher dielectric constant.
- 3
- The substrate lOO is, for example, a semiconductor such as silicon or compound semiconductor such as GaAs or SiGe. Alternatively, the substrate 100 may be an intermediate layer in an integrated circuit such as a dielectric, conductor, or other material. In addition, the upper surface 101 of the substrate 100 may not be planar. In 5 this case, the first insulating layer 105 may be planarized using, for example, chemical mechanical polishing (CMP) as is well known.
At step 15, an etch stop layer 110 is formed above or in direct contact with the first insulating layer 105. In an alternative embodiment, one or more layers may be formed between the etch stop layer 110 and the first insulating layer 105. The material lo for the etch stop layer may be selected to be more etch resistant than the second insulating layer 115 for a selected etchant. In other words, the etch stop layer 110 etches at a slower rate than the second insulating layer 105 when exposed to a selected etchant.
For example, the etch stop layer may be TiN where the second insulating is SiO2.
Further, the etch stop layer may be TafTaN, Si3N4, a silicon-rich oxide, or a multi-layered 5 SiO2 dielectric.
At step 20, a second insulating layer 115 is formed above or in direct contact with the etch stop layer 115. The second layer 115 may be formed using the same materials and processes used to form the first insulating layer 105. At step 25, a first patterned mask 120 is formed above or on the insulating layer 115. The first 20 patterned mask 120 includes openings that correspond to the via or contact openings 125 (hereinafter referred to as "openings") to provide interconnections between different levels in the integrated circuit. In addition, the first patterned mask 120 includes openings that correspond to the openings 127 for a capacitor (hereinafter referred to as the "capacitor openings"). The reticle 90 has a pattern so that capacitor openings 127 25 may be formed when openings 125 are formed.
At step 30, openings 125 and the capacitor openings 127 are opened in the first insulating layer 105, the etch stop layer 110, and the second insulating layer 115.
The openings and the capacitor openings may be opened using conventional etching techniques or a combination of techniques to etch through at least the three different 30 layers. Alternatively, step 30 may etch only the second insulating 115. In this case, at step 40, the exposed portion of the etch stop layer 110 and the corresponding portion of
the first insulating 105 below the exposed portion would be etched to complete the capacitor openings 127 and the openings 125 when the groove is etched. The capacitor openings 127 may be formed in the same metallization level and not above or below each other 5 Illustratively, the openings are formed by: 1) applying a layer of resist material (the first patterned mask) on the second insulating layer 115; 2) exposing the resist material to an energy source which passes through a reticle; 3) removing areas of resist to form the pattern in the resist; and 4) etching the openings 125 and capacitor openings 127. The energy source may be an e-beam, light source, or other suitable lo energy source.
Subsequently, at step 35, a second patterned mask 130 is formed above or on the first patterned mask 120. Illustratively, the second patterned mask 130 is formed by: 1) applying a layer of resist material in the openings 125 and 127 on the first patterned mask 120; 2) exposing the resist material to an energy source which passes 5 through a reticle 95; and 3) removing areas of resist to form the pattern in the resist. The energy source may be an e-beam, light source, or other suitable energy source.
The second patterned mask 130 includes openings for forming the grooves above the openings 125. The patterned mask 130 does not have corresponding openings for the capacitor openings 127 because the etching for these openings has already been 20 completed. If the capacitor openings had not already been completed in the prior step as described above, then at step 35, openings would have been formed in the second patterned mask so that the capacitor's openings could be completed by subsequent processing. At step 40, the second insulating layer 115 is patterned to form grooves 25 135 corresponding to the conductive runners and capacitor to be formed. The second insulating layer 115 may be patterned using conventional etching techniques. During etching, the etch stop layer 110 is used to define the endpoint for this etching process.
The openings are contained or at least partially contained within the borders 136, 138 of the grooves 135. Then, at step 45, the remaining portions of the mask layers 120, 130 are
stripped using well-known techniques and the partially completed integrated circuit is cleaned at step 47 using conventional processes. -
At step 50, a conductive layer 145 is blanket deposited above the second insulating layer 115 and in the openings, grooves, and capacitor openings 127. Then, the s portions of the conductive layer outside the capacitor openings 127 and the grooves 135 and on or above the second insulating layer are removed to complete the interconnect.
This may be accomplished using a conventional chemical mechanical polishing process.
The conductive layer 145 is a conducting material such as tungsten, aluminum, copper, nickel, polysilicon, or other conducting material suitable for use as a conductor and as is 10 known to those skilled in this art.
By using this process a capacitor 170 is formed when the dual damascene structures 175 are formed. As a result, finger capacitors may be incorporated into the process for forming dual daTnascene structures without using additional process steps such as lithography processes and etching. In this ways increased costs for manufacturing 5 an integrated circuit including finger capacitors may be avoided.
In an alternative embodiment, one of more layers, may be formed prior to the deposition of the conductive layer 145. An exemplary barrier layer 147 is shown in Fig. 7. These layers may be barrier layers preventing the migration of moisture and contaminants between the conductive layer and the surrounding layers.
20 For example, if the conductive layer 145 is copper, a barrier layer 147 including layers of Ta and TaN may be deposited on the second insulating layer 120 and in the openings and grooves prior to the deposition of the conductive layer. Where the conductive layer 145 includes Al, a battier layer 147 including layers of (1) Ti and TiN or (2) Ti and TiN and Ti may be used. Other materials for the barrier layer include WSi, 25 TiW, Ta, TaN, Ti, TiN, Cr. Cu. Au, WN, TaSiN, or WSiN. The barrier layer 147 may also function as an adhesion layer and/or a nucleation layer for the subsequently formed conductive layer. In addition, a capping layer, such as Si3N4, TaN, TiN, or TiW may be formed on the upper surface of the conductive layer.
- 6
Figure 8 is a top view of an illustrative finger capacitor and a dual damascene structure formed using the above illustrative embodiment. The finger capacitor 170 includes a first plate 171 and a second plate 172. The interconnection of the capacitor with other portions of the integrated circuit has been omitted for clarity.
5 One skilled in the art would be able to integrate the capacitor in an integrated circuit as necessary to compete the circuitry to be designed.
Subsequently, the integrated circuit is completed by adding, if necessary, additional metal levels that may including interconnects formed using the process above and conventional processes to complete an integrated circuit. The integrated circuit also 10 includes transistors and other components necessary for a particular integrated circuit design. The processes for manufacturing an integrated circuit including these structures are described in 1-3 Wolf, Silicon Processing for the VLSI Era, (1986), which is incorporated herein by reference.
Figures 9-15 illustrate another alternative embodiment of the present 15 invention. Fig. 9 is a flow chart diagram and Figs. 10-15 are schematic diagrams illustrating the successive stages of manufacture of an integrated circuit according to the flow chart shown in Fig. 9.
At step 210, a first insulating layer 305 is formed on a substrate 300. The first insulating layer 305 I is a material as described above with regard to the first 20 insulating layer 105. The substrate 300 is a material as described above with regard to the substrate 100. In addition, the upper surface 301 of the substrate 300 may not be planar. In this case, the first insulating layer 305 may be planarized using, for example, chemical mechanical polishing (CMP) as is well known.
At step 215, an etch stop layer 310 is formed above or in direct contact 25 with the first insulating layer 305. In an alternative embodiment, one or more layers may be formed between the etch stop layer 310 and the first insulating layer 305. The etch stop layer 310 is a material such as the material described above with regard to the first etch stop layer 110.
At step 220, a second insulating layer 315 is formed above or in direct contact with the etch stop layer 315. The second layer 315 may be formed using the same materials and processes used to form the first insulating layer 305. At step 225, a first patterned mask 320 is formed above or on the insulating layer 315. The first s patterned mask 320 includes openings that correspond to the runners or grooves to be formed. In addition, the first patterned mask 320 includes openings that correspond to the openings 327 for a capacitor (hereinafter referred to as the "capacitor openings").
The reticle 390 has a pattern that is translated to the first patterned mask so that the capacitor openings 327 may be formed when openings 325 are formed.
lo At step 230, capacitor openings 327 and grooves 335 are opened in the second insulating layer 315. The grooves 335 may be formed using conventional etching techniques. During etching, the etch stop layer 310 is used to define the endpoint for this etching process. Subsequently, at step 235, a second patterned mask 330 is formed above or on the first patterned mask 320. The second patterned mask is formed so that the 5 openings in this mask correspond to the via or contact openings (hereinafter "openings") to be formed. Further, the second patterned mask includes openings corresponding to the capacitor openings to be formed. A portion of the second patterned mask may be formed on the walls 350, 351 of the grooves 335. As a result, the walls 350, 351 may not be further etched during the formation of the openings. In contrast, a portion of the second 20 patterned layer may not be formed on the walls of the capacitor openings.
At step 240, the etch stop layer 310 and the first insulating layer 305 are patterned to form openings 325 corresponding to the interconnects between layers to be formed. The capacitor openings 327 are also formed by etching the stop layer 310 and the first insulating layer 305. The openings 325 and capacitor openings 327 may be 2s formed using conventional etching techniques or a combination of techniques to etch through at least the two different layers.
The openings 325 are contained or at least partially contained within boundaries defined by the walls 350, 351 of the grooves 335. Then, at step 245, the remaining portions of the mask layers 320, 330 are stripped using well-known techniques 30 and the partially completed integrated circuit is cleaned at step 247 using conventional processes. - 8
At step 250, a conductive layer 345 is blanket deposited above the second insulating layer 315 and in the openings, grooves, and capacitor openings. Then, the portions of the conductive layer outside the capacitor openings 327 and grooves 335 and on or above the second insulating layer 315 are removed. This may be accomplished 5 using a conventional chemical mechanical polishing process. The conductive layer 345 is a conducting material such as tungsten, aluminum, copper, nickel, polysilicon, or other conducting material suitable for use as a conductor as is known to those skilled in this art.
In an alternative embodiment, one of more layers may be formed prior to the deposition of the conductive layer 345 as described above with regard to the first 10 embodiment and shown in Fig. 15. These one or more layers may be referred to as a liner. In addition, a capping layer as described above with regard to the first embodiment may be provided. Subsequently, the integrated circuit is completed by adding, if necessary, additional metal levels that may including interconnects formed using the process above and conventional processes to complete an integrated circuit.
5 Although the three layers including the first insulating layer, the etch stop, and the second insulating layer are shown, the number of these layers may be reduced.
For example, the capacitor and the dual damascene structure may be formed in one or two insulating layers where the openings for the capacitor and the dual damascene structure are formed at substantially the same time.
20 Although the invention has been described with reference to exemplary embodiments, it is not limited to those embodiments. Rather, the appended claims should be construed to include other variants and embodiments of the invention that may be made by those skilled in the art without departing from the true spirit and scope of the present invention.
Claims (10)
- What is Claimed:1 1. An integrated circuit comprising: 2 a layer; 3 a dual damascene structure formed in the layer; 4 a capacitor formed in the layer, the capacitor having a first conductor and 5 a second conductor formed in the layer.1
- 2. The integrated circuit of claim 1 wherein the layer includes at least 2 two layers.1
- 3. The integrated circuit of claim 1 wherein the first conductor and 2 the second conductor are not formed above or below each other.1
- 4. The integrated circuit of claim 1 wherein: 2 the layer includes a stop layer; and 3 the dual daTnascene structure includes at least a groove and a via where a bottom portion of the groove includes at least a top portion of the stop layer.1
- 5. The integrated circuit of claim 4 wherein the stop layer is formed 2 between the first conductor and the second conductor.1
- 6. The integrated circuit of claim 1 wherein the layer includes a stop 2 layer and the stop layer is formed between the first conductor and the second conductor.1
- 7. The integrated circuit of claim 6 wherein the first conductor and 2 the second conductor contact the stop layer.I
- 8. The integrated circuit of claim 7 wherein the first conductor includes a liner and a conductive material.1
- 9. The integrated circuit of claim l wherein the first conductor is a 2 first plate of the capacitor and the second conductor forms the second plate of the 3 capacitor.I
- l O. The integrated circuit of claim 1 further comprising a substrate 2 where the layer is formed on the substrate and the layer is at least not fanned between the 3 first conductor and the substrate.- 10
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US59564200A | 2000-06-16 | 2000-06-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB0114306D0 GB0114306D0 (en) | 2001-08-01 |
| GB2368721A true GB2368721A (en) | 2002-05-08 |
Family
ID=24384078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0114306A Withdrawn GB2368721A (en) | 2000-06-16 | 2001-06-12 | Integrated circuit with damascene structure and capacitor |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2002033394A (en) |
| KR (1) | KR20010113508A (en) |
| GB (1) | GB2368721A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6025226A (en) * | 1998-01-15 | 2000-02-15 | International Business Machines Corporation | Method of forming a capacitor and a capacitor formed using the method |
| EP1020905A1 (en) * | 1999-01-12 | 2000-07-19 | Lucent Technologies Inc. | Integrated circuit device having dual damascene interconnect structure and metal electrode capacitor and associated method for making |
| EP1022783A2 (en) * | 1999-01-12 | 2000-07-26 | Lucent Technologies Inc. | Integrated circuit device having dual damascene capacitor and associated method for making |
| GB2356973A (en) * | 1999-08-30 | 2001-06-06 | Lucent Technologies Inc | Process for manufacturing a dual damascene structure for an integrated circuit using an etch stop layer |
| GB2356974A (en) * | 1999-08-30 | 2001-06-06 | Lucent Technologies Inc | Process for manufacturing a dual damascene structure for an integrated circuit using an etch stop layer |
-
2001
- 2001-06-12 GB GB0114306A patent/GB2368721A/en not_active Withdrawn
- 2001-06-15 JP JP2001181252A patent/JP2002033394A/en not_active Withdrawn
- 2001-06-15 KR KR1020010033891A patent/KR20010113508A/en not_active Application Discontinuation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6025226A (en) * | 1998-01-15 | 2000-02-15 | International Business Machines Corporation | Method of forming a capacitor and a capacitor formed using the method |
| EP1020905A1 (en) * | 1999-01-12 | 2000-07-19 | Lucent Technologies Inc. | Integrated circuit device having dual damascene interconnect structure and metal electrode capacitor and associated method for making |
| EP1022783A2 (en) * | 1999-01-12 | 2000-07-26 | Lucent Technologies Inc. | Integrated circuit device having dual damascene capacitor and associated method for making |
| GB2356973A (en) * | 1999-08-30 | 2001-06-06 | Lucent Technologies Inc | Process for manufacturing a dual damascene structure for an integrated circuit using an etch stop layer |
| GB2356974A (en) * | 1999-08-30 | 2001-06-06 | Lucent Technologies Inc | Process for manufacturing a dual damascene structure for an integrated circuit using an etch stop layer |
Also Published As
| Publication number | Publication date |
|---|---|
| GB0114306D0 (en) | 2001-08-01 |
| KR20010113508A (en) | 2001-12-28 |
| JP2002033394A (en) | 2002-01-31 |
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