[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

GB2366078A - Semiconductor device retaining a resist layer as a buffer layer - Google Patents

Semiconductor device retaining a resist layer as a buffer layer Download PDF

Info

Publication number
GB2366078A
GB2366078A GB0105919A GB0105919A GB2366078A GB 2366078 A GB2366078 A GB 2366078A GB 0105919 A GB0105919 A GB 0105919A GB 0105919 A GB0105919 A GB 0105919A GB 2366078 A GB2366078 A GB 2366078A
Authority
GB
United Kingdom
Prior art keywords
layer
resist
semiconductor device
buffer layer
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0105919A
Other versions
GB0105919D0 (en
Inventor
Daniel P Chesire
Edward A Ehrlacher
William C Finley
Ronald R Gorham
Barbara D Kotzias
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agere Systems LLC
Original Assignee
Agere Systems Guardian Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems Guardian Corp filed Critical Agere Systems Guardian Corp
Publication of GB0105919D0 publication Critical patent/GB0105919D0/en
Publication of GB2366078A publication Critical patent/GB2366078A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A semiconductor device includes a top metal layer 12 and a buffer layer 10 consisting of a photo-definable and compliant resist with good adhesion properties to adjacent layers such as novalak. A passivation layer 18 protects the device from mobile ions, moisture and radiation, and may comprise sublayers of silicon oxide and silicon nitride. The buffer layer provides stress relief between the semiconductor die and the mold compound used in packaging during thermal cycling, and may be the remains of the resist mask used during the etch of the passivation layer. It may also facilitate adhesion between the two halves of a flip-chip. A window 34 etched in the buffer layer and the passivation layer exposes a bond pad 20 for connection to the package wires.

Description

2366078 SEMICONDUCTOR DEVICE HAVING RESIST AS BUFFER LAYER
FIELD OF THE INVENTION
This invention relates to the manufacturing of semiconductor devices. More specifically, the invention relates to a semiconductor device using a resist as a buffer layer 5 over the top layer of the semiconductor device.
BACKGROUND OF THE INVENTION
During the manufacturing of semiconductor devices, layers of dielectric and conductors are deposited onto a wafer, typically but not limited to silicon, until a final layer of conductive material is added, hereinafter referred to as the top metal layer or top 10 layer. Over this top metal layer is typically placed a barrier, CAPS (Coat and Protective Seal) or passivation layer. This passivation layer acts to maintain the mechanical integrity of the semiconductor device, prevent mobile ion diffusion, and provide some radiation protection for the semiconductor device-. I Additionally, a: stress buffer layer (SBL) can be provided over the passivation - 15 layer. Stress buffer layers are occasionally used in the packaging of the final semiconductor product, which includes a silicon wafer die encased in a package. The stress buffer layer reduces the internal stress in the final semiconductor product created during thermal cycling. Thermal cycling occurs during the normal operation of the semiconductor product. For example, a semiconductor product in an engine of an 20 automobile can experience temperatures that range from hundreds of degrees Fahrenheit during engine operation to sub-zero temperatures when idle during the winter months Additionally, even in a temperature controlled environment, the semiconductor device itself can produce significant heat during operation and thus experience thermal cycling.
Internal stress is caused by the die and the package having different thermal 25 expansion coefficients. If a good adhesion exists between the package and the die, the thermal expansion coefficient mismatch causes stress on the die's passivation layer during thermal cycling. This stress can result in cracking of the passivation layer or delamination between the die and package. This can potentially lead to failure of the semiconductor product. The function of the stress buffer layer is to eliminate damage caused by stress between the die and package. By being compliant, the stress buffer layer minimizes the stress that develops between the package and die.
5 Several methods for applying passivation layers over a top metal layer have been used in the semiconductor industry. One such passivation layer is a bi- layer film in which the bottom layer is silicon dioxide and the top layer is silicon nitride. The silicon dioxide layer is flexible and acts as a buffer to relieve stress between the silicon nitride and the top metal layer. Thus, this bottom layer reduces the impact of the mechanisms that result in 10 metal voiding due to the stress migration of the metal and also acts as a mechanical protector for the underlying structures. Although the top silicon nitride layer is more brittle, the silicon nitride layer has the advantage of being resistant to moisture and sodium penetration.
Stress buffer layers are typically formed from polymers or other plastic4ike 15 materials. These materials includ-e-.Polyimides and silicones. However, using these - materials as stress buffer layers have the disadvantages of the cost of the materials and the additional processing steps needed to apply the materials. For example, once the material is applied, the material will require additional processing such as exposing, developing, and curing. A further disadvantage is that additional tooling is required to accomplish 20 these processing steps.
One of the final processes before packaging of the semiconductor device is a CAPS etch. The CAPS etch functions to open a window to the bond pads formed on the top metal layer. The wires connecting the die to the package are then attached to the die at these bond pads during the packaging operations. After the wires are connected to the 25 die, the die is typically encapsulated in a mold compound.
The bond pads are typically exposed by etching the CAPS layer using common lithography techniques. This first involves applying a resist over the CAPS layer. The resist is then exposed and developed. Once the resist mask over the CAPS layer has been formed, the CAPS layer is etched to provide access to the bond pads.
Until very recenoy, resists were characterized as being hygroscopic in that they readily absorbed moisture. Also, any resist remaining on a die before packaging has 5 always been considered a defect and thus a reason to reject the die. As a consequence, once,etching is completed, the resist is removed ftom the semiconductor device by stripping. Once the resist is removed, the die is attached to the package using a molding compound.
SUMMARY OF THE INVENTION
10 A semiconductor device comprises a top layer and a buffer layer, the buffer layer comprising a resist. In one embodiment, a passivation layer is disposed between the top layer and the buffer layer. The top layer can be the top metal layer. The buffer layer comprises a resist, and is preferably a photo-definable and compliant resist. The buffer layer and the passivation layer preferably define at least one window that exposes a bond 15 pad disposed on the top layer.
Many resists currently used with lithography are acceptable for use with this invention, for example resists used in x-ray and e-bearn lithography. Preferable characteristics of the resist include that the resist has good adhesion properties to adjacent layers, is compliant, provides physical protection to the semiconductor die, is resistant to 20 an etch, and relieves stress between the die and mold compound subsequently placed over the die. A presently preferred resist is a photo-definable resist, such as the novalak resin based materials which are currently widely used in the industry. Additives can be included in the resist formulation to improve the properties of the resist for lithography purposes, and/or to improve the properties of the resist formulation for purposes of serving as a 25 buffer layer.
Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, the preferred methods and materials are described below.
BRIEF DESCRIPTION OF TBE DRAWINGS
There are shown in the drawings embodiments of the invention that are presently 5 preferred, it being understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown, FIG. I illustrates a buffer layer'disposed over a passivation layer and a top metal layer of a semiconductor device according to the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODNENTS
10 Referring to FIG. 1, a buffer layer 10, according to the present invention, is illustrated. The buffer layer 10 can act as a stress buffer between the semiconductor die and the packaging. Also, buffer layer 10 can serve as an improved adhesive surface onto which molding compound for encapsulating the semiconductor die in the package can be placed. In a preferred embodiment, the buffer layer 10 is formed using a resist from the 15 final etch.
A top layer 12 of the semiconductor device is preferably covered by one or more protective layers. The top layer 12 is shown as a top metal layer having runners 14, a bond pad 20, and a dielectric between these features, however, it will be appreciated that the top layer 12 could be differently constructed or could be another layer of a 20 semiconductor device. Any number of interceding layers can be positioned between the buffer layer 10 and the top layer 12. For example, the buffer layer 10 can be formed directly over the top layer 12. However, in a presently preferred embodiment, the buffer layer 10 is formed over a passivation layer 18.
The buffer layer 10 is also not limited as to a particular type of resist. Any resist 25 used with lithography is acceptable for use with this invention, for example resists used in x-ray and e-bearn lithography. However, in a presently preferred embodiment of invention, the resist is a photo-definable resist. In a most preferred embodiment of the invention, the resist is a novalak resin based material, which is a compliant material.
Preferable characteristics of the resist include good adhesion properties to adjacent layers, physical protection of the semiconductor die, resistance to an etch, and the provision.of stress relief between the die and mold compound subsequently placed over the die. The buffer layer can include other materials in addition to the resist, so long as the 5 aforementioned properties are substantially retained. Additives are known to be included in resist formulations to improve the properties of the resist for lithography purposes.
Additives can also be included to improve the propeities of the resist formulation for purposes of serving as a buffer layer according to the invention. Examples of such additives would include adhesion promoters, photoactive promoters, materials which 10 promote etch resistance, and materials which improve the properties of the formulation as a buffer layer. Any such additives should not substantially interfere with the lithography and etch processes.
The buffer layer 10 is also not limited as to a particular thickness. The thickness will be varied depending upon the lithography that will be performed and the thickness of 15 the buffer layer that is desired, given the characteristics of the device and the characteristics of the resist. Generally, thicker resist layers require more processing time, and product throughput can become a consideration. However, the thickness of the resist layers used in current lithography procedures is usually between about 0. 5 microns and about 8 microns, and is preferably about 2 microns. The resist can be applied by known 20 methods, and is preferably spun on over the top layer or over the passivation layer.
The top layer 12 of a semiconductor device typically includes metal features, such as the runners 14 and bond pad 20, which are surrounded by dielectric. The top layer 12 can be formed by any suitable method, including such methods as damascene and dual damascene processes. The top layer is usually provided over an interlevel dielectric layer 25 26, which is usually formed over one or more other layers of the device, indicated generally at 30.
In a preferred embodiment of the invention, the passivation layer 18 includes an oxide layer 22 over the top layer 12. The oxide layer 22 fills the spaces between the features of the top layer 12. Alternatively, a separate dielectric deposition step could be used to complete the top layer 12 prior to the deposition of the passivation oxide layer 22.
Although the features such as the runners 14 are typically constructed from 5 electrically conductive materials, for example copper, tungsten, or aluminum, the invention is not limited in this regard. The passivation. layer 18 can be formed over any feature that is formed in the top layer 12. In the serniccinductdr industry, typical features disposed in the top layer 12 are runners 14 and bond pads 20. The invention is also not limited as to the size or type of feature on the top layer 12 over which the passivation layer 18 will be 10 deposited.
The passivation layer 18 can perform many functions. These functions can include, but are not limited to, acting as a barrier to prevent moisture, mobile ions, and radiation from reaching the top layer 12 and also providing mechanical protection to the top metal layer 12. It is known in the art that a passivation layer 18 with such characteristics can be 15 made from many different classes of materials, for example a dielectric--. and this invention is not limited as to a particular material or combination of materials.
The presently preferred passivation layer 18 includes an oxide layer 22. Although the passivation layer 18 can be formed from other oxides, such as an aluminum oxide, the presently preferred passivation layer 18 includes a layer of a silicon oxide. Most 20 preferably, the oxide layer 22 of the passivation layer 18 is formed from a silicon oxide, specifically silicon dioxide (Si02). An advantage of having the oxide layer 22 formed from silicon dioxide is that silicon dioxide tends to be compliant. In this manner, the oxide layer 22 can resist deformation caused by a force being transmitted to the oxide layer 22, which could otherwise cause cracks in the oxide layer 22 and/or damage the underlying top layer 25 12 of the serniconductor device.
The passivation layer 18 can be a single layer, or can comprise two or more sublayers. For -example, there can be other layers disposed over the oxide layer 22. in a presently preferred embodiment, a nitride layer 24 is disposed over the oxide layer 22.
This nitride layer 24 is preferably formed from a silicon nitride. Although a silicon nitride tends to be brittle, forming the nitride layer 24 from a silicon nitride has the advantage of providing a moisture, mobile ions, and radiation resistant barrier.
The passivation layer 18 can also be formed first with a nitride layer and then an 5 oxide layer over the nitride. An additional nitride layer can then be deposited over the oxide layer to form a nitride-oxide-nitride structure. An additional alternative is to have an oxi&-nitride-oxide structure.
The oxide layer 22 can be formed using any process that deposits a layer of dielectric material over the top layer 12. However, the oxide layer 22 is preferably formed 10 using, a high-density plasma chemical vapor deposition (HDP CVD) process.
Advantageously, by using the HDP CVD process, gaps between adjacent features, for example runners 14, in the top layer 12 of the semiconductor device can be filled without the formation of voids.
The deposition of the oxide layer 22 onto the top layer 12 is not limited as to a 15.: particular thickness. However, in a preferred - embodiment of the invention, the oxide layer 22 is applied to a thickness at least as great as the height of the runners 14 disposed on the top layer 12. Applying the material to a height above the runners 14 provides better mechanical protection to the runners 20. For example, if a nitride layer 24 was provided above the oxide layer 22, and a crack propagated through the nitride layer 24, the crack 20 would end at a height above the runners 14. Thus, the stress gradient created by the crack would remain above the level of the runners 14.
A protective package is usually formed over the semiconductor device. The package can be any suitable package for protecting the semiconductor device. The package can be a mold compound that is provided in the space 3 0 over the buffer layer 10.
25 The mold compound can be applied directly over the buffer layer 10, and preferably adheres to the buffer layer 10, as in conventional plastic packages. The package can alternatively be other package constructions known in the art, such as those constructed of 1 8 glass or ceramics. As is known in the art, prior to formation of the package, a contact (not shown) can be attached to the bond pad 20 in the window 34 formed by the etch According to a second embodiment of the invention, a method of forming a stress barrier layer over the top layer of a semiconductor device is disclosed. The method 5 comprises applying a resist as a separate layer over the top layer 12, such as the top metal layer. The resist acts as the stress barrier layer and can be formed directly over the top layer 12 or over interceding layers between the resist and top layer 12. In a presently preferred embodiment of the invention, the interceding layers are a passivation layer 18 as previously discussed.
10 In a most preferred embodiment of the invention, the resist is the resist mask used during the CAPS etch process. In this manner, instead of stripping the resist mask after the etching process, which always occurred previously during the CAPS etch process, the resist mask is retained. Therefore, the modified CAPS etch according to a presently preferred embodiment of the invention comprises applying a resist on the semiconductor 15 device, e)posing and developing the resist, and etching-.the layer over the top metal layer to open a window 34 to the bond pads 20, During this process, the resist mask is typically reduced in thickness during the etching process. However, the etching process introduces roughened features such as pits on the surface of the resist mask. These roughened features enable the molding compound 20 to better adhere to the resist mask.
In an alternative embodiment of the invention, the resist of the resist mask is stripped after etching. Additional resist is then subsequently reapplied, exposed, and developed to form a second resist mask. This second resist mask has not been etched and can therefore provide a buffer layer having a greater thickness than an etched resist mask.
25 In still another alternative embodiment of the invention, the resist mask is not removed after etching. However, a second resist mask is applied over the first resist mask. This involves reapplying the resist, exposing the resist, and developing the resist to form the second mask. This process can provide a thicker barrier than the etched resist mask alone. Additionally, the stripping process is advantageously eliminated.
In a further preferred embodiment of the invention, solvents remaining with the resist mask are removed and cross-links within the resist mask are formed. Although any 5 process of removing the remaining solvents and forming cross-links within the resist mask is acceptable for use with this invention, the presently preferred process is to bake the resist.
In a preferred embodiment of the invention, the temperature of the bake is limited so as to not damage the semiconductor device. In a most preferred embodiment of the 10 invention, the temperature is limited to about 260T, which corresponds approximately to the temperature of solder reflow.
In an alternative embodiment of the invention, the resist mask as a top layer can be used as a layer between opposing halves of a flip chip. This layer can thereby act to facilitate adhesion between the two halves. Also, the layer can act as a stress buffer 15 between the two halves:
It should be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application. The invention can take other specific forms without departing 20 from the spirit or essential attributes thereof for an indication of the scope of the invention.

Claims (22)

CLAIMS:
1. A semiconductor device, comprising:
ò top layer; and, ò buffer layer disposed over said top layer, said buffer layer comprising a resist.
5
2. The semiconductor device according to claim 1, wherein said buffer layer defines at least one window, said window exposing a bond pad disposed on said top layer.
3. The semiconductor device according to claim 1, wherein said resist isa photo-definable resist.
4. The semiconductor device according to claim 3, wherein said resist is 10 compliant.
5. The semiconductor device according to claim -3, wherein said resist is a novalak resin based material.
6. The semiconductor device according to claim 1, further comprising a passivation layer disposed between said top layer and said buffer layer.
15
7. The semiconductor device according to claim 6, wherein said passivation layer comprises a silicon oxide layer and a silicon nitride layer.
8. The semiconductor device according to claim 6, wherein said buffer layer and said passivation layer define at least one window, said window exposing a bond pad disposed on said top layer.
20
9. A semiconductor device, comprising:
a top layer; a passivation layer disposed over said top layer; and, a buffer layer deposited over said passivation layer, said buffer layer comprising a resist, said buffer layer and said passivation layer defining at least one window, said 25 window exposing a bond pad disposed on said top layer.
10. A semiconductor device, comprising:
a semiconductor die having a top layer; an adhesion layer disposed over said top layer, said adhesion layer comprising a resist; and, a package, said adhesion layer attached to said package.
11. The semiconductor device according to claim 10, further comprising a 5 passivation layer disposed between said top layer and said adhesion layer,
12. The semiconductor device according to claim 11, wherein said passivation layer comprises a silicon oxide layer and a silicon nitride layer.
13. The semiconductor device according to claim 10, wherein said adhesion layer defines at least one window, said window exposing a bond pad disposed on said top 10 layer.
14. The semiconductor device according to claim 10, wherein said resist is a photo-definable resist.
15. The semiconductor device according to claim. 14, wherein said resist is compliant.
15
16. The semiconductor device according to claim 14, wherein said resist is a novalak resin based material.
17. A method of making a semiconductor device, comprising the steps of a) forming a semiconductor die having a top layer; b) applying a buffer layer over the top layer, said buffer layer 20 comprising a resist; and, c) applying a package layer over said buffer layer.
18. The method of claim 17, wherein after said buffer layer application step b) and before said package layer application step c), performing the steps of exposing and developing the resist of said buffer layer to define openings in the resist.
25
19. The method of claim 17, further comprising the step of depositing a passivation layer over said top layer.
20. The method of claim 19, further comprising the steps of exposing and developing the resist of said buffer layer, and etching to define openings in said passivation layer.
2 1. The method of claim 20, wherein after said etching step and before said 5 package layer application step, another layer of resist is applied to said resist layer that is on said passivation layer.
22. The method of claim 17, wherein said resist is a novalak based resin.
GB0105919A 2000-03-09 2001-03-09 Semiconductor device retaining a resist layer as a buffer layer Withdrawn GB2366078A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US52158600A 2000-03-09 2000-03-09

Publications (2)

Publication Number Publication Date
GB0105919D0 GB0105919D0 (en) 2001-04-25
GB2366078A true GB2366078A (en) 2002-02-27

Family

ID=24077294

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0105919A Withdrawn GB2366078A (en) 2000-03-09 2001-03-09 Semiconductor device retaining a resist layer as a buffer layer

Country Status (3)

Country Link
JP (1) JP2001284499A (en)
KR (1) KR20010088439A (en)
GB (1) GB2366078A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8844826B2 (en) 2006-07-10 2014-09-30 Nxp B.V. Integrated circuit transponder, method of producing an integrated circuit and method of producing a transponder

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4328262A (en) * 1979-07-31 1982-05-04 Fujitsu Limited Method of manufacturing semiconductor devices having photoresist film as a permanent layer
EP0122631A2 (en) * 1983-04-15 1984-10-24 Hitachi, Ltd. Electronic device having a multi-layer wiring structure
EP0251347A1 (en) * 1986-04-23 1988-01-07 Koninklijke Philips Electronics N.V. Method of covering a device with a first layer of silicon nitride and with a second layer of a polyimide, and device covered by means of the method
EP0275588A1 (en) * 1986-12-19 1988-07-27 Koninklijke Philips Electronics N.V. Method of fabricating a semiconductor device with reduced packaging stress
US5013689A (en) * 1985-08-14 1991-05-07 Mitsubishi Denki Kabushiki Kaisha Method of forming a passivation film
US5286679A (en) * 1993-03-18 1994-02-15 Micron Technology, Inc. Method for attaching a semiconductor die to a leadframe using a patterned adhesive layer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4328262A (en) * 1979-07-31 1982-05-04 Fujitsu Limited Method of manufacturing semiconductor devices having photoresist film as a permanent layer
EP0122631A2 (en) * 1983-04-15 1984-10-24 Hitachi, Ltd. Electronic device having a multi-layer wiring structure
US5013689A (en) * 1985-08-14 1991-05-07 Mitsubishi Denki Kabushiki Kaisha Method of forming a passivation film
EP0251347A1 (en) * 1986-04-23 1988-01-07 Koninklijke Philips Electronics N.V. Method of covering a device with a first layer of silicon nitride and with a second layer of a polyimide, and device covered by means of the method
EP0275588A1 (en) * 1986-12-19 1988-07-27 Koninklijke Philips Electronics N.V. Method of fabricating a semiconductor device with reduced packaging stress
US5286679A (en) * 1993-03-18 1994-02-15 Micron Technology, Inc. Method for attaching a semiconductor die to a leadframe using a patterned adhesive layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8844826B2 (en) 2006-07-10 2014-09-30 Nxp B.V. Integrated circuit transponder, method of producing an integrated circuit and method of producing a transponder

Also Published As

Publication number Publication date
JP2001284499A (en) 2001-10-12
KR20010088439A (en) 2001-09-26
GB0105919D0 (en) 2001-04-25

Similar Documents

Publication Publication Date Title
US5682065A (en) Hermetic chip and method of manufacture
US5854141A (en) Inorganic seal for encapsulation of an organic layer and method for making the same
US6806168B2 (en) Healing of micro-cracks in an on-chip dielectric
US6028347A (en) Semiconductor structures and packaging methods
US7462940B2 (en) Semiconductor component comprising flip chip contacts with polymer cores and method of producing the same
US4172907A (en) Method of protecting bumped semiconductor chips
JP2002075981A (en) Semiconductor device protective film having polymer material and intensified adhesion and its manufacturing method
US8119453B2 (en) Chip-size-package semiconductor chip and manufacturing method
US5438022A (en) Method for using low dielectric constant material in integrated circuit fabrication
EP0318954B1 (en) Semiconductor device having a composite insulating interlayer
WO2016073962A1 (en) Reliability improvement of polymer-based capacitors by moisture barrier
KR870000350B1 (en) Electronic apparatus with a multiplex distributing wire system
JP2000188357A (en) Semiconductor device and manufacture thereof
JPS63226046A (en) Manufacture of semiconductor device with reduced packaging stress
US5045918A (en) Semiconductor device with reduced packaging stress
JP2925960B2 (en) Method for manufacturing semiconductor device
US5525839A (en) Method of packing an IC die in a molded plastic employing an ultra-thin die coating process
GB2366078A (en) Semiconductor device retaining a resist layer as a buffer layer
CN108511350B (en) Packaging method of power device and power device
JP2649157B2 (en) Semiconductor device
US12148717B2 (en) Through wafer trench isolation between transistors in an integrated circuit
KR100374300B1 (en) Copper layer for semiconductor fabrication method
JPS60145628A (en) Semiconductor device
JP2865224B2 (en) Resin-sealed semiconductor device
JPS62256457A (en) Semiconductor device

Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)