GB2353154A - Phase-locked loop circuit adapted to perate both as a digital modulator and as a frequency synthesizer at the same time - Google Patents

Abstract

A phase-locked loop circuit comprises a voltage controlled oscillator 101, means 103 for receiving a reference frequency and the output of a divider as inputs, the means 103 providing a signal for controlling said oscillator, a frequency multiplier 201 which multiplies the output of the oscillator and then applies the multiplied output to the frequency divider 102 to be divided thus producing said output of the divider. A digital input source 105 controls the divide ratio of the divider and the circuit may be adapted to operate as a digital modulator, or as a frequency synthesizer, or as both at the same time. The minimum step size of the digital input controlling the divide ratio of the divider 102 can thus effect a phase change of 1/m cycle (2 f /m radians) at the output of the oscillator where m is the multiplying factor of the frequency multiplier. The circuit increases the phase resolution at the output of the voltage controller oscillator.

Description

2353154 IMPROVEMENTS IN OR RELATING TO PHASE-LOCKED LOOP CIRCUITS This

invention relates to phase-locked loop (PLL) circuits.

A PLL circuit may be used as a frequency synthesizer or as a digital modulator where a digital input controls a divider, or counter, in the PLL circuit to provide an output frequency corresponding to the digital input in the case of a frequency synthesizer, or an output frequency or phase which varies with the digital input in the case of a digital modulator. Known PLL circuits have a resolution of I cycle (2n radians) long term phase change at the output due to a unit impulse change in the digital input to the divider.

Modem wireless systems, however, may require finer resolution of, for example, Y2cycle or 1/4cycle (a or n/2 radians respectively). Previous attempts to achieve a finer resolution in the short term have included the use of oversampling systems (based on delta-sigma modulator techniques) to generate inputs to the PLL circuit, but such inputs have effectively comprised infinitely long duration sequences which continue long after the required phase change transient has passed. The continuing sequence may generate unwanted noise at the PLL output. The oversampling systern must actively calculate its output, and it is impractical to store such sequences in a table or read only memory (ROM).

According to this invention a phase-locked loop circuit comprises a voltage controlled oscillator, means for receiving as inputs a reference frequency and the output of a divider and for providing, in dependence on the frequency and/or phase difference betv.-een said inputs, a signal for controlling said oscillator, and a frequency multiplier for multiplying the output frequency of the oscillator and for applying the multiplied output frequency to the divider to be divided thereby to produce said output of the divider.

There may be provided a digital input source for controlling the divide ratio of the divider.

The digital input source may be a modulating signal which serves to modulate the divide ratio of the divider whereby the circuit is adapted to operate as a diaital modulator.

The digital input source may serve to control the divide ratio of the 5 divider whereby the circuit is adapted to operate as a frequency synthesizer.

The digital input source may serve to control the divide ratio of the divider whereby the circuit is adapted to operate both as a digital modulator and as a frequency synthesizer at the same time.

The invention will now be described by way of example with reference to the accompanying drawings, in which:

FIG. I is a schematic diagram of a known PLL circuit; and FIG.2 is a schematic diagram of a PLL circuit -embodying the invention.

Referring now to FIG. 1, a known PLL circuit, which may serve as a frequency synthesizer or as a digital modulator, comprises a voltage controlled oscillator (VCO) 10 1, a divider 102, a phase-frequency detector 103, and a low pass loop filter 104. In operation, the output of VCO 101, fo,,t, is divided down in divider 102 by a divide ratio controlled by a digital input to the divider from a digital input source 105. The divided down output, ff, of divider 102 is compared with a fixed reference frequency, fin from a reference frequency source 106, in phase-frequency detector 103 to develop a control signal for controlling the frequency of VCO 101 after passing through the low pass loop filter 104. For an input frequency fin and a digital input of No setting the divide ratio in divider 102 of N= N', the output frequency f""t is equal to N, x fin. If the value of N is changed to a value N,, + 6N, then the output frequency, fit + ff.,q, is equal to (N, + 6N) x fin. The change in output frequency is Mut which is equal to fin x 6N. As will be appreciated, for changes within the PLL circuit bandwidth, the PLL circuit is behaving as a numerically controlled oscillator.

The phase-frequency detector 103 can be a known phase-frequency detector device, or a device which combines separate frequency detector and phase detector devices by switching and/or multiplexing. The action of phasefrequency detector 10') is to bring the output frequency of VCO 10 1 close to its intended value (rather than a harmonic or sub-harmonic of its intended value), and also to establish the intended phase relationship between the reference fequency fin and the output ff of divider 102.

The action of the I'LL is to adjust the voltage controlling VCO 101 such that the divider output ff is synchronized with the reference frequency fi, Digital input signals are applied as a sequence of numbers to the divider to control the divider ratio N. their application being synchronized with, for example, the falling edge of each cycle 5 of the reference frequency f, or the divider output ff.

It is instructive to consider the case where the sequence for N is provided by N,... No, N2, No......... which denotes a sequence of numbers whose previous, current (underscored), and future value is No, and the case where the sequence 6N is a unit impulse 8N, I 0, 0, 0,1, 0, 0, 0 I which denotes a sequence whose previous value was 0, current (underscored) value is 1, and future value is 0. Note that all values of N, and 6N, are integers, and that SN, is the smallest increment that can be applied to the digital input of divider 102.

Considering the case where the sequence Ns is presented as digital input, it has already been noted that the VCO output frequency when the loop has locked will be fo.t = No x fi, Because of the relationship between VCO output frequency and VCO output phase, Nvhere folt d(Doul 2;r dt there is a conceptual VCO output phase ramp with time, where = 27E No fi,,.

dt If a time varvincy change such as 5N, is added to N, and presented as digital input to the divider, there is a resulting VCO output phase change superimposed on the VCO output phase ramp described. In this case the divider, in practice a counter circuit, will count for an extra cycle of the VCO frequency which will delay the divided down signal by one period of the VCO oscillator 101. The action of the PLL circuit gives rise to a transient which adJusts the phase of the VCO 10 1 until the extra count is compensated for. This advances the phase of VCO 10 1 by I cycle (21r radians) in the long term. Thus the unit impulse applied to the digital input of divider 102, which is the smallest change that can be applied. gives rise to an output phase step of I cycle ( 2a radians) at the -4output of VCO 10 1, and this is the output phase resolution of the PLL circuit. No finite duration sequence of integer values can result in a long term phase change at the output of less than I cycle (27r radians). Thus finer resolution phase transitions, for example 1/4 cycle or 7r/2 radians, cannot be achieved in known PLL circuits using finite duration input sequences. Modem wireless systems may require finer resolutions of, for example, V2 cycle or 1/4cycle (7r or 7r/2 radians).

Referring now to FIG-2, an exemplary PLL circuit embodying the invention comprises the components already described with reference to FIG. I which, accordingly, bear the same reference signs. In addition, however, the PLL circuit of FIG.2 comprises a frequency multiplier 201 interposed between the output of VCO 10 1 and the input of divider 102. The output frequency of frequency multiplier 201 is in times its input frequency. In operation, a unit impulse sequence 5Ns added at the digital input to divider 102 leads to a long-term phase change of I cycle (2n radians) at the counting input to the divider. Because of the presence of frequency multiplier 201, a 1'5 phase change of only I /in cycle (27r/m. radians) at the output of VCO 101 is required to establish the 1 cycle (27r radians) phase change at the input to the divider. Thus a unit impulse at the digital input to the divider gives rise to a long-term phase change of I M cycle (27r/m radians) at the output of VCO 10 1, and this is the output phase resolution of the new system. Hence finite duration sequences of integer values at the digital input of the divider can give rise to phase changes with fine long-term resolution.

For example, for a system requiring a VCO output phase resolution of 1/4 cycle (Tr/2 radians) the multiplying factor m of a frequency multiplier 201 will be 4.

This may be useful in modem wireless systems requiring output phase resolution of 1/4 cycle'(7r/2 radians), such as GMSK (Gaussian Minimum Shift Keying) systems.

The invention permits phase modulation in fine resolution steps by means of a finite duration sequence of numbers presented at the digital input to the divider of the PLL circuit.

Finite duration integer sequences can be stored in a table or in a ROM.

Phase modulation can be achieved by sequentially reading the integer sequence from the table or ROM, according to a modulating input value, and presenting the sequence at the digital input to the divider. A digital modulator embodying the invention does not require a computationally intensive oversampling digital system to provide the digital input to the PLL, and is likely to be smaller, less expensive and is likely to consume less power. Also, once a phase transient has been effected at the VCO output, no further dynamic digital input signal is required, thus avoiding extra noise which might have been introduced in the PLL circuit of FIG. I by long term input sequences.

As will be appreciated, for the same reference frequency in both FIGs. I and 2, the divide ratio in FIG.2 will have to be m x the divide ratio in FIG. I to achieve the same output frequency from the VCO 10 1.

Depending on the digital input to divider 102, the PLL circuit may serve as a variable frequency source, e.g., as a frequency synthesizer, or as a digital modulator, or both as a frequency synthesizer and as a digital modulator at the same time.

CIaims 1. A phase-locked loop circuit comprising a voltage controlled oscillator, means for receiving as inputs a reference frequency and the output of a divider and for providing, in dependence on the frequency and/or phase difference between said inputs a signal for controlling said oscillator, and a frequency multiplier for multiplying the output frequency of the oscillator and for applying the multiplied output frequency to the divider to be divided thereby to produce said output of the divider.

2. A circuit as claimed in claim I comprising -a digital input source for controlling the divide ratio of the divider.

3. A circuit as claimed in claim 2 wherein the digital input source is a modulating signal which serves to modulate the divide ratio of the divider whereby the circuit is adapted to operate as a digital modulator.

4. A circuit as claimed in claim 2 wherein the digital input source serves to control the divide ratio of the divider whereby the circuit is adapted to operate as a frequency synthesizer. 5. A circuit as claimed in claim 2 wherein the digital input source serves to control the divide ratio of the divi der whereby the circuit is adapted to operate both as a digital modulator and as a frequency synthesizer at the same time. 20 6. A phase-locked loop circuit substantially as herein described with reference to FIG.2 of the accompanying drawings.

I.