GB2344694A - High dielectric constant capacitors - Google Patents
High dielectric constant capacitors Download PDFInfo
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- GB2344694A GB2344694A GB9929376A GB9929376A GB2344694A GB 2344694 A GB2344694 A GB 2344694A GB 9929376 A GB9929376 A GB 9929376A GB 9929376 A GB9929376 A GB 9929376A GB 2344694 A GB2344694 A GB 2344694A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 61
- -1 tungsten silicide nitride Chemical class 0.000 claims abstract description 42
- 239000010936 titanium Substances 0.000 claims abstract description 32
- 230000004888 barrier function Effects 0.000 claims abstract description 31
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims abstract description 26
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 22
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 21
- 229910052721 tungsten Inorganic materials 0.000 claims description 28
- 239000010937 tungsten Substances 0.000 claims description 28
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 9
- 230000009467 reduction Effects 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 4
- 239000000758 substrate Substances 0.000 claims 1
- 229910008807 WSiN Inorganic materials 0.000 abstract description 9
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 238000012545 processing Methods 0.000 abstract description 3
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 229910021529 ammonia Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000006731 degradation reaction Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 206010067484 Adverse reaction Diseases 0.000 description 1
- 229910007264 Si2H6 Inorganic materials 0.000 description 1
- 230000006838 adverse reaction Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Tungsten nitride (WN) and/or tungsten silicide nitride (WSiN) diffusion barrier layers are situated between a titanium electrode and a tantalum pentoxide (Ta<SB>2</SB>O<SB>5</SB>) dielectric layer of a DRAM capacitor. The diffusion barrier layer(s) prevent reaction between the titanium electrode and the tantalum pentoxide during thermal processing of the device structure.
Description
TUNGSTEN NITRIDE AS AN OXYGEN DIFFUSION BARRIER WHEN USED WITH
TANTALUM PENTOXIDE AS PART OF A METAL-OXIDE-METAL CAPACITOR
FIELD OF THE INVENTION
The present invention is directed, in general, to integrated circuits and, more specifically, to an integrated circuit that includes a capacitor.
BACKGROUND OF THE INVENTION
Integrated circuits in general, and CMOS devices in particular, have continued to gain wide spread usage as user demands for increased functionality and enhanced benefits continues to increase. In order to meet this demand, the integrated circuit industry continues to decrease the size of circuit structures in order to place more circuits in the same size integrated circuit area thereby continuously increasing the packing density for a given chip size. Over the last several years, structures have gone from 1.2 micron gate areas (1 Meg capacity) in the past, down to gate structure areas of 0.25 microns (1 Gbit capacity) currently and promise to become even smaller in the near future.
For example, the ever increasing demand for computer memory to facilitate calculations and data storage has fostered intense development efforts in the area of
Dynamic Random Access Memory (DRAM), and especially embedded DRAM. The
DRAM is generally a collection of transistor devices with each having an integrated circuit capacitor typically connected to its source electrode thereby forming a memory cell. This collection of memory cells is then arranged into a memory structure using a word line and a bit line to address each memory cell. This integrated capacitor may store an electrical charge to represent a logical"1"or store no electrical charge for a logical"0"as instructed by the word and bit control lines.
Construction of these memory capacitors consists of using typically a tungsten (W) plug structure for 0.25 micron technology connected to the source of the transistor, which then supports a barrier layer, a bottom electrode, a dielectric material, such as tantalum pentoxide and then a top electrode in sequence. There are many other uses for capacitors in integrated circuits.
As the size technology of CMOS devices continues to shrink, the structure for a given memory size or circuit capability also shrinks as noted above. For example, the bond pads, which allow the integrated circuit to connect to external circuitry, cannot continue to shrink indefinitely. Currently, an integrated circuit package may have about 200 bond pads that are 50 microns by 50 microns in size. Shrinking topology coupled with this bond pad lower limitation results in an excess of empty space around the bond pads. This at ! ows for the inclusion of additional embedded memory around the bond pads. The use of higher dielectric constant oxides such as tantalum pentoxide as substitutes for silicon dioxide have allowed smaller structures still.
In an attempt to add the above-mentioned memory in certain conventional
CMOS technologies, some manufacturers have used titanium nitride (TiN) to form a barrier layer with a titanium (Ti) lower electrode in conjunction with the use of silicon dioxide, a conventional stack-up being Ti/TiN/silicon dioxide/AI/TiN. However, migration from silicon dioxide to tantalum pentoxide (Ta20$) as the dielectric layer of the capacitor poses problems. The TiN barrier precludes the use of such a structure in conjunction with tantalum pentoxide because the underlying Ti layer getters the oxygen from the tantalum pentoxide via diffusion through the barrier, thus reducing the tantalum pentoxide to elemental Ta, creating electrical leakage paths or shorts. This results in general circuit performance degradation or failure. Note that if the TiN is not deposited optimally, it will have minicracks or other defects that form fast diffusion paths.
This interdiffusion of oxygen through the TiN also causes the underlying Ti to oxidize. Moreover, such a TiN underlayer decomposes at about 600C, preventing subsequent high temperature processing. Accordingly, what is needed in the art is a
CMOS structure and a process of fabrication therefore in which embedded memory can be added without substantial changes in the fabrication processes typically used to manufacture CMOS technologies.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides for use with an integrated circuit, a capacitor with a diffusion barrier of tungsten nitride (WN) as an alternative to titanium nitride when the dielectric is tantalum pentoxide.
In another embodiment, tungsten silicide nitride (WSiN) is used instead of, or in addition to titanium nitride when the dielectric is tantalum pentoxide. The silicon contained in the WSiN does not readily reduce the tantalum pentoxide and hence, tungsten silicide nitride is an effective barrier.
One application for such a capacitor is in memory, optionally embedded, having a transistor in contact with an interconnect formed within a dielectric layer overlaying the transistor. In one embodiment, the memory comprises a capacitor located on the dielectric layer that contacts the interconnect. In this particular embodiment, the capacitor inclues a first electrode located on the interconnect wherein the first electrode comprises a layer of titanium and tungsten nitride or tungsten silicide nitride and substantially free of a titanium nitride layer. Tungsten nitride is preferred.
Moreover, the thickness of the first electrode may, of course, vary depending on the design. However, in one particular embodiment, the first electrode may have a thickness ranging from about 10 nm to about 60 nm.
In the present invention, the capacitor further inclues a capacitor dielectric located on the first electrode, which is subject to reduction by titanium. For example, in one embodiment, the capacitor dielectric may be tantalum pentoxide. Additionally, the capacitor includes a second electrode located on the capacitor dielectric.
In another embodiment, the first electrode includes a barrier layer in contact with the capacitor dielectric that is located between the first electrode and the capacitor dielectric. The barrier layer serves to prevent or inhibit cross diffusion of diverse materials. In such embodiments, the barrier layer may be comprised of tungsten nitride. In yet other embodiments, the barrier layer may be tungsten silicide nitride wherein the barrier has a thickness less than about 100 nm.
In a further embodiment, the top electrode also comprises tungsten nitride or tungsten silicide nitride or both.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIGURE 1 illustrates cross-sectional view of a prior art embedded memory cell structure ; and
FIGURE 2 illustrates a cross-sectional view of one embodiment of an embedded memory cell structure covered by the present invention.
DETAILEDDESCRIPTION
Referring initially to FIGURE 1, illustrated is a prior art capacitor as part of an embedded memory cell structure 100, showing a transistor structure 105, an interconnect 110, and a capacitor 115. The memory capacitor 115, comprises a first (bottom) electrode comprising an adhesion/conduction layer 120 and a barrier layer 125, a dielectric material 130, and a top electrode comprising an electrical conduction layer 140, and an optional TiN layer 135. As stated earlier, tungsten (W) is typically used for 0.25 micron technology to form the interconnect 110. In Figure 1, titanium (Ti) is used to form layer 120, with titanium nitride (TiN) forming layer 125. The dielectric layer 130 is then formed using silicon dioxide or tantalum pentoxide, and aluminum or copper forms layer 140.
As stated earlier, the Ti/TiN layers are in contact with the tantalum pentoxide, which causes the Ti to chemically reduce the tantalum pentoxide. This results in electrical leakage paths or shorts causing general circuit performance degradation or failure and therefore poor device reliability when the dielectric is tantalum pentoxide.
Turning now to FIGURE 2, illustrated is a preferred embodiment of a capacitor of the present invention as part of an embedded memory cell structure 200 showing a transistor structure 205, and an interconnect 210 contacting a capacitor 215. The capacitor 215, comprises a first (bottom) electrode comprising an adhesion/electrical conduction layer 220 and a barrier layer comprising tungsten nitride or tungsten silicide nitride 225 located on the interconnect, a dielectric material 230 subject to reduction by titanium located on the first electrode, a second electrode 240 located over the dielectric material, and an optional layer 235 as shown. In one embodiment as shown in FIGURE 2, the first layer located on the interconnect is titanium and layer 225 is tungsten nitride, tungsten silicide nitride, or any combination thereof. In an advantageous embodiment, the first electrode may be deposited to a thickness of about 10 nm to about 60 nm at a temperature ranging from about 150CC to about 400duc, under a pressure ranging from about 2 milliTorr to about 6 milliTorr. The deposition of the first electrode may be accomplished by physical vapor deposition at a power ranging from about 1 to about 12 kilowatts. Tungsten nitride or tungsten nitride silicide is used to form layer 225 by reactive sputtering of tungsten or tungsten silicide in nitrogen. The tungsten silicide and tungsten nitride may be deposited as a functionally gradient material, wherein the nitrogen and silicon content are made to deliberately vary smoothly within the film thickness. The dielectric layer 230 is then formed using tantalum pentoxide by conventional deposition processes. Finally, aluminum or copper forms layer 235, which is used to make electrical connection. Layer 235 may optionally be capped with titanium nitride or preferably tungsten nitride or tungsten silicide.
Note that the deposition of tungsten nitride and tungsten silicide nitride may also be accomplished by chemical vapor deposition (CVD). Tungsten nitride is typically applied using WF6 and ammonia (NH3) as precursors, while Si2H6 is added to the mix to make tungsten silicide nitride. However, the present invention is preferably done in the absence of ammonia, which generates hydrogen. While not wishing to be held to any theory, it is believed that the hydrogen reduces the tantalum pentoxide. Nitrogen trifluoride should be used instead of ammonia as a nitrogen source when using CVD.
The embodiment illustrated in FIGURE 2 is substantially free of titanium nitride (TiN) in the first electrode, which eliminates the possibility of adverse reactions with dielectric materials using tantalum pentoxide. That is, there is a reliable oxygen diffusion barrier between the titanium and the dielectric to prevent reduction of the dielectric, which would cause an electrical degradation in the structure. Also, tungsten nitride and tungsten silicide nitride extend the thermal budget to allow processing at 800C prior to deposition of the top electrode, as TiN, which is not present, decomposes at around 600C. Further benefit with respect to reducing oxygen diffusion, is gained if a layer (not shown) of tungsten nitride or tungsten silicide nitride is inserted between the dielectric layer 230 and the conduction layer 235. Also, tungsten nitride and tungsten silicide nitride may substitute for titanium nitride in the optional layer 240. Layer 240 is etched away if contact is to be made to the top of the electrode.
As shown, the first electrode 220 contacts the interconnect 210, which in tum, contacts the source region 206 of the transistor 205. The transistor 205 of the embedded memory may be of conventional design in that it also includes a word line 207, a bit line 208 and a drain region 209. A dielectric layer, such as silicon dioxide is formed over the transistor 205 to electrically isolate it.
Embodiments of capacitor stack-ups of the present invention include Ti/WN or WSiN or both/Ta2Os or other titanium reducible dielectric/AI or other electrical conductor, Ti/WN or WSiN or both/Ta205 or other titanium reducible dielectric/WN or WSiN or both/AI or other electrical conductor, Ti/WN or WSiN or both/Ta2Os or other titanium reducible dielectric/Al/TiN, and Ti/WN or WSiN or both/Ta2Os or other titanium reducible dielectricl WN or WSiN or both/AI or other electrical conductor/TiN.
From the foregoing, it is readily apparent that the present invention provides for use with an integrated circuit, an embedded memory having a transistor in contact with an interconnect formed within a dielectric layer overlaying the transistor. The embedded memory may comprise a capacitor located on the dielectric layer that contacts the interconnect.
Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form.
Claims (20)
1. A method for fabricating a capacitor, comprising the steps of:
forming a first electrode over a substrate, wherein the first electrode comprises a layer of titanium, and a first barrier layer selected from the group consisting of tungsten nitride, tungsten silicide nitride and mixtures thereof and wherein the first electrode is substantially free of a titanium nitride layer;
forming a capacitor dielectric over the first electrode, wherein the capacitor dielectric is subject to reduction by titanium; and
forming a second electrode comprising an electrically conductive layer over the capacitor dielectric.
2. The method as recited in Claim 1, wherein the step for forming the second electrode further comprises a step for depositing a second barrier layer selected from the group consisting of tungsten nitride, tungsten silicide nitride and mixtures thereof and wherein the second barrier layer is between the capacitor dielectric and the electrically conductive layer.
3. The method as recited in Claim 1, wherein the step of forming a capacitor dielectric includes forming the capacitor dielectric out of tantalum pentoxide.
4. The method as recited in Claim 1, wherein the barrier layer is in contact with the capacitor dielectric and located between the first electrode and the capacitor.
5. The method as recited in Claim 1, wherein the barrier layer is tungsten nitride and has a thickness less than about 60 nm.
6 The method as recited in Claim 1, wherein the step of forming a first electrode inclues the step of forming a first electrode having a thickness ranging from about 10 nm to about 60 nm.
7. A capacitor produced by the method of claim 1, wherein the capacitor comprises an electrode of titanium and tungsten nitride, and a tantalum pentoxide dielectric.
8. A capacitor, comprising :
a first electrode comprising a layer of titanium, and a first barrier layer selected from the group consisting of tungsten nitride, tungsten silicide nitride and mixtures thereof and substantially free of a titanium nitride layer ;
a capacitor dielectric over the first electrode, the dielectric subject to reduction by titanium ; and
a second electrode over the capacitor dielectric comprising an electrically conductive layer.
9. The capacitor as recited in Claim 8, wherein the second electrode further comprises a second barrier layer selected from the group consisting of tungsten nitride, tungsten silicide nitride and mixtures thereof and wherein the second barrier layer is between the capacitor dielectric and the electrically conductive layer.
10. The capacitor as recited in Claim 8, wherein the capacitor dielectric is tantalum pentoxide.
11. The capacitor as recited in Claim 8, wherein the barrier layer is in contact with the capacitor dielectric and located between the first electrode and the capacitor.
12. The capacitor as recited in Claim 8, wherein the first barrier layer has a thickness less than about 30 nm.
13. The capacitor as recited in Claim 8, wherein the first electrode has a thickness ranging from about 10 nm to about 60 nm.
14. A capacitor according to claim 8, wherein the capacitor comprises a first electrode of titanium and tungsten nitride, and a tantalum pentoxide dielectric.
15. An integrated circuit memory having a transistor in contact with an interconnect formed within a dielectric layer overlaying the transistor, comprising:
a capacitor located over the dielectric layer and contacting the interconnect, the capacitor comprising:
a first electrode located over the interconnect wherein the first electrode
comprises a layer of titanium and a first barrier layer selected from the group
consisting of tungsten nitride and tungsten silicide nitride and substantially free
of a titanium nitride layer ;
a capacitor dielectric located over the first electrode, the capacitor
dielectric subject to reduction by titanium; and
a second electrode located over the capacitor dielectric.
16. The integrated circuit memory as recited in Claim 15, wherein the capacitor dielectric is tantalum pentoxide.
17. The integrated circuit memory as recited in Claim 15 wherein the first barrier layer has a thickness less than about 60 nm.
18. The integrated circuit memory as recited in Claim 15 wherein the first electrode has a thickness ranging from about 10 nm to about 60 nm.
19. The integrated circuit memory as recited in Claim 15, wherein the first electrode barrier layer is in contact with the capacitor dielectric and located between the first electrode and the capacitor dielectric.
20. The integrated circuit memory as recited in Claim 15, wherein the second electrode comprises a second barrier layer selected from the group consisting of tungsten nitride and tungsten silicide nitride and substantially free of a titanium nitride layer.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US20978898A | 1998-12-11 | 1998-12-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9929376D0 GB9929376D0 (en) | 2000-02-09 |
| GB2344694A true GB2344694A (en) | 2000-06-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9929376A Withdrawn GB2344694A (en) | 1998-12-11 | 1999-12-10 | High dielectric constant capacitors |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2000232208A (en) |
| KR (1) | KR20000048092A (en) |
| GB (1) | GB2344694A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002033461A (en) * | 2000-07-14 | 2002-01-31 | Tokyo Electron Ltd | Semiconductor device and its fabricating method |
| US7960216B2 (en) | 2008-05-10 | 2011-06-14 | Intermolecular, Inc. | Confinement techniques for non-volatile resistive-switching memories |
| US7977152B2 (en) | 2008-05-10 | 2011-07-12 | Intermolecular, Inc. | Non-volatile resistive-switching memories formed using anodization |
| US8008096B2 (en) | 2008-06-05 | 2011-08-30 | Intermolecular, Inc. | ALD processing techniques for forming non-volatile resistive-switching memories |
| US8049305B1 (en) | 2008-10-16 | 2011-11-01 | Intermolecular, Inc. | Stress-engineered resistance-change memory device |
| US8072795B1 (en) | 2009-10-28 | 2011-12-06 | Intermolecular, Inc. | Biploar resistive-switching memory with a single diode per memory cell |
| US8129704B2 (en) | 2008-05-01 | 2012-03-06 | Intermolecular, Inc. | Non-volatile resistive-switching memories |
| US8183553B2 (en) | 2009-04-10 | 2012-05-22 | Intermolecular, Inc. | Resistive switching memory element including doped silicon electrode |
| US8343813B2 (en) | 2009-04-10 | 2013-01-01 | Intermolecular, Inc. | Resistive-switching memory elements having improved switching characteristics |
| US8420478B2 (en) | 2009-03-31 | 2013-04-16 | Intermolecular, Inc. | Controlled localized defect paths for resistive memories |
| US8975613B1 (en) | 2007-05-09 | 2015-03-10 | Intermolecular, Inc. | Resistive-switching memory elements having improved switching characteristics |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8551809B2 (en) * | 2008-05-01 | 2013-10-08 | Intermolecular, Inc. | Reduction of forming voltage in semiconductor devices |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0722190A2 (en) * | 1995-01-12 | 1996-07-17 | International Business Machines Corporation | TaSiN oxygen diffusion barrier in multilayer structures |
| US5633200A (en) * | 1996-05-24 | 1997-05-27 | Micron Technology, Inc. | Process for manufacturing a large grain tungsten nitride film and process for manufacturing a lightly nitrided titanium salicide diffusion barrier with a large grain tungsten nitride cover layer |
| EP0862203A1 (en) * | 1997-01-31 | 1998-09-02 | Texas Instruments Incorporated | Method for fabricating a semiconductor memory capacitor |
-
1999
- 1999-12-10 GB GB9929376A patent/GB2344694A/en not_active Withdrawn
- 1999-12-11 KR KR1019990056907A patent/KR20000048092A/en not_active Application Discontinuation
- 1999-12-13 JP JP11353615A patent/JP2000232208A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0722190A2 (en) * | 1995-01-12 | 1996-07-17 | International Business Machines Corporation | TaSiN oxygen diffusion barrier in multilayer structures |
| US5633200A (en) * | 1996-05-24 | 1997-05-27 | Micron Technology, Inc. | Process for manufacturing a large grain tungsten nitride film and process for manufacturing a lightly nitrided titanium salicide diffusion barrier with a large grain tungsten nitride cover layer |
| EP0862203A1 (en) * | 1997-01-31 | 1998-09-02 | Texas Instruments Incorporated | Method for fabricating a semiconductor memory capacitor |
Non-Patent Citations (1)
| Title |
|---|
| App. Phys. Lett. Vol 74, No 24, 14/6/99, pp 3705-7, "Capacitor strauctures" JP Chiang et al * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002033461A (en) * | 2000-07-14 | 2002-01-31 | Tokyo Electron Ltd | Semiconductor device and its fabricating method |
| US8975613B1 (en) | 2007-05-09 | 2015-03-10 | Intermolecular, Inc. | Resistive-switching memory elements having improved switching characteristics |
| US8129704B2 (en) | 2008-05-01 | 2012-03-06 | Intermolecular, Inc. | Non-volatile resistive-switching memories |
| US7960216B2 (en) | 2008-05-10 | 2011-06-14 | Intermolecular, Inc. | Confinement techniques for non-volatile resistive-switching memories |
| US7977152B2 (en) | 2008-05-10 | 2011-07-12 | Intermolecular, Inc. | Non-volatile resistive-switching memories formed using anodization |
| US8008096B2 (en) | 2008-06-05 | 2011-08-30 | Intermolecular, Inc. | ALD processing techniques for forming non-volatile resistive-switching memories |
| US8049305B1 (en) | 2008-10-16 | 2011-11-01 | Intermolecular, Inc. | Stress-engineered resistance-change memory device |
| US8420478B2 (en) | 2009-03-31 | 2013-04-16 | Intermolecular, Inc. | Controlled localized defect paths for resistive memories |
| US8183553B2 (en) | 2009-04-10 | 2012-05-22 | Intermolecular, Inc. | Resistive switching memory element including doped silicon electrode |
| US8343813B2 (en) | 2009-04-10 | 2013-01-01 | Intermolecular, Inc. | Resistive-switching memory elements having improved switching characteristics |
| US8072795B1 (en) | 2009-10-28 | 2011-12-06 | Intermolecular, Inc. | Biploar resistive-switching memory with a single diode per memory cell |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9929376D0 (en) | 2000-02-09 |
| KR20000048092A (en) | 2000-07-25 |
| JP2000232208A (en) | 2000-08-22 |
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