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GB2340685B - Controllable biasing circuitry - Google Patents

Controllable biasing circuitry

Info

Publication number
GB2340685B
GB2340685B GB9817397A GB9817397A GB2340685B GB 2340685 B GB2340685 B GB 2340685B GB 9817397 A GB9817397 A GB 9817397A GB 9817397 A GB9817397 A GB 9817397A GB 2340685 B GB2340685 B GB 2340685B
Authority
GB
United Kingdom
Prior art keywords
biasing circuitry
controllable biasing
controllable
circuitry
biasing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9817397A
Other versions
GB2340685A (en
GB9817397D0 (en
Inventor
Trevor Monk
Peter William Hughes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
Original Assignee
SGS Thomson Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Ltd filed Critical SGS Thomson Microelectronics Ltd
Priority to GB9817397A priority Critical patent/GB2340685B/en
Publication of GB9817397D0 publication Critical patent/GB9817397D0/en
Publication of GB2340685A publication Critical patent/GB2340685A/en
Application granted granted Critical
Publication of GB2340685B publication Critical patent/GB2340685B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
GB9817397A 1998-08-10 1998-08-10 Controllable biasing circuitry Expired - Fee Related GB2340685B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9817397A GB2340685B (en) 1998-08-10 1998-08-10 Controllable biasing circuitry

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9817397A GB2340685B (en) 1998-08-10 1998-08-10 Controllable biasing circuitry

Publications (3)

Publication Number Publication Date
GB9817397D0 GB9817397D0 (en) 1998-10-07
GB2340685A GB2340685A (en) 2000-02-23
GB2340685B true GB2340685B (en) 2003-08-20

Family

ID=10837012

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9817397A Expired - Fee Related GB2340685B (en) 1998-08-10 1998-08-10 Controllable biasing circuitry

Country Status (1)

Country Link
GB (1) GB2340685B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004002408B4 (en) * 2004-01-16 2006-01-26 Infineon Technologies Ag Receiver circuit with an inverter circuit
DE102005007579A1 (en) * 2005-02-18 2006-08-24 Infineon Technologies Ag Receiver circuit, for relaying data signals e.g. for computer and software applications, uses two inputs for coupling external digital data signal into receiver circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4242604A (en) * 1978-08-10 1980-12-30 National Semiconductor Corporation MOS Input circuit with selectable stabilized trip voltage
US4988897A (en) * 1989-05-27 1991-01-29 Samsung Electronics, Co., Ltd. TTL to CMOS input buffer circuit
EP0661812A1 (en) * 1993-12-31 1995-07-05 STMicroelectronics S.r.l. Interface TTL/CMOS circuit with temperature and supply voltage independent threshold level
US5517131A (en) * 1992-08-11 1996-05-14 Integrated Device Technology, Inc. TTL input buffer with on-chip reference bias regulator and decoupling capacitor
US5742184A (en) * 1996-02-16 1998-04-21 Cyrix Corporation Microprocessor having a compensated input buffer circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4242604A (en) * 1978-08-10 1980-12-30 National Semiconductor Corporation MOS Input circuit with selectable stabilized trip voltage
US4988897A (en) * 1989-05-27 1991-01-29 Samsung Electronics, Co., Ltd. TTL to CMOS input buffer circuit
US5517131A (en) * 1992-08-11 1996-05-14 Integrated Device Technology, Inc. TTL input buffer with on-chip reference bias regulator and decoupling capacitor
EP0661812A1 (en) * 1993-12-31 1995-07-05 STMicroelectronics S.r.l. Interface TTL/CMOS circuit with temperature and supply voltage independent threshold level
US5742184A (en) * 1996-02-16 1998-04-21 Cyrix Corporation Microprocessor having a compensated input buffer circuit

Also Published As

Publication number Publication date
GB2340685A (en) 2000-02-23
GB9817397D0 (en) 1998-10-07

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20070810