GB2233534A - A signal calibration circuit - Google Patents

Abstract

A digital signal calibration circuit for receiving an input digital signal, filtering transient signal pulses, lengthening pulses of a first predetermined duration to a second predetermined duration, and generating a calibrated digital output signal in response thereto. The output signal is then digitally sampled to detect predetermined digital signal bit patterns. The signal calibration circuit can be used in a communication system for detecting digital switchhook flash and dial pulsing signals.

Description

1 - 01 02 03 04 06 07 08 09 10 11 12 13 14 is 16 17 18 19 20 21 22 23 24

25 26 27 28 2,9 30 31 32 33 34 36 37 38 A SIGNAL CALIBRATION CIRCUIT This invention relates to a.signal calibration circuit which has particular, though not exclusive, application for use in a communication system to detect switchhook flash and dial pulse signals.

In a digital communication systemp signals generated by a subscriber set and applied to a two-wire balanced line are received via a peripheral line circuit and are digitized therein. such signals may includer for example, voice signalst switchhookflash signalsp dial pulse signals# and DTMF tones. A switchhook flash signal is generated in response to a momentary depression of the switchhook on a subscriber set, and is used to initiate a special feature such as call forwarding# call transferringr holdr speed dialf etc.

Dial pulse and switchhook flash signals are required to'be detected and distinguished by a peripheral processor of the communication system in order to implement the desired special feature or to connect the subscriber set to an extension corresponding to dialed numbers. The dial signals are typically in the form of a succession of logic high and logic low level pulses of approximately 40 and 60 milliseconds respectively. Switchhook flash signals are typically in the form of momentary logic high level signals having durations of approximately 25 milliseconds.

one prior art method for'detecting dial pulse and switchhook flash signals involves constant scanning of the digital input signal at a high sampling rate (i.e. much greater than 1000 samples per second) by the peripheral processor. The peripheral processor is required to execute many additional tasks, so that high speed sampling of the digital input signal from the line circuit typically consumes excess processor time and is.therefore impractical.

01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 2.1 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Another prior art method utilizes intelligent hardware comprising-an onboard microprocessor disposed on each peripheral card in order to perform the aforementioned high speed digital sampling. Howevert this has been found to be expensive, to occupy a large amount of circuit.b.oard area, and to consume a large amount of power.

In an embodiment to be described circuitry is provided for debouncing the digital signal generated by the line circuitt in order to eliminate transient pulses, and additional circuitry is provided for calibrating the switchhook flash and dial pulse signals to a standard duration. Discrete implementation of these functions can be implemented utilizing analog timing either on the line hybrid or line circuit cardp or with digital filtering on the line circuit card. The calibration circuitry is then followed by circuitry for digital multiplexing of the calibrated signals to the peripheral processor backplane.

A minor disadvantage of the discrete implementation discussed above is the lack of available space on many line circuit cards and hybrids to support the discrete circuit components. In the event that the hybrid or line circuit is modifiedi a compatability problem may develop with some existing systems.

Thus,, according to a preferred embodiment of the present invention. a CMOS uncommitted logic array (ULA) is utilized to implementing the circuitry of the presentinvention. ULA technology can be used to effectively realize any combinatorial or sequential logic circuit in an inexpensive, and easy to define semiconductor chip. The advantages of using a ULA are low cost and low space consumption, compatability with existing line circuits, and reduction of random logic already existing on the line circuits. In a 01 02 03 04 05 06 07 08 09 10 11 12 13 14 is 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 - 3 successful prototype# the digital signal calibration circuitry of the preferred embodiment was realized on a single ULA per line circuit cardi thereby optimizing circuit pin count for implementation of as many peripheral card logic functions as possible.

Functionallyp the circuit of the preferred embodiment is connected in series between digital signal outputs of the line c.ircuit cards# and the peripheral processor backplane. Latches read the switchhook-bit from each of a plurality of time division channels of digital signals received from the line circuit cardsi and forward the information to individual real time processing networks within the ULA. These ULA networks produce two output bits per channel; one indicating detection of a short,witchboQk flash signal, and the other being a debounced and conditionally stretched version of the switchhook signal, ignoring transient logic level signals (ie. "glitches"). The ULA networks stretch short makes and breaks of the switchhook signal to a standard calibrated duration.

As a result of debouncing and stretching of the switchhook signal, the peripheral processor is able to sample at a relatively slow (approximately 1000 samples per second) scan ratep and still reliably detect rapidly changing logic levels (e.g. a 20 pulse per second dialing signal).

In general# in the arrangements to-be described there is provided a signal calibration circuitt comprised of circuitry for receiving a digital input signal comprised of logic higb and logic low level pulsest circuitry for eliminating transient ones of the pulses from the signal, which are of duration less than a first predetermined time period# and circuitry for lengthening the duration of further ones of the pulses from a second predetermined time period which is greater than the first time period to 01 02 03 04 05 06 07 08 09 10 11 12 13 14 is 16 17 18 19 20 2 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 -a third predetermined time period greater than the first and second time periods, whereby the input signal is debounced and calibrated enabling sampling thereof at a low sampling rate.

A better understanding. of the present invention will be obtained with reference to. the detailed description below in conjunction with the following drawings in which:

Figure 1 is a block diagram showing digital signal calibration circuitry according to the present invention, for use in a communication system, in its most general form, Figures 2A-2G are timing wavefoim representations showing the relationship between digital input signals and calibrated output signals for various circumstancesy in accordance with the present invention, Figure 3 is a block schematic diagram showing the circuitry of the present invention disposed in a ULAy Figure 4 is a detailed schematic diagram of ripple counter circuitry for implementing the switchhook debounce and stretching functions according to a preferred embodiment of the present invention.

Figure 5 is a timing waveform representation illustrating signal waveforms that result in the ripple counter circuitry in response to a digital input signal and timing control signalst Figure 6A is a timing waveform representation illustrating the relationshp between timing control signals applied to the ripple counter circuitryp Figure 6B is a timing waveform representation illustrating the relationship between digital input signalsi timing control signals and digital output signals in the signal calibration A 1 01 02 03 04 05 06 07 08 09 10 11 12 13 -14 15 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 33 34 35 36 37 38 portion of the circuit of Figure 4, and.

Figure 7 is a timing waveform representation illustrating the relationship between digital input signals, timing control signals and digital output signals in the calibrated flash portion of the circuit of Figure 4.

With reference to Figure lt a plurality of line circuit cards 1. 3 and 5 are shown for connection to respective pluralities of subscribers' sets via a plurality of bi-directional communication leads, shown generally as 7. For the purposes of explanation. only three line circuit cards are illustrated. However# typically many more are actually utilized in a typical communication system such as a PABX or key telephone system.

Each of the line circuit cards 1, 3. and 5 receives analog voice and control signals from a plurality of telephone sets. and generates a multiplexed serial digital signal in response thereto in a well known manner. For exampleg in many well known digital PABX systems, up to 16 analog subscriber sets may be connected to a single line circuit card. The line circuit cardr such as line circuit card 1, digitizes incoming analog signals received from the sets (e.g."voice signals, dial pulsest DTMF tonest etc.) and multiplexes the digitized signals from the sets onto 32 channel PCM and TDM data links for transmission to digital switching circuitryr such as a dual time and space division cross-point switching matrix (not shown)r in a well known manner. Such a prior art system that performs this function is sold by Mitel Corporation as SX20OV.

Also. the line circuit cards, 1. 3 and 5 detect momentary grounding of the ring lead (i.e. one of the leads in each of bidirectional balanced tip and ring lead pairs 7), and momentary high impedance conditions between the tip and ring leads of the 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Z1 22 23 24 25 26 27 28 '29 30 31 32 33 34 35 36 37 38 bidirectional balanced lead pair. A serial data output 8 from each of the line circuit cards 1, 3 and. 5 carries digital control information relating to respective ones of the subscriber sets connected thereto.

In particular. typically 32 channels of 8 bit digital signals are transmitted from the data output of the line circuit cards 1, 3 and 5 in serial fashion, for reception by the peripheral processor 9. Each of the 8 bit signals is comprised of four least significant bits (designated as "GB") each of which indicates the status of European ground button (EGB) voltage associated with respective ones of the sets. and four most significant bits (designated as "SHK"), each of which indicates the status of the switchhook impedance associated with the respective subscriber sets. More particularly. logic low level of the SU signal indicates an on-hook impedance between tip and ring leads of the balanced lead pair 7r and logic high level of the SHK signal indicates an off-hook impedance between the tip and ring leads. Similarlyg a logic high level of each of the least significant GB bits indicates that the ring lead of the bidirectional balanced lead pair has been connected to ground at the subscriber set, while a logic low level of the GB bits indicates that the ring lead is connected to a source of battery voltage (eg. typically -48 volts).

The serial data output signals from the line circuit cards 1. 3 and 5 are transmitted for reception by signal calibration circuits llr 13 and 15. respectivelyj whichi in the preferred embodiment of the present invention, are disposed in respective uncommitted logic arrays (ULAS). Each of the signal calibration circuits 11, 13 and 15 receive the serial digital signals output on line 8 from the line circuit cards 1, 3 and 5, as well as timing signals generated by peripheral controller 9 o.n C244f FP and RST 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 inputs. In response to receiving the serial digital signals and timing signalst circuits 11, 13 and 15 digitally filter transient logic level pulses of the.SHK and GB signalsi and generate further serial digital output signals including a debounced and stretched switchliook signal denoted SHUF and a calibrated flash signal. denoted as CF.

The serial digital output signal from each of the calibration circuits 11, 13 and 15 is preferably comprised of 32 channels of informationt each channel being in the form of an eight bit byte, the most significant location in the byte being occupied by the SM bite the next most significant location being occupied by the CF bite the next two most significant locations being occupied by redundant versions of the SU bit. and each of the last four locations being occupied by redundant versions of the GB bit.

A series of latches internal to the signal calibration circuits 11, 13 and 15 read the SU bit from channels 0-15 output from circuits l# 3 and 5 and forward the SHK bits to individual real time processing networks within the signal calibration circuitst as discussed in greater detail below with reference to figures 3 and 4. The individual real time processing networks produce the aforementioned "calibrated flash" bit (CF) and the debounced and conditionally stretched version of the SHK bit, (i.e. SM). The real-time processing networks ignore 6-9 millisecond transient pulses of SU and also digitally stretch the short make and break intervals of the SHK signal to produce the calibrated SUD output. By filtering transient logic level puls es and stretching or elongating the SHK bit. the SHKD bit is calibrated in order that peripheral controller 9 may sample the serial output signals from the calibration circuits 111 13 and 15 at a relatively low sampling rater 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 2 3 24 25 31 32 33 34 35 36 37 38 39 40 8 thereby reducing the processor's real time work load.

The data output streams from individual ones of the circuits 11. 13 and 15 are selectively multiplexed with the unprocessed serial digital input signals received from the line circuit cards in response to predetermined control signals being applied to the select inputs SO and S1 by line circuit cards 1, 3 and 5, respectively.

In particular, groups of channels of the unprocessed serial digital input signals are modified in accordance with the SO and S1 bit values as shown in Table 1.

TABLE 1 so 0 1 0 1 1 S1 0 0 1 1 CHANNELS MODIFIED None CH 0-7 CH 0-3r CH 8-11 CH 0-15 For channels 16-30,, 'the internal multiplexer of the calibration circuits passes the data output stream through transparently to the backplane for reception by the peripheral controller 9. Channel 31 is assigned as an 8 bit parallel input port which allows for serialization of an 8 bit identification PROM data signal which does not form part of the present invention.

In operationf the circuits 11, 13 and 15 receive the serial digital input signals from the line cards in the following format, in which DO-D7 represent the bits of each byte constituting a channel:

D 7 SHK D 6 D 5 D 4 D 3 D 2 D 1. D 0 SHK SHK SHK GB' GB GB GB The SHK bits are extracted and processed to generate the aforementioned SHKD and CF bits. In particular, with reference to Figures 2A-2G (which 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Z1 22 23 24 26 27 28 29 30 31 32 33 34 35 36 37 38 - 9 will be described in more detail later), the SUD bit forms a delayedi debounced and stretched version of the SHK bit. The SM bit goes to a logic high level in the event the SHK bit maintains a logic high level for at least 6-9 milliseconds (see Figure 2A). Therefore, in the event of a transient logic high level pulse of the SHK bit having duration of less than 6 milliseconds. the SHKD bit remains at a logic low level. In the event the SHK bit is at a logic high level for greater than 9 milliseconds and less than 16.5 milliseconds then the SM goes to a logic high level for between 13.5 and 16.5 milliseconds.

The SM bit goes to a logic low level 6-9 milliseconds after the SHK bit has gone to a logic low level (see Melay" in Figures 2A-2G). Thereforep in the event of a transient logic low level pulse of the SU bit having a duration less than 6 milliseconds. the SHKD bit maintains a logic high level. In the event the SHK bit goes to a logic low level for greater than 9 milliseconds and less than 16.5 milliseconds then the SM bit drops to a logic low level for 13.5 - 16.5 milliseconds.

By the circuit stretching and debouncing the SHK switchhook signal, the typically busy peripheral controller 9 is able to scan the-switchhook signal at a relatively low (eg. 10 milliseconds) scan rate. allowing it to serve other functions with greater efficiencyo yet it can capture rapidly changing data (e.g. 20 pulse per second dial pulses received from the subscriber sets) The calibrated flash (CF) bit goes to a logic high level for 168 milliseconds in the event the SU bit remains at a logic low level for greater than 18 milliseconds. This allows the peripheral controller 9 to scan for short switchhook flashes at a slow scan rate (e.g. 100 milliseconds), therefore optimizing the real time task performing capability of 01 02 03 04 05 06 D 7 08 09 10 11 12 13 14 is 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 33 34 35 36 37 38 39 - 10 the typically busy peripheral controller 9.

During assertion of the CF bity the CP time out (i.e. 168 milliseconds) is restarted by any validated SHK breaksi (i.e. dial pulses).

The serial digital signal output from circuits 11, 13 and 15 is provided to the backplane for sampling by the peripheral conttoller 9j'in the following format:

D7 D6 D5 D4 D3 D2 D1 DO SM CF SHK SHK GB GB GB GB Considering Figures 2A-2G in greater detail, the signal waveforms are illustrated for the SM bit and the CF bit in response to various waveforms of the SHK bit.

With reference to Figure 2A representing the offhook instruction of a cally the SU bit is shown changing from a logic low level to a logic high level. (i.e. the subscriber set has gone off-hook). The SHKD bit changes from a logic low to a logic high level after an approximately 6-9 milliseconds delay. The CF bit remains at a logic low level.

Turning to Figure 2B. the SU bit waveform illustrates thepresence of dial pulses. In responses the SM bit reproduces the SU bit waveform delayed by 6-9 milliseconds. During the break portion of the SU bit waveform. the SU bit assumes a logic low level for greater than at least 18-24 milliseconds, resulting in the CF bit changing from a logic low to a logic-high level approximately 26-32 milliseconds after the SHK bit changes from a logic high level to a logic low level. The CF bit maintains the logic high level for a period extending to approximately 200 milliseconds after the final transition of the SM bit from a logic high level to a logic low level.

Turning to Figure 2Cj the SM waveform is shown representing dial pulses with short 10 ms breaksi rather than 60 ms as in the example of Figure 1 01 02 03 04 05 06 07 08 09 10 11 12 13 14 is 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 311 32 33 34 35 36 37 38 - 1 1 - 2B. The SM bit constitutes a waveform in which the break (logic low) portion is stretched from 10 milliseconds to approximately 13.5-16.5 milliseconds. The SHKD bit then changes to a logic high level for the remainder of the duration of 'the logic high level make portion of the UK bit plus the aforementioned delay of 6-9 milliseconds (>33 ms). Since the logic low level or break portion of the SHK bit is maintained for less than 18 millisecondsi the CF bit stays at a logic low level.

With reference to Figure 2Di the SHK bit waveform is shown representing dialling digits having short 10 ms make intervals. The SM bit waveform is delayed by 6-9 milliseconds from the SHK bit waveformr and the short make interval is stretched from 10 milliseconds to approximately 13.5-16.5 milliseconds. Since the break porl-ion of the SU bit exceeds 18 milliseconds in durationp the CF bit changes from a logic low level to a logic high level approximately 26-32 milliseconds after the SHK bit switches from a logic high level to a logic low level,, and is maintained at a logic high level for approximately 200 milliseconds after the last transition of the SHK signal from the logic high to the logic low level.

Considering Pigure 2Ei a talk state flash condition i's indicated wherein the SHK switchhook bit waveform goes from a logic high level to a logic low level signal for a duration of 25 milliseconds and then reverts to the logic high level. In responser the RHKD. bit wAvnfnt-m follnt.?.e; thp SPK bit waveform with a delay of 6-9 milliseconds# as discussed above. Alsorthe CF bit goes to a logic high level signal for 168 milliseconds, after an initial delay of 26-j2 milliseconds.

- Turning to Figure 2Fi transient low and high logic level pulses 10A and 10B respectively of the SU bit waveform are illustratedr indicating 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 33 34 35 36 37 38 "glitches". These glitches are ignored and the SUD bit goes to a logic low level for 13.5-16.5 milliseconds approximately 6-9 milliseconds after the SHK bit has changed from a logic high to a logic low level. The CF bit is maintained at a logic low level.

With reference to Figure 2Gr the SHK bit waveform indicates the condition when a subscriber set releases the line and goes on-hook. The SUD bit goes from a logic high to a logic low level 6-9 milliseconds after the SHK bitt and the CF bit goes from a logic low to a logic high level for 168 milliseconds, 26-32 milliseconds after the SHK bit goes from a logic high to a logic low level.

In Figure 3 a block schematic diagram is shown illustrating the principle components of each of the calibration circuits llr 13 and 15. In particular, a timing circuit 30 is shown for receiving 244 nanosecond clockp and 125 microsecond frame pulse timing and control signals from the backplane, on C244 and FP respectively. In addition, timing circuit 30 receives reset signal RST generated at the line circuit card. The timing circuit 30 generates a plurality of timing signals and applies them onto a clock bus 32 for application to the clock inputs CLKIN of a multiplex controller 34 and a serial-to-parallel converter 36, as well as to the timing input of a signal processing circuit 38.

Multiplex controller 34 receives control bits SO and S1 from the line card. In response, the multiplex controller generates a multiplex clock signal for application to the multiplex control input MUX CLKIN of an output multiplexer 40. The multiplex controller 34 supervises UM channel modification in accordance with the select control signals SO and S1 received from its respective line card, as discussed above with reference to Figure 1 and Table 1; The serial-to-parallel converter 36 01 02 03 04 05 06 07 08 09 10 11 12 13 14 is 16 17 18 19 20 21 22 1 23 24 25 26 27 28 29 30 '31 32 33 34 35 36 37 38 - 13 receives the serial digital input signal from corresponding ones of the line circuit cards l# 3 or 5, on a serial input IN. The serial digital input signal is passed transparently to a serial output SOUT thereof for application to a serial input SIN of the output multiplexer 40.. The input signal is also converted to parallel form and is transmitted via a 16 bit parallel bus from a SHK output of the serial-to- parallel converter 36 to the SIGNAL INPUT of signal processing circuit 38.

Signal processing circuit 38 is comprised of sixteen individual circuits for receiving respective channels of the parallel SHK input signals and for generating the corresponding CF and SM signals in response to receiving the clock signal output from timing circuit 30. The respective circuits comprising the processing circuit 38, are described in greater detail below with reference to Figure 4.

As discussed above with reference to Figure 3, output multiplexer 40 modifies predetermined ones of the input channels received from serial-toparallel converter 36 under control of multiplex controller 34y whereby the CF and SM bits are selectively inserted into the outgoing serial output stream.

The sixteen W and SM outputs of signal processing unit 38 are applied to parallel W IN and SM IN inputs of the output multiplexer 40.

The serial digital output signal from multiplexer 40 is applied to the PABX backplane as discussed above with reference to Figure 1.

Turning now to Figure 4, a schematic diagram is shown illustrating the components comprising a representative first one of the sixteen ULA calibration circuits comprising signal processing unit 38. for processing the SHK bit on the first M t 01 02 03 04 05 06 07 08 12 13 14 19 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 33 34 36 37 38 39 40 channel (i.e. channel 0). The remaining fifteen ULA circuits of signal processing unit 38, corresponding to channels 1-15f are of identical construction to that shown in Figure 4.

The switchhook bit SHKO from the first TDM channel of the serial digital input signal is received from the serial/parallel converter 36 on the data input D of a flip-flop 100 having enable inputs EN and connected to a source of timing signal T3P2 carried by the clock bus 32(Figure 3).

The Q output of flip-flop 100 is connected to the data input D of a second flip-flop 102 which in turn has a Q output connected to the data input D of a third flip-flop 104. The enable inputs EN and 'EN of the flip-flops 102 and 104 are connected to additional sources of timing signal. designated T3P1 and T3P0 respectively. The T3P2, T3P1 and T3P0 signals are three phases of a 3 millisecond sampling list clock for clocking in the SHKO signal into the flip-flops 100r 102 and 104. Thus. at a given instant in timer the signal appearing on the Q outputs of the flip-flops. constitute a 9 milliseconds "snapshot" of three successive SHKO bits.

With reference to Figure SF signal. waveforms Q100y Q102 and Q104 are illustrated for the Q outputs of corresponding flip-flops 100, 102 and 104 in response to the clocking in of a logic high SHM signal by the T3P2. T3P1 and T3P0 signals of the sampling list clock. With reference to sampling time A in Figure 5p since the Q outputs of the flip-flops are all hight then the SHKO signal must have been high during the previous three samplesi i.e. the SHKO signal was high for at least 6 milliseconds.

Logic circuitry comprising NAND gates 106 and 1080 NOR gates 110t 112r 118 and 120p and flip-flops 114 and'116r performs a state code monitor function for determining when three successive SHKO 01 - 15 - 02 bits are identical and in response clock out a 03 corresponding debounced and stretched switchhook bit 04 DSM. In the event at least one of the logic level signals appearing on one of the Q outputs of the 06 flip-flops 100-104 is different from the othersi the 07 debounced output DSM bit does not change.

08 A signal STRTCH is received from an 09 additional flip-flop 126 forming part of a shift register comprised of flip-flops 124-132. The 11 flip-flops 124-132 perform timing signal generation 12 for stretching SHKO bits having duration greater than 13 9 milliseconds but less than 16.5 milliseconds.

14 A better understanding of the operation of the state code monitor circuit will be obtained with 16 reference to Table 2, below:

17 TABLE 2

18 19 LOGIC LEVEL SIGNAL OUTPUTS 21 FLIP-FLOPS NAND NOR NOR NAND NOR NOR 22 100 102 104 106 110 112 108 118 120 23 24 0 0 0 1 1 0 0 0 1 0 0 1 1 1 0 1 1 0 26 0 1 0 1 0 0 1 1 0 27 0 1 1 1 0 0 1 1 0 28 1 0 0 1 0 0 1 1 0 29 1 0 1 1 0 0 1 1 0 1 1 0 0 0 0 1 1 0 31 1 1 1 0 0 1 1 0 1 32 33 when STRTCH 0 34 36 37 38 39 41 42 43 A signal SDPOR is carried by the clock bus 32 connected to timing circuit 30, and is in the form of a logic high level for 1.2 milliseconds fni, 'n(7 ----nw, power up. Once the 12 milliseconds time period has elapsed the SDPOR signal goes to a logic level low thus enabling the debouncing and calibrated flash functions of processing circuit 38 (Figure 3). In particular. the SDPOR signal is applied to a first input of a NOR gate 134 having a second input connected to the Q output of flip-flop 132. An output 01 02 03 04 8R 07 08 09 10 11 12 13 14 16 19 19 20 21 22 3 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 16 of NOR gate 134 is connected to a first input of AND gate 136 having an output connected to a first input of a further NAND gate 138. The output of NAND gate 138 is connected to the second input of NAND gate 136 as well as to the reset inputs 1 of flip-flops 126132. A second input of NAND gate 138 is connected to a further timing control signal output CC16BX from the clock bus 32 (Figure 3), which signal is inverted via an inverter 140. The inverted CC16BX signal is also applied to the enable input EN offlip-flops 114 and 116 discussed above.

A further timing control signal CC16X is received from the clock bus 32 and inverted via an additional inverter 142 and applied to the clock input C of flip-flop 124 and the complimentary enable input of the flip- flops 114 and 116.

The output from NOR gate 118 is connected to the data input D of the first flip-flop 124 of the bit stretching shift register. Enable inputs EN of flip-flops 128-132 are connected to three phases of a further timing control signals T6P2l T6P1 and T6P0 respectively. Each of the I'T611 signals form a different phase of a 6 millisecond list clock signal.

In Figure 6A signal waveforms are illustrated for timing control signals TW2j TGP1 and TGPO in relation to timing control signals T3P2, T3P1 and T3PO, and further in relation to timing control signals CC16X and CC16M Thust in operation, the logic level output signal from NOR gate 118 is clocked through flip-flop 124 such that in the event of a transition in the logic level output of NOR gate 118. a logic high level signal is clocked into the D input of flip-flop 126 and further clocked through flip-flops 128-132 for application to the second input of NOR gate 134.

A better understanding of the operation of the signal calibration portion of the circuit will be 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 2.1 22 23 24 25 26 27 28 29 30 ?' i 32 33 34 35 36 37 38 - 17 obtained with reference to Figure 6B in which timing and control signal waveforms are illustrated for the case of a SHKO signal that maintains a logic high level for at least 6-9 milliseconds. Signals T3-0, X,2 represent samplings of timing control signals T3P0.' T3P1 and T3P2 respectively, and signals TG-0pl12p represent samplings of timing control signals TGPO, TGPI, and TGP2 respectively. The sampling arrows are shown for illustrative purposes and represent the signals at the Q outputs of flip-flops 100r 102 and 104.

As stated previously the T3PO, T3P1 and T3P2 timing control signals clock in the SM signal into flip-flops 100p 102 and 104p and at a given instant in time, the signal appearing on the Q outputs of the flip-flops constitute a 9 milliseconds snapshot of three successive SHEO bits.

With further reference to Table 2, the output of NOR gate 118 assumes a logic high level when the Q outputs of flip-flops 100, 102 and 104 are of different logic levelsi and assumes a logic low value when the Q outputs are all of the same logic level.

Thus. the output of NOR gate 118 assumes a logic low value when the SHKO signal maintains a logic high level for at least 6-9 milliseconds.

The transition of the output of NOR gate 118 from a logic high to a logic low level is transferred to the output Qof flip-flop 124 during a logic high to logic low transition of timing control signal C171.6X (not shown) moreover# just prior to the output Q of flip..flop 124 going low and during the time period during which CC16X is hight the output of NOR gate 118 and the output Q of flip-flop 126 (STRTCM) are both low. thus the output of NOR gate 120 assumes a logic high level, enabling the Q output of flip-flop 104 to be sampled and sent to the' Q Output df flip-flop 122 9 01 02 03 04 89 99 11 12 13 14 16 (DSHKO). Thus, the signal DSHKO transforms from a logic low level to a logic high level.

When the Q output of flip-flop 124 _(STRTCH) transforms from a logic low to a logic high level# the Q output of flip-flop 126 MSHM) is set to a logic low level by an li input of flip-flop 126 assuming a logic low level. The reset input "5 of flip-flops 126-132 is derived from NOR gate 134p NAND gate 126. NAND gate 138 and by logic inputs SDPORt the 0 output of flip-flop 132 and timing control signal CC16BX (not shown).

operation of the logic circuitry controlling resetting of flip-flops 1261321 will be 17 better understood with reference to the following 18 table:

19 TABLE 3

31 LOGIC LEVEL SIGNAL OUTPUTS 23 24 SDPOR FLIP-FLOP =GBX NOR NAND NAND 132 134 136 133 26 0 0 0 1 0 1 27 0 0 1 1 0 1 28 0 1 0 0 1 0 29 0 1 1 0 1 1 1 0 0 0 1 0 31 1 0 1 0 1 1 32 1 1 0 0 1 0 33 1 1 1 0 1 1 34 36 37 a 38 39 41 42 43 44 1 As stated previously the SDPUR signal is at a logic high level for only a 12 millisecond time period following power up. Thus in steady-state when a STRTCM signal (Q output of flip-flop 126) propagates through to the Q output of flip-flop 132r the output of NAND gate 138 (reset for flip- flops 126-132) will assume a logic low level as soon as timing control signal CC16X assumes a logic low level.

Thus, in operation from the time that DSHKO transforms from a logic low to high level to the time that the reset occurs, two 6 millisecond samples and one-half of the 3 millisecond clock periods 4 01 02 03 04 05 89 14 15 16 19 19 39 33 24 25 26 27 2.8 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 - 19 elapse, effectively making DSHKO at least 13.5 millisecond in duration.

Considering the calibrated flash portion of the circuiti a plurality of flip-flops 144-156 are linked together in the form of a ripple counter. In particular. the Q and outputs of flip-flops 144-152 are connected to the and C inputs respectively of flip-flops 146-154. The 'd output of flip-flop 154 is connected to the reset input of the last flip-flop 156. as well as to a first input of NAND gate 158. A second input of NAND gate 158 receives a timing signal T6MX at a period of 6 milliseconds, and the output of NAND gate 158 is connected to the C input of flip-flop 144, and inverted via inverter 160 and applied to the input of flip-flop 144.

Accordingly, the outputs Of flip-flops 144r 146y 148r 150r 152 and 154 comprise respective outputs of the ripple countert carrying clock signals denoted as EDGE 6, EDGE 12r EDGE 24,, EDGE 48# EDGE 96 and EDGE 192 respectively.

The Q output of flip-flop 148 is connected to the enable input EN of flipflop 156. The data input D of flip-flop 156 is connected a logic high voltage level and the set input S is connected to ground. The Q output of flip-flop 156 carries the calibrated flash signal W for the first M channelf. designated as CFO.

The CFO signal is applied to a first input of a NAND gate 162, the second input thereof being connected to the output of NOR gate 118 via an inverter 164. An output of NAND gate 162 is connected to a first input of a further NAND gate 166 having a second input thereof connected to the Q output of flip-flop 122 for receiving the DSM signal. An output of NAND gate 166 is inverted via inverter 168 and applied to a first input of a NOR gate 170. The 01 02 second input of NOR gate 170 is connected to the clock bus 32 (Figure 3) for receiving the aforementioned 03 89 06 SDPOR signal. The output of NOR gate 170 is connected to the reset input - 9 of each of the flip-flops 144-154.

1 07 08 In operation. the flip-flops 144-154 are reset in response to the output of NOR gate 170 going 09 to a logic low level.

11 12 Operation of the logic circuitry controlling resetting of the ripple counter# will be better understood with reference to the following 13 14 table:

is 16 17 18 19 20 21 22 23 24 25 216 27 28 29 30 31 32 33 34 35 36 37 38 TABLE 4

LOGIC LEVEL SIGNAL OUTPUTS SDPOR DSMKO NOR 118 NAND NAND 162 166 NOT NOR 168 170 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 1 1 39 Accordingly, it is seen that the ripple counter is in a state of resett and does not count 41 whenever the SDPOR signal is at a logic high level (i.e. for the first 12 milliseconds after power up), 42 43 as well as whenever the DSHKO signal is at a logic high level and the outputs of NOR gate 118 and CFO are not at logic low and logic high levels respectively.

A better understanding of the operation of the calibrated flash portion of the circuit will be 1 44 46 47 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 -21 22 23 24 25 9 28 29 30 31 13 34 35 36 37 38 1 obtained with reference to Figure 6B with consideration of the case of the signal DSHKO on a transition from a high logic level to a low logic level and the signals SDPOR and CFO at a logic low level.

As stated previously. when DSHKO is at a logic high level and NOR gate 118 and the Q output of flip-flop 156. (output CFO) are not at logic low and high levels respectively. the ripple counte is in a state of reset until the signal DUKO assumes a logic low level i.e. the output of NOR gate 170 is at a logic high level.

Once the signal DSHKO makes a transit-ion from a logic high level to a logic low level i.e. the output of NOR gate 170 is at a logic low level, the clocking signal TGU will start a ripple count through flip-flops 144154.

Turning to Figure 7f signal waveforms are illustrated for the Q outputs of flip-flops 144-154 and 156 (output CFO) which comprise respective outputs of the ripple counter. Q144-Q156 represent the Q outputs of flip- flops 144-156 respectively and illustrate signal waveforms that result in response to the clocking signal TGMX starting a ripple count through flipflops 144-154.

As stated previously# the " outputs of flip-flops 144, 146r 148f 150, 152 and 154 comprise respective outputs of the ripple countert carrying clock signals denoted as EDGE 61 EDGE 121 EDGE 24p EDGE 43t EDGE 96 and EMr 192 respectively (Fig-re 4).

The d outputs of flip-flops 144 (EDGE 6)t 148 (EDGE 12)r 150 (EDGE 24)r 150 (EDGE 48)y 152 (EDGE 96) and 154 (EDGE 192) change from a high logic level to a low logic level 6, 12r 24r 48, 96 and 192 milliseconds respectively after the ripple count has 01 - 22 - 83 started.

04 The '5 Output of flip-flop 150 (EDGE 24) is applied to the EN input of flip-flop 156 and it is 06 seen that EDGE 24 is set to a logic low level then the 07 Q output of flip-flop 156 (CFO) will be set to a logic 08 high level. This is dependent on the condition that 09 the signal DSHKO remains at a logic low level after the transition from a logic high level to a logic low 11 level for a time period greater than 18 milliseconds, 12 i.e. 4 counts of the 6 millisecond sample clock TGU.

13 If however, the signal DSHKO remains at a logic low 14 level for a period less than 18 millisecondst the Q 19 output of flip-flop 150 (EDGE 24) will remain at a 17 logic high level and the U.output of flip-flop 150 18 (EDGE 24) will remain at a logic high level and the Q 19 output of flip-flop 156 (output CFO) will remain at a logic low level.

The;5 output of flip-flop 154 (EDGE 142) 24 is applied to the R input of flip-flop 156 and it is seen that if EDGE 142 is set to a low logic level then 26 the Q output of flip-flop 156 (CFO) will be set to a 27 logic low level.

28 The total time of which the Q output of 29 flip-flop 156 (CFO) is at a logic high level is the time interval between EDGE 142 and EDGE 24, i.e.

31 192-24 milliseocnds = 168 milliseconds.

32 Thust according to the circuit of Figure 33 4r the DSHKO signal provides a stretched and debounced 34 version of the SHKO signal applied thereto. and the CF0 signal provides a calibrated flash signal which is 36 valid for 200 milliseconds after a valid hookswitch 37 flash.

38 As discussed previouslyr the DSHK and W 39 signals output from respective ones of the signal calibration circuits are applied to the output 41 multiplexer 40 (Figure 3) via respective 16 bit 42 parallel busses. The serial.output from the 1 4 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 33 34 35 36 37 38 - 23 muliplexer 40 is applied to the backplane (Figure 1) for sampling via the peripheral controller 9.

In summary, in the embodiments that have been described there is provided a signal calibration circuit for receiving the switchhook bits SU from respective line circuit cards and in response generating a calibrated switchhook signal DSHK and a calibrated flash signal CF which are then sampled by a peripheral controller. By debouncing and stretching the SHK and W signals# the peripheral controller is able to sample the signals at a relatively,low sampling rate. thereby freeing up additional processor time for other functions. However# it will be understood from the arrangements described that relatively short switchhook flashes# as well as dial pulsing can be accurately detected.

The circuitry that has been described can: be advantageously disposed on an uncommitted logic array (ULA) and disposed between respective ones of the line circuit cards and the peripheral controller backplane in a communication systemr such as a PAM. By implementing the present invention on a ULA# circuit board area is optimized, and additional circuitry such as timing generation# etc.r may be incorporated within ULA to further decrease circuit board real- estate. of course# the circuitry can also be implemented using discrete components# with the resultant sacrifices in circuit board area.

A person understanding the present invention may conceive of other embodiments or' variations therein.

For exampler the principles of the present invention may be applied to any system requiring digital sampling of pulses having predetermined durations. It is contemplated that a multiplicity of applications outside of the telecommunications field are possible. The circuit Of the present invention

01 02 03 04 05 06 07 08 09 10 11 12 13 14 - 24 can be inserted in any digital serial data stream for debouncing or filtering short data pulses and extending or stretching valid data pulses to a.predetermined duration for sampling via a computer or other digital sampling circuitry at a slow sampling rate.

The invention has been.described, by way of example, with reference to particular tmbodiments,-but it will be understood that variations, modifications and other embodiments of the invention may be made within the scope of the invention as defined by the appended claims,. given a purposive construction.

Claims (10)

1. For use ina communication system including one or more signal ports for generating serial data signals comprised of logic high and logic low level pulsest and a peripheral processor connected to said signal ports for sampling said data signalst a signal calibration circuit comprised of first means for receiving said logic high and logic low level pulses. and in response eliminating transient ones of said pulses having durations less than a first predetermined time period, and second means for detecting further ones of said pulses having durations greater than said first time period and less than a second predetermined time period and in response lengthening each of said further pulses to a duration equal to said second predetermined time period, whereby said peripheral processor is able to sample said serial data signals at a sampling rate of at least one sample per said first predetermined time period.

2. A signal calibration circuit as defined in claim 1, including additional means for detecting logic low level pulses having duration greater than a third predetermined time period greater than said second time period, and in response generating a calibrated logic high level signal having duration equal to a fourth predetermined time period greater than said third time period for sampling by said peripheral processor at a further sampling rate of at least one sample per said fourth predetermined time period and less than one sample per said third predetermined time period.

A 1

3. A signal calibration circuit as defined in claim 2, wherein said firsty second, third and fourth predetermined time periods are approximately 6 msec. 13.5 msec. 18 msec and 168 msect respectively.

4. A signal calibration circuit as defined in claim 1. 2 or 3 further comprised of:

(a) a 3-stage shift register for receiving and clocking said logic high and logic low level pulses at a rate equal to said first predetermined time periodr (b) an output latch for receiving and latching said pulses clocked via said shift register# (c) logic circuitry connected to said shift register and output latchr for detecting successive opposite polarity ones of said pulses and in response disabling said output latch. thereby eliminating transient pulses, and (d) timing circuitry connected to said shift register and output latch for controlling said clocking of said logic high and logic low level pulses and said latching of said pulses clocked via said shift register. for lengthening said further pulses to said duration equal to said second predetermined time period.

5. A signal calibration circuit as defined in claim 2r wherein said additional means is comprised of a ripple counter for generating a plurality of digital count signals. a predetermined one of said count signals for changing logic levels once per said fourth predetermined time periodp and logic circuitry connected to reset inputs of said counter for detecting said logic low level pulses having duration greater than said third predetermined time period,-and in response generating a reset signal for resetting said counter.

a -1 27 -

6. A signal calibration circuit as defined in claim 2 or 3 wherein said first, second and additional means are disposed on a signal chip ULA.

q

7. In a communication system including one or more signal ports for generating serial data signals comprised of logic high and logic low level pulses. a method for calibrating said data signals for sampling at a predetermined sampling rate,- comprising the steps of:

(a) receiving said logic high and logic low level pulsest (b) eliminating transient ones of said pulses of duration less than a first predetermined time period, (c) detecting further ones of said pulses of duration greater than said first time period and less than a second predetermined time period. and (d) lengthening each of said further pulses to a duration equal to said second predetermined time period. whereby said lengthened pulses can be sampled at said sampling rate, said sampling rate being at least one sample per said second predetermined time period and less than one sample per said first predetermined time period..

8. A signal calibration circuit, comprised of:

(a) means for receiving a digital input signal comprised of logic high and logic low level pulses j (b) means for eliminating transient ones of said pulses from said signal, said transient pulses being of duration less than a first predetermined time periodi and (c) means for lengthening the duration of further ones of said pulses from a second 1 predetermined time period greater than said first time period to a third predetermined time period greater than said first and second time periods, whereby said input signal is debounced and calibrated enabling sampling thereof at a low sampling rate.

9. A signal calibration circuit as defined in claim 8, wherein said means for eliminating transient ones of said pulses is comprised of a shift register having a plurality of stages for recei,ing successive pulses of said signaly logic circuitry for detecting the polarity of said successive pulses received by individual ones of said stages and generating a control signal in response to detection of three successive pulses of alternating polarityr and a latch circuit for receiving said input signal from said shift register and said control signal from said logic circuitry. for transmitting said digital input signal unmodified in the absence of receipt of said control signal and reversing the polarity of the second of said three successive pulses in response to receiving said control signal.

10. A signal calibration circuit as claimed in claim 1 including arrangements substantially as described herein with reference to Fig. 1 and Figs. 2A-2G, Fig. 3, or Fig. 4 and any one of Figs. 5, 6A, 6B or 7 of the accompanying drawings.

A Pubhshed 1991 at The Patent Office, State House. 66171 High Holborn. LondonWC I R 4TP. Further copies may be obtained from The Patent Office Sales Branch. St Mary Cray. Orpington. Kent BR5 3RD. Printed by Multiplex techniques lid, St Mary Cray. Kent, Con 1187 1 i