GB2224184A - Digital data demodulation - Google Patents

Abstract

A digital data demodulating method and means in which a band limited digital signal is filtered in a filter (72) having a bandwidth less than half the symbol rate of the signal. The signal is sampled at less than the symbol rate and applied to an equaliser (76) operating at the sample rate. The equalised signal is applied to a rate increasing stage (78) (which may comprise an interpolator to increase the signal rate to the symbol rate after which it is applied to a symbol detector (80). The equaliser (76) may comprise a linear equaliser or a decision feedback equaliser, the tap weights of which are calculated recursively. When the input signal has been modulated in accordance with a band limited scheme such as Tamed Frequency Modulation, the sampling rate is half the data rate and the bandwidth of the pass filter is a quarter of the data rate. Parallel equalisers may handle even, respectively odd, samples, (Fig. 6). <IMAGE>

Description

DESCRIPTION DIGITAL DATA DEMODULATION The present invention relates to digital data demodulation for use with band limited digital signals and to a demodulator including at least one equaliser for facilitating the making of decisions about digital signals which have been distorted by intersymbol interference.

Normally, adaptive equalisers such as linear equalisers (LE) and decision feedback equalisers (DFE) sample a digital signal at, or above, the symbol rate. Additionally if the channel impulse response characteristic of the transmission channel is changing then the equaliser coefficients or tap weights are updated as required. The number of taps which the digital filters in an equaliser possesses determines the processing requirements. The larger the number (N) of taps, the greater the amount of processing which in many implementations requires a greater power consumption.

An object of the present invention is to reduce the processing requirements of adaptive equalisers.

According to a first aspect of the present invention there is provided a method of demodulating a band limited digital signal, comprising equalising the signal by sampling the signal at less than the symbol rate.

The first aspect of the present invention further provides a method of demodulating a band limited digital signal, comprising equalising the signal by sampling the signal at less than the symbol rate, rate increasing the equalised samples to the symbol rate and applying the rate increased signals to a decision stage.

If desired the band limited digital signal may be frequency down-converted prior to being equalised.

According to a second aspect of the present invention there is provided a digital data demodulator comprising an input for a band limited digital signal, equalising means coupled to the input and means for clocking the equalising means at a sampling rate which is less than the symbol rate of the data signal.

The second aspect of the present invention further provides a digital data demodulator comprising an input for a band limited digital signal, equalising means coupled to the input, means for clocking the equalising means at a sampling rate which is less than the symbol rate of the data signal, means coupled to the equalising means for rate increasing the equalised samples to the symbol rate and a decision stage coupled to the rate increasing means for determining the data from the rate increased equalised samples.

The present invention is based on the realisation that according to the Nyquist sampling theorem when bandwidth efficient modulation, such as tamed frequency modulation, is used, an equaliser can be run at less than the symbol rate and still be capable of carrying all the information necessary for demodulation. By operating at less than the symbol rate, the number of taps required by the equaliser is reduced and the amount of processing is consequently also reduced leading to a concomitant decrease in power consumption. However in order to recover the data from the equalised samples it is necessary to rate up-convert the samples, for example by interpolation, to the symbol rate of the signal. Thereafter the symbols are applied to a decision stage.

Adjustment of the tap coefficients of the equaliser may be carried out by making an error measurement on the data derived from the decision stage using, for example, either a training sequence such as the preamble and/or synchronisation sequence(s) transmitted as part of the signal, or a comparison of the input with the output from the decision stage. Since the equaliser is operating at a sampling rate which is lower than the symbol rate, the error measurement signals have to be rate down-converted.

In one embodiment of the present invention, the receiver is a baseband or zero IF receiver. Quadrature related frequency down-converted signals I and Q are low pass filtered in respective filters having a bandwidth significantly less than that of the signal bandwidth before being sampled at half the symbol rate and applied to respective equalisers. The even period I and Q signals are applied to one equaliser and the odd period I and Q signals are applied to the other equaliser. The equaliser signals are then rate up-converted by multiplexing the outputs of the equalisers. Decisions on the values of the symbols are made using a de Buda type of demodulator. The results of the error measurements are rate down-converted by a multiplexing arrangement before being used to adjust the tap weights of the respective equalisers.

If the modulation of the signal is in accordance with a bandwidth efficient scheme, for example Tamed Frequency Modulation, then the frequency down-converted signal can be sampled at half the bit rate. Furthermore low pass filtering of the baseband signals can take place at substantially a quarter of the bit rate without loss of useful information.

The present invention will now be described, by way of example, with reference to the accompanying drawings, wherein: Figure 1 is a block schematic diagram of a simulated transmission channel, Figure 2 is a block schematic diagram of a linear equaliser, Figure 3 is a block schematic diagram of a decision feedback equaliser, Figure 4 illustrates a hypothetical channel impulse response, Figre 5 is a block schematic diagram of a receiver including digital data demodulating means in accordance with the present invention, and Figure 6 is a block schematic diagram of a dual branch zero IF receiver incluidng digital data demodulating means in accordance with the present invention.

In the drawings, the same reference numerals have been used to indicate corresponding features.

Figure 1 illustrates an elementary data transmission system as described and illustrated in a paper by J.W.M. Bergmans entitled "Equalisation, Detection and Channel Coding for Digital Transmission and Recording Systems", Proceedings "Sixth Symposium on Information Theory in the Benelux", The Netherlands, May 1985 pages 161 to 169. A binary data source 10 is coupled to a transmitter 12 formed by a modulator, which produces a signal s(t). The signal s(t) is applied to a dispersive transmission channel 14 which comprises a filter 16 and a noise source 18 and which is modelled as a filtered signal channel, the impulse response h(t) of which is incompletely known.The channel 14 introduces memory and noise into the modulated signal to form an output signal r(t). This signal r(t) is applied to a receiver 20 formed by a receiving filter 22, a linear equaliser 24 and a bit-by-bit detector 26. The output of the detector 26 is connected to a data sink 28.

In the receiver 20, the channel noise is partially suppressed by means of the receiving filter 22. This filter has a small bandwidth and as a consequence introduces extra memory.

The influence of the total memory of the modulator, channel and receiving filter is ideally eliminated by means of an equaliser.

This enables detection by means of the simple bit-by-bit detector 26.

In Figure 1 the equaliser comprises a linear filter and hence the designation linear equaliser. Bergmans remarks that the receiving filter 22 and the equaliser 24 mutually influence each other. More powerful equalisation methods enable the receiving filter 22 to have a smaller bandwidth thereby causing a better suppression of noise and improved transmission quality.

In the following description of embodiments of the present invention, equalisation may be effected using a linear equaliser (LE) or a decision feedback equaliser (DFE). Figure 2 illustrates a LE comprising a tapped delay line 30 having five taps connected to respective multipliers 32, 34, 36, 38 and 40 to which are also applied weighting coefficients hl to h5. The outputs of the multipliers 32 to 40 are summed in an adding stage 42 whose output is coupled to a bit detector 26 (Figure 1).

Because the channel impulse response of the channel is incompletely known the tap weights are determined recursively so that the equalised sample of the signal which has come from the wanted signal (or symbol) is as large as possible relative to the portions (or samples) coming from the subsequent symbols. The LE is in known receivers normally operated at the symbol rate and the number of taps is related to the number of samples in the impulse response. The amount of processing required and thereby the current consumption is usually related to the square of the number (N) of taps.

Figure 3 illustrates a DFE which comprises a feedforward section 44 and a feedback section 46 which includes a decision stage 48. The feedforward section 44 is similar to the LE shown in Figure 2 and in the interests of brevity it will not be described in detail. The main difference occurs in the values of the weighting coefficients hl to h5 which are calculated to reduce the effects of samples of the following symbols.

The feedback section 46 is essentially a recursive filter formed by a subtraction stage 50 having one input connected to the adding stage 42 and an output connected to the input of the decision stage 48. The decision stage 48 is connected to an output terminal 52 and also to a transversal filter formed by a tapped delay line 54 (or an equivalent such as a shift register), the four taps of which are connected to respective multipliers 56 to 62 to which weighting coefficients h6 to h9 are connected respectively. The outputs of the multipliers are summed in an adding circuit 64 whose output is applied to a second input of the subtraction stage 50. In operation, the feedback section 46 is driven by preceding data decisions and in so doing cancels the effects of the preceding symbols on the current decision.

Advantages of a DFE over an LE are that any noise enhancement is reduced and the weighting coefficients are easier to calculate.

As with the LE, the amount of processing by a DFE and thereby its power consumption is typically proportional to the square of the number of taps in the feedforward and feedback sections 44, 46.

Figure 4 illustrates a channel impulse response (CIR) of a hypothetical dispersive communications channel. The CIR comprises a plurality of samples which occur at time intervals tO to t5, respectively which correspond to the symbol rate. With the arrangement shown in Figure 1, the equaliser has been operated at the symbol rate. However according to the Nyquist sampling theorem, when bandwidth efficient modulation is used, the data can be sampled at less than the symbol rate and the resulting samples will still carry all the desired information necessary for demodulation. Accordingly in accordance with an embodiment of the present invention the data is sampled at tO, t2 and t4 of the channel impulse response and is applied to an equaliser, either a LE or DFE, having half the number of taps used by known equalisers.Reducing the number of taps in the equaliser, reduces both the amount of processing and the power consumption. Whilst the data can be equalised at half the symbol rate, samples at the symbol rate are more suitable for symbol detection. This can be achieved by providing a rate up-converter, for example an interpolator, to produce samples at the intervening periods, that is at tl, t3 and t5 in Figure 4.

Figure 5 is a block schematic diagram of a receiver including digital data demodulating means made in accordance with the present invention. A data input signal having a symbol period t seconds which is present on an input terminal 66 is applied to one input of a mixer 68 to a second input of which a local oscillator 70 is connected. A frequency down-converted signal from the mixer 68 is filtered in band pass filter 72 having a narrow bandwidth to eliminate as much noise as possible. The output of the band pass filter 72 is sampled at intervals of 2t seconds in a sampling device 74 and applied to an equaliser 76 which may be a DFE or an LE operating at the sampling rate (that is half the symbol rate).The equalised output is applied to an interpolator 78 which produces the missing samples at intervals tl, t3 and t5 (Figure 4) and thereby a sample stream at the symbol rate is derived which is applied to a symbol detector 80. The symbol values derived by the detector 80 are applied to a data sink (not shown) by way of a terminal 82.

As the signal characteristics about a channel may not be fully known at switch-on and also the CIR may change dynamically it is necessary to train the equaliser coefficients recursively.

This may be done by an error measurement stage 84 which can be operated in one of two ways and which is coupled to the output line from the symbol detector 80. One technique is to compare the input to the detector 80 (that is, the equalised signal) with the corresponding output from the detector 80. This can be done by feeding the signal from the interpolator 78 to the stage 84 using a line 86. A second technique is to compare the symbols on the output terminal 82 with a training sequence applied to the stage 84 by way of an input 88. The training sequence may comprise preamble and/or synchronising signals which form part of the signalling format. The error measurements produced will be at the symbol rate which is too high.Accordingly these error measurements are applied to a rate down-converter 90 which reduces the number of error measurements to be applied to a processing circuit forming part of the equaliser 76. In some cases the rate down conversion will be implicit in the algorithms used to adjust the equaliser coefficients.

Figure 6 illustrates an embodiment of the present invention which is fabricated as a dual branch receiver in which the rate increase of the signals after equalisation is achieved by multiplexing and the symbol detection of the multiplex signals is achieved using a de Buda type of coherent demodulator disclosed in an article "Coherent Demodulation of Frequency-Shift Keying with Low Deviation Ratio" by Rude de Buda IEEE Transactions on Communications, June 1972, pages 429 to 435.

The receiver shown in Figure 6 comprises an antenna 92 which is connected to first and second mixers 94, 96. A local oscillator 98 is coupled to a second input of the mixer 94 and, by way of a 90 degree phase shifter 100, to a second input of the mixer 96. Low pass filters 102, 104 having a bandwidth equal to a quarter of the bit rate pass the desired components of the frequency down-converted outputs of the mixers 94, 96, respectively. This bandwidth is sufficient to satisfy the Nyquist sampling rate. The output IN, QN of the filters 102, 104 are quadrature related in that there is a relative phase shift of 90 degrees between the signals which corresponds to a quarter of a symbol period.

A signal sampling arrangement comprising pairs of switches 106, 108 and 110, 112, which are actuated alternately at half the symbol rate, couples even numbered samples of the IN and QN signals, that is samples I2N, Q2N, to the input of a first complex decision feedback equaliser (eql) 114 and the odd numbered samples, that is I2N+1, Q2N+1, to the input of a second complex decision feedback equaliser (eq2). The equalised signals Ieql, Qeql and Ieq2, Qeq2 from the equalisers 114, 116, respectively, are multiplexed using change-over switches 118, 120 operating at the symbol rate to produce I and Q signals at the bit rate which are applied to a coherent detector or demodulator 122. Data is produced on an output 124.I and Q decision signals Idec and Qdec are applied to an error measurement stage 126 and error signals at the symbol rate are produced. A demultiplexing arrangement formed by change-over switches 128, 130 apply two even numbered error signals, that is Idec-2N and Qdec-2N alternately to the first equaliser 114 and two odd numbered error signals, that is Idec-2N+1 and Qdec-2N+1, alternately to the second equaliser 116. A delay of 2N occurs because of the demodulating arrangmeent for the I and Q signals comprises, respectively, a two-input exclusive-OR gate one input of which receives a preceding symbol delayed by two symbol periods. The outputs of the exclusive-OR gates are applied to interleaving gates. Such an arrangement is shown in Figure 6 of the earlier mentioned article by de Buda.

The receiver shown in Figure 6 has particular, but not exclusive, application to partial response modulated signals such as Tamed Frequency Modulation (TFM) and Gaussian Minimum Shift Keying (GMSK), which are bandwidth efficient and typically require a transmission bandwidth of half the bit rate or less.

Thus for a symbol rate of 2400 bits per second, the TFM transmission bandwidth is 1200 bits per second. After frequency down-conversion in the mixers 94,96 the signal is filtered in the low pass filters 102, 104 which have a bandwidth equal to a quarter of the symbol rate, that is 600 bits per second. The sampling devices 108 to 112 are operated at the Nyquist rate, namely 1200 bits per second, in order that the sampled signals carry all the desired information necessary for demodulation.

The equalisers 114, 116 are operated at the sampling rate of 1200 bits per second and thereafter the samples are interpolated to provide digital signals at the symbol rate. The remainder of the circuit operates as described previously.

In the examples given above the equaliser(s) is (or are) run at half the symbol rate. For modulation schemes in which the signal bandwidth can be reduced to an even smaller fraction of the symbol rate, for example heavily filtered GMSK, it will be possible to run the equaliser at even Lower sampling rates.

Provided the Nyquist criterion is obeyed (that is sampling at twice the signal bandwidth) the necessary information for demodulation can still be recovered.

From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known in the design, manufacture and use of digital data demodulating arrangements and component parts thereof and which may be used instead of or in addition to features already described herein.

Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims (30)

CLAIM(S)

1. A method of demodulating a band limited digital signal, comprising equalising the signal by sampling the signal at less than the symbol rate.

2. A method as claimed in Claim 1, further comprising rate increasing the equalised samples to the symbol rate.

3. A method of demodulating a band limited digital signal, comprising equalising the signal by sampling the signal at less than the symbol rate, rate increasing the equalised samples to the symbol rate and applying the rate increased signals to a decision stage.

4. A method as claimed in any one of Claims 1 to 3, wherein the band limited digital signal is frequency down-converted prior to being equalised.

5. A method as claimed in Claim 4, wherein the frequency down-converted signal is sampled at half the symbol rate.

6. A method as claimed in any one of Claims 1 to 5, wherein the equalised samples are rate increased by interpolation.

7. A method as claimed in any one of Claims 1 to 6, wherein the band limited digital signal has been modulated in accordance with a bandwidth efficient modulation scheme.

8. A method as claimed in Claim 7, wherein the modulation scheme is Tamed Frequency Modulation.

9. A method as claimed in Claim 7, wherein the modulation scheme is Gaussian Minimum Shift Keying.

10. A method as claimed in Claim 7, 8 or 9, wherein the frequency down-converted signal is filtered in a filter having a bandwidth less than half the symbol rate.

11. A method as claimed in Claim 3 or any one of Claims 4 to 10 when appended to Claim 3, wherein coefficients of the equaliser are updated recursively by obtaining an error measurement based on the decisions made in the decision stage, rate reducing the error measurements to the sampling rate of the equaliser and recalculating the coefficients using the reduced rate error measurements.

12. A method as claimed in Claim 11, wherein the error measurement is made on the basis of comparing the inputs to, with the corresponding outputs from, the decision stage.

13. A method as claimed in Claim 11, wherein the error measurement is made on the basis of comparing the decisions produced by the decision stage with a training sequence present in the transmitted signal.

14. A method as claimed in Claim 4 or any one of Claims 5 to 13 when appended to Claim 4, wherein the frequency down-conversion is effected in quadrature to obtain I and Q signals, wherein even numbered samples of the I and Q signals are equalised in one equaliser and odd numbered samples of the I and Q signals are equalised in a second equaliser, and wherein the I and Q sample outputs of the equalisers are rate increased to the symbol rate by multiplexing said outputs.

15. A method as claimed in Claim 14 when appended to Claim 11, 12 or 13, wherein I and Q error measurements are obtained at the symbol rate, the rate of the I and Q error measurements are reduced to the sample rate of the equalisers, the even numbered I and Q error measurement samples are applied to said one equaliser to update recursively its coefficients, and wherein the odd numbered I and Q error measurement samples are applied to said second equaliser to update recursively its coefficients.

16. A method as claimed in any one of Claims 1 to 15, wherein the equalisation of the band limited digital signals is by decision feedback equalisation.

17. A method as claimed in any one of Claims 1 to 15, wherein the equalisation of the band limited digital signals is by linear equalisation.

18. A digital data demodulator comprising an input for a band limited digital signal, equalising means coupled to the input and means for clocking the equalising means at a sampling rate which is less than the symbol rate of the data signal.

19. A demodulator as claimed in Claim 18, wherein means are coupled to the equalising means for rate increasing the equalised samples to the symbol rate.

20. A digital data demodulator comprising an input for a band limited digital signal, equalising means coupled to the input means for clocking the equalising means at a sampling rate which is less than the symbol rate of the data signal, means coupled to the equalising means for rate increasing the equalised samples to the symbol rate and a decision stage coupled to the rate increasing means for determining the data from the rate increased equalised samples.

21. A demodulator as claimed in any one of Claims 18 to 20, further comprising means connected to said input for frequency down-converting the received digital signal.

22. A demodulator as claimed in any one of Claims 18 to 21, wherein the clocking means operates at half the symbol rate.

23. A demodulator as claimed in Claim 19 or 20 or Claim 21 or 22 when appended to Claim 19 or 20, wherein the rate increasing means comprises interpolation means.

24. A demodulator as claimed in Claim 21 or Claim 22 or 23 when appended to Claim 21, further comprising a filter having a bandwidth less than half the symbol rate coupled to the output of the frequency down-converting means.

25. A demodulator as claimed in Claim 20 or any one of Claims 21 to 24 when appended to Claim 20, further comprising means coupled to the decision stage for deriving error measurements at the symbol rate, rate reducing means coupled to the error measurement deriving means for producing error measurements at the sampling rate, and means coupled to the rate reducing means for updating recursively the coefficients of the equaliser.

26. A demodulator as claimed in Claim 21 or any one of Claims 22 to 25 when appended to Claim 21, wherein the frequency down-conversion means comprises first and second mixers coupled to the input, the first and second mixers each having an input for a received signal and an input for a local oscillator signal and an output for a frequency down-converted signal, means for shifting the phase of signal applied to an input of one of the first and second mixers by 90 degrees whereby the output (I) of the first mixer is quadrature related with respect to the output (Q) of the second mixer, the equalising means comprises first and second equalisers, means for applying even numbered samples of the I and Q outputs to the first equaliser and odd numbered samples of the I and Q outputs to the second equaliser, and means for multiplexing I and Q equalised samples from the first and second equalisers and applying them to the decision stage.

27. A demodulator as claimed in any one of Claims 18 to 26, wherein the equalising means comprise at least one decision feedback equaliser.

28. A demodulator as claimed in any one of Claims 18 to 26, wherein the equalising means comprise at least one linear equaliser.

29. A method of demodulating a digital signal, substantially as hereinbefore described with reference to the accompanying drawings.

30. A digital data demodulator substantially as hereinbefore described with reference to and as shown in the accompanying drawings.