GB2215124A - Integrated circuit underpasses - Google Patents
Integrated circuit underpasses Download PDFInfo
- Publication number
- GB2215124A GB2215124A GB8803506A GB8803506A GB2215124A GB 2215124 A GB2215124 A GB 2215124A GB 8803506 A GB8803506 A GB 8803506A GB 8803506 A GB8803506 A GB 8803506A GB 2215124 A GB2215124 A GB 2215124A
- Authority
- GB
- United Kingdom
- Prior art keywords
- underpass
- underpasses
- transistor array
- elongate
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
In an integrated circuit transistor array an elongate underpass 11 is provided between parts of a conductive line 13. The underpass may have two or more elongate parallel contacts 14 which can be separated on the underpass as required. This allows for customer configuration of contact positions. <IMAGE>
Description
IMPROVEMENTS IN INTEGRATED CIRCUITS.
This invention relates to integrated circuits and in particular to the provision of underpasses in such circuits.
Transistor array devices, for example bipolar analogue arrays, are conventionally customised by the application of one or more layers of configurable metal whereby circuit elements are coupled in a particular way to provide a desired circuit function. Usually only a single layer of metal is available and in such cases it is normal for the chip to contain a number of relatively low impedance semiconductor underpasses to facilitate metal routing. Such underpasses are relatively small and have their silicon to metal contact windows in a fixed position as the contact mask is not configurable by the customer. This can provide serious constraints on the layout of the metal routing.
The object of the invention is to minimise or to overcome this disadvantage.
According to the invention there is provided a transistor array adapted to provide a predetermined circuit function by the application thereto of a conductor pattern, said array including a plurality of similar cells of transistors, routing paths between said cells for a conductor pattern whereby selected transistors are interconnected, and one or more underpasses whereby cross-overs of said pattern are provided, wherein each said underpass is elongate in configuration whereby contact windows providing access to the underpass may be disposed at positions determined by the function of the underpass.
The elongate underpass allows the use of a customer configurable mask for the positioning of the contact windows. This allows each underpass to be tailored to the local topological requirements thus improving design flexibility.
Embodiments of the invention will now be described with reference to the accompanying drawings in which Figures 1 to 4 illustrate various configurationa of an elongate underpass.
Referring to Figure 1 of the drawings, this depicts an elongate underpass 11 which provides a cross-over between a power bus 12 and a signal line 13.
The underpass 11 is provided by a diffusion or implantation in a semiconductor substrate and is covered by an insulating layer (not shown). To accomodate the relatively wide power bus 12 the contacts 14 whereby the signal line 13 is connected to the underpass are displaced towards the end of the underpass.
In Figure 2 the underpass 11 provides a cross-over between a pair of signal lines 21 and 22. In this structure the contact windows 23 are disposed near the centre of the underpass thus minimising thne resistance of the underpassing signal line 22.
Figure 3 illustrates the use of the underpass 11 on a multijunction arrangement e.g. for use in encoders, decoders and signal buses. In this structure further contacts 31, 32 are provided between the contacts 33 to which signal line 34 is connected. These further contacts provide a connection between signal line 34 and signal lines 35 and 36. The underpass also provides a cross-over between signal line 34 and further signal lines 37.
Figure 4 shows an alternative cross-over between a power bus 41 and a signal line 42. In this arrangement elongate contacts 43 are disposed longitudinally on the underpass 11 and provide connection to the power bus 41. As the contacts 41 are close together and extend for most of the underpass length, a very low resistance path is provided.
The underpass arrangement described above are of particular application in bipolar analogue arrays. It will however be understood that their use is not limited to such arrays and that underpasses of this type may be used in other integrated circuit constructions.
Claims (4)
1. A transistor array adapted to provide a predetermined circuit function by the application thereto of a conductor pattern, said array including a plurality of similar cells of transistors, routing paths between said cells for a conductor pattern whereby selected transistors are interconnected, and one or more underpasses whereby cross-overs of said pattern are provided, wherein each said underpass is elongate in configuration whereby contact windows providing access to the underpass may be disposed at positions determined by the function of the underpass.
2. A transistor array as calimed in Claim 1, wherein at least one of said underpasses is provided with elongate parallel contacts adapted to provide connection to a power bus.
3. A transistor array as claimed in claim 1, wherein at least one of said underpasses is provided with more than two contacts whereby to provide a circuit node.
4. A transistor array substantially as described herein with reference to and as shown in any one or more of Figures 1 to 4 of the accompanying drawing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8803506A GB2215124A (en) | 1988-02-16 | 1988-02-16 | Integrated circuit underpasses |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8803506A GB2215124A (en) | 1988-02-16 | 1988-02-16 | Integrated circuit underpasses |
Publications (2)
Publication Number | Publication Date |
---|---|
GB8803506D0 GB8803506D0 (en) | 1988-03-16 |
GB2215124A true GB2215124A (en) | 1989-09-13 |
Family
ID=10631768
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8803506A Withdrawn GB2215124A (en) | 1988-02-16 | 1988-02-16 | Integrated circuit underpasses |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2215124A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5747867A (en) * | 1995-01-09 | 1998-05-05 | Siemens Aktiengesellschaft | Integrated circuit structure with interconnect formed along walls of silicon island |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1182325A (en) * | 1966-05-19 | 1970-02-25 | Philips Electronic Associated | Improvements in and relating to Semiconductor devices |
GB1209268A (en) * | 1967-06-23 | 1970-10-21 | Rca Corp | Integrated circuit array of cells |
GB1209269A (en) * | 1967-06-23 | 1970-10-21 | Rca Corp | Array of cells in integrated circuits |
US3584269A (en) * | 1968-10-11 | 1971-06-08 | Ibm | Diffused equal impedance interconnections for integrated circuits |
GB1315171A (en) * | 1969-09-15 | 1973-04-26 | Ibm | Read only store |
US4161662A (en) * | 1976-01-22 | 1979-07-17 | Motorola, Inc. | Standardized digital logic chip |
GB1567197A (en) * | 1976-10-25 | 1980-05-14 | Philips Electronic Associated | Methods of manufacturing semiconductor devices |
EP0042643A1 (en) * | 1980-06-23 | 1981-12-30 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device and semiconductor device manufactured by using said method |
US4521799A (en) * | 1982-12-27 | 1985-06-04 | Motorola, Inc. | Crossunder within an active device |
-
1988
- 1988-02-16 GB GB8803506A patent/GB2215124A/en not_active Withdrawn
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1182325A (en) * | 1966-05-19 | 1970-02-25 | Philips Electronic Associated | Improvements in and relating to Semiconductor devices |
GB1209268A (en) * | 1967-06-23 | 1970-10-21 | Rca Corp | Integrated circuit array of cells |
GB1209269A (en) * | 1967-06-23 | 1970-10-21 | Rca Corp | Array of cells in integrated circuits |
US3584269A (en) * | 1968-10-11 | 1971-06-08 | Ibm | Diffused equal impedance interconnections for integrated circuits |
GB1315171A (en) * | 1969-09-15 | 1973-04-26 | Ibm | Read only store |
US4161662A (en) * | 1976-01-22 | 1979-07-17 | Motorola, Inc. | Standardized digital logic chip |
GB1567197A (en) * | 1976-10-25 | 1980-05-14 | Philips Electronic Associated | Methods of manufacturing semiconductor devices |
EP0042643A1 (en) * | 1980-06-23 | 1981-12-30 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device and semiconductor device manufactured by using said method |
US4521799A (en) * | 1982-12-27 | 1985-06-04 | Motorola, Inc. | Crossunder within an active device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5747867A (en) * | 1995-01-09 | 1998-05-05 | Siemens Aktiengesellschaft | Integrated circuit structure with interconnect formed along walls of silicon island |
Also Published As
Publication number | Publication date |
---|---|
GB8803506D0 (en) | 1988-03-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4161662A (en) | Standardized digital logic chip | |
US5650653A (en) | Microelectronic integrated circuit including triangular CMOS "nand" gate device | |
US4811073A (en) | Gate array arrangement | |
EP0782187B1 (en) | A library of standard cells for the design of integrated circuits | |
US5917230A (en) | Filter capacitor construction | |
KR970063679A (en) | A method of wiring metal interconnect lines in an integrated circuit, and the integrated circuit manufactured thereby | |
EP0792520A1 (en) | Transistor structure with specific gate and pad areas | |
US5229629A (en) | Semiconductor integrated circuit having improved cell layout | |
US5157477A (en) | Matched impedance vertical conductors in multilevel dielectric laminated wiring | |
US4234888A (en) | Multi-level large scale complex integrated circuit having functional interconnected circuit routed to master patterns | |
US5539246A (en) | Microelectronic integrated circuit including hexagonal semiconductor "gate " device | |
US5440153A (en) | Array architecture with enhanced routing for linear asics | |
CA1102009A (en) | Integrated circuit layout utilizing separated active circuit and wiring regions | |
US4890191A (en) | Integrated circuits | |
US4631570A (en) | Integrated circuit having buried oxide isolation and low resistivity substrate for power supply interconnection | |
EP0421168B1 (en) | Semiconductor memory with metallic interconnection layer of the same potential as the word line and connected thereto outside of the memory cell region | |
GB2215124A (en) | Integrated circuit underpasses | |
US5654563A (en) | Microelectronic integrated circuit including triangular semiconductor "or"g | |
JPH0817227B2 (en) | Semiconductor chips that can be personalized | |
JP4041873B2 (en) | Electrostatic discharge protection circuit and method for forming electrostatic discharge protection circuit | |
JPH11251430A (en) | Method and system for mutually connecting conductive elements in integrated circuit | |
KR100413148B1 (en) | Low resistance contacts for minimizing the voltage required to electrically blow fuses | |
US5656850A (en) | Microelectronic integrated circuit including hexagonal semiconductor "and"g | |
US5631581A (en) | Microelectronic integrated circuit including triangular semiconductor "and" gate device | |
EP0690509A1 (en) | Substrate contact for gate array base cell and method of forming same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |