GB2205682A - A semiconductor device - Google Patents
A semiconductor device Download PDFInfo
- Publication number
- GB2205682A GB2205682A GB08712971A GB8712971A GB2205682A GB 2205682 A GB2205682 A GB 2205682A GB 08712971 A GB08712971 A GB 08712971A GB 8712971 A GB8712971 A GB 8712971A GB 2205682 A GB2205682 A GB 2205682A
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- region
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- dielectric material
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 239000003989 dielectric material Substances 0.000 claims abstract description 21
- 230000015556 catabolic process Effects 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 5
- 230000005669 field effect Effects 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000001465 metallisation Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 210000000746 body region Anatomy 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910001415 sodium ion Inorganic materials 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005686 electrostatic field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- -1 sodium ions Chemical class 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Passivating dielectric material (9) is provided on a given surface (3) covering further regions (6) which surround a main p-n junction (5), and a respective electrically conductive region (11), which may be in the form of a metal area, is provided on the passivating layer (9) so as to cover each further region (6) and so that each electrically conductive region (11) is electrically isolated from the semiconductor body and spaced apart from the other electrically conductive regions (11). Each electrically conductive region lies within the bounds of the respective underlying further region (6) and is electrically isolated from the underlying further region (6) by the passivating dielectric material (9). The main p-n junction (5) is reverse-biased in at least one mode of operation of the device and the further regions lie within the spread of the depletion region of this junction so as to increase the breakdown voltage of the junction. The device may be fabricated as a rectifier diode, field effect transistor, bipolar transistor or thyristor. <IMAGE>
Description
A SEMICONDUCTOR DEVICE
This invention relates to a semiconductor device, for example a rectifier diode, field effect transistor, bipolar transistor or thyristor, having a gn junction which is operated under reverse bias in at least one mode of operation of the device.
DE-A-3338718 describes a semiconductor device comprising a semiconductor body having a first region of one conductivity type adjacent a given surface of the body and a second region of the opposite conductivity type surrounding the first region so as to form with the first region a main Ìn junction which is reverse-biased in at least one mode of operation of the device. A further region of the one conductivity type provided in the second region spaced apart from the first region and adjacent the given surface surrounds the main p-n junction and lies within the spread of the depletion region of the main p-n junction when the main rn junction is reverse-biased in operation of the device so as to serve to increase the breakdown voltage of the main ern junction.
Passivating dielectric material in the form of a layer on the given surface covers the further region.
As described in DE-A-3338718, more than one such further region may be provided surrounding the main rn junction and one or more of the further regions is contacted by a metal electrode which extends through the passivating dielectric material layer onto the surface of the dielectric layer and serves to tie the potential of the top surface of the passivating dielectric material layer to that of the underlying further region. The metal electrode may extend beyond the bounds of the underlying further region towards the main rn junction to act as a field plate.
EP-A-182,422 describes a similar semiconductor device in which the metal electrodes do not contact the underlying further regions but are connected together by a resistive layer which extends outwardly from an electrode contacting the first region and may extend over or be interrupted by the metal electrodes.
According to the present invention, there is provided a semiconductor device comprising a semiconductor body having a first region of one conductivity type adjacent a given surface of the body, a second region of the opposite conductivity type surrounding the first region so as to form with the first region a main E n junction which is reverse-biased in at least one mode of operation of the device, a further region of the one conductivity type provided in the second region spaced apart from the first.region and adjacent the given surface, the further region surrounding the main gn junction and lying within the spread of the depletion region of the main E"n junction when the main rn junction is reverse-biased in operation of the device so as to serve to increase the breakdown voltage of the main p-n junction, passivating dielectric material on the given surface covering the further region and an electrically conductive region provided on the passivating layer over the further region so as to cover the further region and so as to be electrically isolated from the semiconductor body, the electrically conductive region lying within the bounds of the further region and being electrically isolated from the further region by the passivating dielectric material.
A plurality of spaced apart further regions may be provided in the second region adjacent the given surface, the further regions each surrounding the main will junction so as to lie within the spread of the depletion region of the main rn junction when the main gn junction is reverse-biased in operation of the device, each further region being covered by passivating dielectric material and a respective conductive region being provided over each further region so as to cover the further region and so as to be electrically isolated from the semiconductor body and spaced apart from the other electrically conductive region(s), each electrically conductive region lying within the bounds of the associated further region and being electrically isolated from the associated further region by the passivating dielectric material.
As used herein, the term 'electrically isolated' should be understood to mean that there is no electrical contact between the conductive region(s) and the semiconductor body or the further region(s).
Further passivating dielectric material may cover the conductive region(s) and may be in the form of a layer extending from the first region over the given surface so as to cover the electrically conductive region(s). Alternatively, the further passivating dielectric material may be provided on the passivating material to cover the side edges only of the electrically conductive region(s).
The passivating material on the given surface may similarly be in the form of a layer extending from the first region over the further region(s).
The or each electrically conductive region may comprise a metal area but other electrically conductive material, for example electrically conductive polycrystalline silicon, could be used to form the conductive regions.
The or each further region may be annular and be concentric with the first region, it being understood that the term annular as used herein is not restricted to circular annuli but includes polygonal annuli, for example square or rectangular annuli (possibly with rounded corners) or other non-circular e.g. oval annuli.
The shape or geometry of the further regions will normally be similar if not the same as the shape of the first region. The further region(s) need not necessarily be in the form of solid annuli or annulus. Thus the or one or more of the further regions may be made up of a number of closely spaced discrete subsidiary regions or islands separated by the second region. In such a case, the electrically conductive region(s) will similarly be made of a number of subsidiary regions-or islands, each electrically conductive island lying within the bounds of and being insulated from the underlying island of the further region.
Embodiments of the invention will now be described, by way of example, with reference to the accompanying diagrammatic drawing, in which:
Figure 1 shows a cross-sectional view of part of a semiconductor device in accordance with the invention, and
Figure 2 shows a cross-sectional view of part of a modified version of the semiconductor device shown in Figure 1.
It should be noted that Figure 1 and Figure 2 are not drawn to scale; the relative dimensions and proportions of parts of these
Figures (particularly in the direction of thickness) have been exaggerated or diminished for the sake of clarity and convenience in the drawings. The same reference signs as used in one embodiment are generally used when referring to corresponding or similar parts in the other embodiment.
The semiconductor device of Figure 1 comprises a semiconductor body 1 (for example of monocrystalline silicon) having a first or active device region 2 of the one conductivity type (g type in the example shown) adjoining or meeting a given surface 3 of the semiconductor body 1. A second region 4 of the opposite conductivity type (n type in the example shown) adjoining or meeting the given surface 3 surrounds the first region 2 so as to form with the first region 2 a main gn junction 5 which extends to the given or upper major surface 3. The main E n junction 5 is operated in reverse-bias in at least one mode of operation of the device, by applying a reverse-biasing voltage between connections A and B in Figure 1.
Further regions 6 of the one conductivity type (g type in the example shown) are provided spaced apart in the second region 4 adjacent the given surface 3. As shown each further region 6 is an annular region surrounding and concentric with the active device region 2. Each further region forms a respective auxiliary rn junction 7 with the second region 4 and is arranged so as to be located within the spread of the depletion region of the main p-n junction 5 when the main E n junction 5 is reverse-biased in operation of the device so as to increase the breakdown voltage of the main rn junction 5.In Figure 1 an example of a depletion layer 8 is shown as extending across the thickness of the second region 4 although in some cases the depletion layer 8 may not extend so deeply from the junction 5.
A passivating dielectric layer 9, for example a layer of silicon dioxide, extends on the given surface 3 from the active device region 2 over the annular regions 6 and over a more highly doped channel stopper region 10 of the opposite conductivity type (n type in this example) which, if provided, extends in a concentric arrangement around the further regions 6.
A respective electrically conductive region 11 is provided on the passivating dielectric layer 9 to cover each annular region 6 so that each electrically conductive region 11 lies within the bounds of the associated underlying further region 6 and is electrically isolated from the semiconductor body 1 and spaced apart from the other electrically conductive regions 11, the passivating dielectric layer 9 electrically isolating or insulating each conductive region 11 from the associated underlying further region 6. In the arrangement shown in the drawings, the further regions 6 are annular regions arranged concentrically about the first region 2 and accordingly the electrically conductive regions 11 will be similar annularly shaped regions arranged concentrically about the first region 2.
Each conductive region 11 lies within the underlying further region 6 in such a manner that the outer and inner edges Ila and lib of the conductive region 11 are aligned with outer and inner edges 6a and 6b, respectively, of the underlying further region 6.
It should of course be appreciated, as indicated in the Figures, that, in practice, the alignment will be to normal manufacturing tolerances and that the edges Ila and lib may in practice be slightly offset or misaligned from the corresponding edges 6a and 6b. Also, it should be understood that a conductive region 11 may be intentionally slightly smaller or larger in width than the underlying further region 6 yet still be considered to lie within the bounds of the underlying further region 6.
A further electrically conductive region 10a contacts the channel stopper region and extends up onto the passivating layer 9 so as to lie within the bounds of the channel stopper region 10.
In the example given above, the electrically conductive regions 10a and 11 are in the form of annular metal plates, for example aluminium plates, but the conductive regions 10a and 11 may also be formed of other electrically conductive material.
In the arrangement shown in Figure 1, although not shown, further passivating dielectric material may be provided over the surface 9a of the passivating dielectric layer 9 exposed between the conductive regions 11 leaving top surfaces 11' of the conductive regions 11 exposed. Alternatively as illustrated in
Figure 2, a further passivating dielectric layer 12 may extend from the first region 2 to cover the conductive regions 10a and 11 completely. The further passivating dielectric material may be silicon nitride to provide a barrier to contaminant ions such as sodium ions and also to moisture.
It is believed that each conductive region 11 capacitively couples to the underlying further region 6 so that the voltage drop across the surface of the passivating dielectric layer 9 follows more closely the voltage drop within the semiconductor body along the given surface 3 outwardly from the main p-n junction 5. Such a capacitive coupling enables vertical electric fields in the passivating layer 9 under and between the conductive regions 11 to be minimised or at least reduced and hence assists in minimising the effect of external mobile ions (e.g. sodium ions) above the passivating layer on the voltage distribution at the surface 3 of the semiconductor body.The electrically conductive regions 11 may also act as a physical barrier to prevent migration of contaminant ions, e.g. sodium ions, along the surface of the passivating layer 9 towards the main p-n junction 5.
The passivating layer 9 should be sufficiently thick underneath the conductive regions 11, for example of the order of 0.2 micrometres, to ensure electrical isolation or insulation (that is to prevent any contact between the conductive region and the further region) of the electrically conductive region 11 from the underlying further region 6 but should be sufficiently thin to enable capacitive coupling between the underlying further region 6 and the electrically conductive region 11. In one example, the passivating layer 9 may have a thickness in the region of 2 to 3 micrometres and may be formed by a first thermally grown layer of silicon dioxide and a subsequent layer of silicon dioxide deposited from the vapour phase.
The devices shown in Figure 1 and Figure 2 may be manufactured using existing power semiconductor technology. Thus, for example, the second region 4 may be a monocrystalline silicon substrate which is lowly doped so as to be of the opposite conductivity type (n type in this example) and the active device region 2 and annular regions 6 which are more highly doped than the second region 4 may be formed by locally (using an appropriate mask) implanting and/or diffusing dopant of the one conductivity type (ptype in this example) to locally overdope the substrate or second region 4.
The channel stopper region 10, if provided, is formed by local dopant (n type in this example) introduction in a separate step from the regions 2 and 6. The passivating dielectric layer 9 may be of, for example, silicon dioxide and may be formed by thermally oxidising the given surface 3 or by depositing a layer on the surface. A window 13 (and a further window over the channel stopper region 10, if provided) is opened in the passivating dielectric layer 9 to enable contact to be made to the active device region 2 (and the channel stopper region 10) by depositing metal, for example aluminium. The electrically conductive regions 11 may be formed of the same metal as the active device region metallisation 14 and may be formed at the same time as the active device region metallisation 14 by using an appropriate mask. Metallisation 16 is similarly deposited on the surface 15 of the semiconductor body 1 opposite the given surface 3. To ensure a good contact, a more highly doped layer 17 of the opposite conductivity type (n+ type in this example) may be provided by dopant diffusion and/or implantation at the surface 15.
As illustrated in the figures, not only are the conductive regions 11 aligned to the underlying further regions 6 as described above, but the metallisation 14 extends up onto the passivating layer 9 to terminate at an edge 14a aligned with the edge 2a of the underlying region 2.
The annular regions 6 and 10 may be circular rings which have circular symmetry around the active device region 2 at the given surface 3. However, other geometrical outlines are possible, depending on the outline of the active device region 2 and the type of the device and it should be understood that, as used herein, the term annular encompasses not only circular annuli but annuli which are polygonal in plan, for example four or six sided polygonal annuli, or which are non-circular, for example etliptical or oval.
Thus, for example the region 2 may have a square or rectangular outline with straight sides but with rounded corners and the concentric annular regions 6 and 10 may be similarly square or rectangular with straight sides and rounded corners. Such different outlines and geometries are already known in the power semiconductor device art and so will not be described further in the present specification. For convenience and simplicity in the drawing, Figure 1 and Figure 2 show a cross-section through part of the annular region structure 6 and 10 at the right-hand side of the active device region 2.
The series of further regions 6 serves to increase the breakdown voltage of the -n junction 5 by widening the spread of the depletion layer 8 along the given surface 3 so as to reduce the associated electrostatic field adjacent the surface to a value less than that of the critical field for electron-hole pair generation by avalanche breakdown. The precise number, widths and spacings of the annular regions depend on the desired breakdown voltage and the depths of the regions, and these are chosen as appropriate to the type of device. Thus, although six regions 6 are shown in Figure 1, one single deep annular region may be sufficient for some devices in accordance with the invention, especially for lower voltage operation.Also where a number of regions 6 are provided the width of the regions 6 may vary as described in EP-A-115093 and/or the depth of the regions may be varied as described in EP-A-124139.
Although the further regions 6 are described above as being annular regions, one or more of the further regions 6 could be formed of a number of discrete subsidiary regions or islands and also where the geometry of the device is non-circular, additional such subsidiary regions or islands may be provided near corners of the active device region where local high spots in the electric field (which could lead to premature breakdown) may be expected.
Thus, for example a further region 6 may be made up of one or more rows of islands, for example circular islands, disposed spaced apart along an imaginary path concentric with and surrounding the active device region.
Where a further region is formed of discrete subsidiary regions or islands, the electrically conductive region 11 associated with the further region will similarly be formed of discrete subsidiary regions or islands each lying within the associated underlying island of the further region and being electrically isolated from the other electrically conductive region islands, the passivating dielectric layer electrically isolating or insulating the conductive electrically conductive region islands from the underlying islands of the associated further region.
The basic device structure shown in Figure 1 and Figure 2 may be used for various types of semiconductor device in accordance with the invention, for example a power rectifier diode, a high voltage bipolar transistor, a thyristor, or a high voltage insulated-gate field-effect transistor.
In the case of a power rectifier diode, the main rn junction 5 may constitute the rectifying junction, contacts A and B to the metallisation 14 and 16 providing the diode terminals. However the rectifying junction of a power rectifier diode in accordance with the invention may be formed by a metal-semiconductor Schottky contact to the second region 4 and this Schottky junction may be bounded at its periphery by an annular guard region 2.
In the case of a lateral insulated-gate field-effect transistor, the gn junction 5 may constitute the drain junction formed by an annular p type drain region 2 which extends around and is spaced from a central p type source region and an intermediate channel region of the transistor, and the body portion or second region 4 may be a high resistivity n type epitaxial layer on a highly-doped n type substrate 17 to which the p type source region may be short-circuited in known manner.
If the insulated-gate field-effect transistor is of vertical type, that is so that the metallisation 16 provides the drain contact, then the region 2 may be a body region within which the source region (not shown) is provided so that part of the body region defines a channel area of the transistor, the source region being again shorted to the body region.
In the case of a bipolar transistor, the rn junction 5 may constitute a base-collector junction of the transistor, the region 2 being a p type base region which is provided in a high resistivity n type epitaxial layer 4 on a highly-doped n type substrate 17. The electrode contacts A and B are then base and collector terminals respectively of the transistor, and at least one highly-doped n type emitter region (not shown) having its own electrode is provided in the base region 2. The main gn junction 5 may even be one blocking junction of a thyristor structure. In this latter case, the Figure 1 structure is modified to have for example a high resistivity n type substrate 4 into which p type regions 2 and 17 may be diffused to form two oppositely-located blocking -n junctions, the p type region 17 constituting the anode of the thyristor while an n type cathode emitter is provided in the p type base region 2.
Where a lateral rather than vertical device is desired, the electrically conductive region 10a may form one of the main contacts and the contact B omitted, for example the electrically conductive region 10a may provide the collector contact of a lateral bipolar transistor or the drain contact of a lateral insulated-gate field-effect transistor.
The conductivity types of all the regions of the devices shown in the drawings may be reversed to form opposite conductivity type devices. Furthermore semiconductor materials other than silicon may be used for the devices, although allowance must then be made for different critical field strengths for avalanche breakdown in such other semiconductor materials.
From reading the present disclosure, other modifications will be apparent to persons skilled in the semiconductor art for example persons skilled in the design, manufacture and/or use of semiconductor devices. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or novel combination of features disclosed herein either explicitly or implicitly or any generalisation or modification of that feature or of one or more of those features which would be obvious to persons skilled in the art, whether or not it relates to the same invention as presently claimed in any claim. The applicants hereby give notice that new claims to such features and/or combinations of such features may be formulated during the prosecution of the present application or of any further application derived therefrom.
Claims (9)
1. A semiconductor device comprising a semiconductor body having a first region of one conductivity type adjacent a given surface of the body, a second region of the opposite conductivity type surrounding the first region so as to form with the first region a main p-n junction which is reverse-biased in at least one mode of operation of the device, a further region of the one conductivity type provided in the second region spaced apart from the first region and adjacent the given surface, the further region surrounding the main g-n junction and lying within the spread of the depletion region of the main p-n junction when the main p-n junction is reverse-biased in operation of the device so as to serve to increase the breakdown voltage of the main p-n junction, passivating dielectric material on the given surface covering the further region and an electrically conductive region provided on the passivating layer over the further region so as to cover the further region and so as to be electrically isolated from the semiconductor body, the elecrically conductive region lying within the bounds of the further region and being electrically isolated from the further region by the passivating dielectric material.
2. A semiconductor device according to Claim 1, wherein a plurality of spaced apart further regions are provided in the second region adjacent the given surface, the further regions each surrounding the main p-n junction so as to lie within the spread of the depletion region of the main rn junction when the main gn junction is reverse-biased in operation of the device, each further region being covered by passivating dielectric material and a respective conductive region being provided so as to cover each further region and so as to be electrically isolated from the semiconductor body and spaced apart from the other electrically conductive region(s), each electrically conductive region lying within the bounds of the associated further region and being electrically isolated from the associated further region by the passivating dielectric material.
3. A semiconductor device according to Claim 1 or 2, wherein further passivating dielectric material covers the conductive region(s).
4. A semiconductor device according to Claim 3, wherein the further passivating dielectric material is in the form of a layer extending from the first region over the given surface so as to cover the conductive region(s).
5. A semiconductor device according to Claim 1 or 2,.wherein further passivating dielectric material is provided on the passivating material to cover the side edges only of the conductive region(s).
6. A semiconductor device according to any preceding claim, wherein the passivating dielectric material is in the form of a layer extending from the first region over the further region(s).
7. A semiconductor device according to any preceding claim, wherein the or each conductive region comprises a metal area.
8. A semiconductor device substantially as herebefore described with reference to, and as illustrated in, Figure 1 or 2 of the accompanying drawing.
9. Any novel feature or combination of features described herein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08712971A GB2205682A (en) | 1987-06-03 | 1987-06-03 | A semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08712971A GB2205682A (en) | 1987-06-03 | 1987-06-03 | A semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8712971D0 GB8712971D0 (en) | 1987-07-08 |
| GB2205682A true GB2205682A (en) | 1988-12-14 |
Family
ID=10618302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08712971A Withdrawn GB2205682A (en) | 1987-06-03 | 1987-06-03 | A semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2205682A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0461877A2 (en) * | 1990-06-12 | 1991-12-18 | Mitsubishi Denki Kabushiki Kaisha | Structure for preventing electric field concentration in semiconductor device |
| US5113237A (en) * | 1988-09-20 | 1992-05-12 | Siemens Aktiengesellschaft | Planar pn-junction of high electric strength |
| US5324971A (en) * | 1992-04-09 | 1994-06-28 | U.S. Philips Corporation | Power semiconductor device having over voltage protection |
| EP0661753A1 (en) * | 1994-01-04 | 1995-07-05 | Motorola, Inc. | Semiconductor structure with field limiting ring and method for making |
| EP1058315A1 (en) * | 1999-06-03 | 2000-12-06 | STMicroelectronics S.r.l. | Edge termination of semiconductor devices for high voltages with capacitive voltage divider |
-
1987
- 1987-06-03 GB GB08712971A patent/GB2205682A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5113237A (en) * | 1988-09-20 | 1992-05-12 | Siemens Aktiengesellschaft | Planar pn-junction of high electric strength |
| EP0461877A2 (en) * | 1990-06-12 | 1991-12-18 | Mitsubishi Denki Kabushiki Kaisha | Structure for preventing electric field concentration in semiconductor device |
| EP0461877A3 (en) * | 1990-06-12 | 1994-05-11 | Mitsubishi Electric Corp | Structure for preventing electric field concentration in semiconductor device |
| US5324971A (en) * | 1992-04-09 | 1994-06-28 | U.S. Philips Corporation | Power semiconductor device having over voltage protection |
| EP0661753A1 (en) * | 1994-01-04 | 1995-07-05 | Motorola, Inc. | Semiconductor structure with field limiting ring and method for making |
| EP1058315A1 (en) * | 1999-06-03 | 2000-12-06 | STMicroelectronics S.r.l. | Edge termination of semiconductor devices for high voltages with capacitive voltage divider |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8712971D0 (en) | 1987-07-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |