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GB2296155B - Data decompression circuit - Google Patents

Data decompression circuit

Info

Publication number
GB2296155B
GB2296155B GB9600315A GB9600315A GB2296155B GB 2296155 B GB2296155 B GB 2296155B GB 9600315 A GB9600315 A GB 9600315A GB 9600315 A GB9600315 A GB 9600315A GB 2296155 B GB2296155 B GB 2296155B
Authority
GB
United Kingdom
Prior art keywords
data decompression
decompression circuit
circuit
data
decompression
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9600315A
Other versions
GB2296155A (en
GB9600315D0 (en
Inventor
Amit Mital
David Voth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsoft Corp
Original Assignee
Microsoft Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/263,540 external-priority patent/US5512921A/en
Application filed by Microsoft Corp filed Critical Microsoft Corp
Publication of GB9600315D0 publication Critical patent/GB9600315D0/en
Publication of GB2296155A publication Critical patent/GB2296155A/en
Application granted granted Critical
Publication of GB2296155B publication Critical patent/GB2296155B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T9/00—Image coding
    • G06T9/005—Statistical coding, e.g. Huffman, run length coding
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/46—Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/02—Handling of images in compressed format, e.g. JPEG, MPEG

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Multimedia (AREA)
  • Digital Computer Display Output (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Liquid Crystal Display Device Control (AREA)
GB9600315A 1994-06-22 1995-06-16 Data decompression circuit Expired - Fee Related GB2296155B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/263,540 US5512921A (en) 1994-06-22 1994-06-22 Visual display system having low energy data storage subsystem with date compression capabilities, and method for operating same
GB9512315A GB2291528B (en) 1994-06-22 1995-06-16 Display system with data compression

Publications (3)

Publication Number Publication Date
GB9600315D0 GB9600315D0 (en) 1996-03-13
GB2296155A GB2296155A (en) 1996-06-19
GB2296155B true GB2296155B (en) 1997-04-23

Family

ID=26307227

Family Applications (2)

Application Number Title Priority Date Filing Date
GB9600315A Expired - Fee Related GB2296155B (en) 1994-06-22 1995-06-16 Data decompression circuit
GB9624541A Expired - Fee Related GB2306271B (en) 1994-06-22 1995-06-16 Data analyser

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB9624541A Expired - Fee Related GB2306271B (en) 1994-06-22 1995-06-16 Data analyser

Country Status (1)

Country Link
GB (2) GB2296155B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12141094B2 (en) 2020-03-14 2024-11-12 Intel Corporation Systolic disaggregation within a matrix accelerator architecture

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0863497A1 (en) * 1997-03-06 1998-09-09 Sony Computer Entertainment Inc. Graphic data generation device with frame buffer regions for normal and size reduced graphics data
GB2331649A (en) * 1997-11-25 1999-05-26 Dilip Daniel James Image compresssion system
US10474458B2 (en) 2017-04-28 2019-11-12 Intel Corporation Instructions and logic to perform floating-point and integer operations for machine learning
US11934342B2 (en) 2019-03-15 2024-03-19 Intel Corporation Assistance for hardware prefetch in cache access
US20220114108A1 (en) 2019-03-15 2022-04-14 Intel Corporation Systems and methods for cache optimization
KR20210135998A (en) 2019-03-15 2021-11-16 인텔 코포레이션 Sparse Optimization for Matrix Accelerator Architectures
US11954062B2 (en) 2019-03-15 2024-04-09 Intel Corporation Dynamic memory reconfiguration
US11861761B2 (en) 2019-11-15 2024-01-02 Intel Corporation Graphics processing unit processing and caching improvements
US11663746B2 (en) 2019-11-15 2023-05-30 Intel Corporation Systolic arithmetic on sparse data

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2260236A (en) * 1991-10-04 1993-04-07 Sony Broadcast & Communication Data encoder

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5305111A (en) * 1990-12-11 1994-04-19 Industrial Technology Research Institute Run length encoding method and system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2260236A (en) * 1991-10-04 1993-04-07 Sony Broadcast & Communication Data encoder

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12141094B2 (en) 2020-03-14 2024-11-12 Intel Corporation Systolic disaggregation within a matrix accelerator architecture

Also Published As

Publication number Publication date
GB9624541D0 (en) 1997-01-15
GB2306271B (en) 1997-07-16
GB2296155A (en) 1996-06-19
GB9600315D0 (en) 1996-03-13
GB2306271A (en) 1997-04-30

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20010616

732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20150312 AND 20150318