GB2292855A - CMOS latch suitable for low voltage operation - Google Patents

Abstract

The master and slave latches comprise cross-coupled inverters 15, 16 and 21, 22. Complementary input signals are fed to the latch nodes 17, 18 and 23, 24 through nmos switches 19, 20 and 25, 26. During storage of an input signal one of the latch nodes will be pulled down sufficiently strongly to overcome the output of the latch inverter feeding that node. Transistors 8', 29 and 30 act as inverters. Pull-up pmos transistors are not required in these inverters. A scan input may be provided (figures 4 and 5). <IMAGE>

Description

An electrical circuit comprising a latch This invention relates to an electrical circuit comprising a latch.

In a known latch circuit, an element for storing a data bit is formed from two inverters that are crosscoupled together (that is to say, the output of each inverter is connected to the input of the other inverter) between two terminals. An input in the form of an electrical signal is supplied to the latch from a data source and is applied, through a switch, to one terminal of the storage element. The switch is in the form of an N channel pass transistor connected between the data source and one terminal of the storage element. The switch is controlled by a clock signal from a clock source connected to the gate of the pass transistor. The data bit stored in the storage element is available through its two terminals, on which one output is the inverse of the other.In this latch circuit, a data bit to be stored is supplied to one terminal of the storage element only, making use of the fact that one inverter in the storage element is stronger than the other inverter (that is to say, the current output from one inverter is greater than the current output from the other inverter) so that the data stored can be changed as required by applying the data bit to the input of the stronger inverter. As the input data bit is supplied to the terminal at the input of the stronger inverter, when a new data bit is supplied, the supplied signal overcomes the output of the weaker inverter to cause the stored data bit to change in response to the supplied signal.

A disadvantage of the prior art circuit described above is that at low supply voltages, for example, 3V, more errors are likely to occur than at higher supply voltages when the correct data as supplied to the latch is not received and stored correctly in the storage element. Such errors occur as a result of the voltage drop across the N channel pass transistor. In such circuits, a bit "1" is represented by a signal level in a first range of voltages and a bit "0" is represented by a signal level in a different range of voltages separated from the first range of voltages.An error occurs when the voltage of a signal supplied to the input of the pass transistor that falls within the range of voltages representing a bit "1", say, has its voltage reduced as a result of the voltage drop across the pass transistor, so that it falls outside that range and may represent neither a bit "1" nor a bit "O". If the circuit is designed to operate with a smaller supply voltage, inevitably the ranges of voltages representing the bits 11011 and "1" generally become smaller and lie closer together. As a result, the voltage drop across the pass transistor is more likely to cause errors.

A second disadvantage of the circuit is that power is consumed when the first, stronger inverter overcomes the second, weaker inverter in the storage element to change the stored data bit. A further disadvantage of the circuit described above is the requirement for the two inverters in the latch to be of different strengths.

If the circuit is manufactured as an integrated circuit, then the need for different sized inverters necessitates the use of different geometries for the devices of the inverters, increasing the cost per unit of the IC.

In order to overcome the problem just descrbed it has been proposed to use a transmission gate, comprising a P channel transistor and an N channel transistor in parallel, in place of the single N channel pass transistor. That arrangement has the advantage that the transmission gate does not produce a voltage drop and consequently the latch does not fail at low supply voltages. When a transmission gate is used, however, two clocks are required for controlling the gate: the first clock controls the N channel transistor, and the second clock, which is the inverse of the first clock, operates the P channel transistor. The generation of the second clock inevitably increases the power consumption of the circuit when the data bit is not changing (that is to say when the circuit is operating in non-toggle mode).

The type of latch described above is used in a known two-stage or master-slave, level-triggered latch.

A two-stage latch comprises two latches connected together in cascade, each latch comprising a storage element in the form of a pair of cross-coupled inverters.

A data bit is input to one terminal of the storage element in the first latch, the "master" latch, through a first switch in the form of an N channel pass transistor operated by a first clock. The second terminal of the storage element in the master latch provides the output of that latch and is connected to one terminal of the storage element in the second latch, the "slave" latch, through a second switch, also in the form of an N channel pass transistor, operated by a second clock, and the data bit stored in the master latch is written into the slave latch when the second clock turns on the second switch.

In use, the two clocks are out of phase by half a period so that data bits are stepped through the latch.

This type of level-triggered, two-stage latch has the advantage that the clock input capacitance is very low, typically of the order of 0.034pF in 0.8 m technology, and hence the power consumption in the circuit is low. Generally, the power consumption in a level-triggered two-stage latch is lower than the power consumption in a conventional, edge-triggered two-stage latch. In non-toggle mode the power consumption is almost zero, and the total power required to clock the latch in non-toggle mode at the system level is extremely low. The known two-stage latch described above shares the above-described disadvantages of the single-stage latch when operated by a low supply voltage.

The use of low supply voltages in devices is increasingly being considered in circuit design. Amongst other reasons, the use of low supply voltages is desirable because of the resulting reduction in power consumption. The reduction in power consumption is particularly welcome in certain applications, for example, telecommunications. If circuits can be designed that operate satisfactorily at low supply voltages then in battery operated devices the number of batteries can be reduced, making devices lighter and more portable, and having obvious environmental benefits. Circuits which can operate satisfactorily at low supply voltages would also be advantageous, for example, in devices using a solar power cell, where the supply voltage might fall, say, to 1.5V, when the light intensity is reduced. In view of the advantages of low supply voltages, it is clearly desirable to design circuits and components that operate satisfactorily at such voltages.

Accordingly, the present invention provides a circuit including a latch comprising a bistable element in the form of two cross-coupled inverters connected between a first and a second terminal, a first and a second switch, each switch having an input terminal and an output terminal, the output terminal of the first switch being connected to the first terminal of the bistable element and the output terminal of the second switch being connected to the second terminal of the bistable element, each switch being controllable by a clock signal, the circuit also comprising a first input for a data signal having a voltage within a first one of two predetermined voltage ranges representing a data bit to be stored in the latch, and a second input for the inverse of the data signal and having a voltage within the second of the two voltage ranges, the first input being connected to the input terminal of the first switch and the second input being connected to the input terminal of the second switch.

Because a signal dependent on the data signal is supplied simultaneously to both sides of the bistable, storage element of the latch, the correct data bit is always written into the latch, even at low voltages. The circuit receives two signals respectively representing the input data signal and the inverse of the input data signal, one signal being applied to one side of the storage element and the other signal being applied to the other side of the storage element. Even if the voltage drop across the switches causes one of the data signals to be incorrectly passed on to the storage element by taking the more positive signal, for example, outside its allowed voltage range, the other signal will still be correctly passed on to the storage element because its voltage will remain within the allowed range, with the result that the data bit will be correctly entered.

The circuit may include a second bistable element comprising two further inverters cross-coupled between a third and a fourth terminal, a third and a fourth switch, each switch having an input terminal and an output terminal, the output terminal of the third switch being connected to the third terminal and the output terminal of the fourth switch being connected to the fourth terminal, each switch being controllable by a clock signal, wherein the second bistable element is so connected to the first and second terminal of the first bistable element to receive, in use, through the third and fourth switches, data signals from the first bistable element dependent on the data stored in that first bistable element. This type of circuit is known as a two-stage, or "master-slave" latch circuit, and is commonly used in digital circuits.

Preferably, buffering means are connected between the terminals of the first bistable element and the input terminals of the third and fourth switches to ensure that signals are not fed back from the second, or slave, latch to the master latch. The buffering means may consist of suitably connected N-channel field-effect transistors.

The transistors may be small and take up less wafer space than CMOS inverters in an integrated circuit.

Preferably, each switch is an N-channel fieldeffect pass transistor, and preferably, in use, the relevant clock signal is applied to the gate of the appropriate transistors.

Because there are two pass transistors in each transfer connection from one latch to the next, they can be smaller than the pass transistors used for a singleended data transfer as in the prior art. That reduction in size means that clock input capacitance is lower and consequently the power consumption is reduced.

The pair of cross-coupled inverters in the or each bistable element may be identical to each other. As a result, the manufacture of the circuit is simpler than it would be if the inverters were different.

The inverting means may consist of a suitably connected N-channel field-effect transistor. In comparison with a CMOS inverter, the transistor is smaller, and consumes less power.

The invention also provides a method of entering binary coded data into a latch comprising two crosscoupled inverters in which each bit of the data is provided as logic levels in both upright and inverted forms which are applied at the same time respectively to the inputs of both inverters of the latch.

The logic levels representing a bit of the data are preferably applied to the inverters of the latch through respective pass transistors that are opened at the same time by a clock signal.

Several forms of latch circuit constructed according to the invention will now be described by way of example only, with reference to the accompanying drawings of which: Fig. 1 is a circuit diagram of a single-stage latch circuit; Fig. 2 is a circuit diagram of a first example of a master-slave latch circuit; Fig. 3 is a circuit diagram of a second example of a master-slave latch circuit; Fig. 4 is a circuit diagram of a third example of a master-slave latch circuit; and Fig. 5 is a circuit diagram of a further example of a master-slave latch circuit.

Fig. 1 shows a single-stage latch circuit. The circuit has a basic cell comprising a bistable, storage element consisting of a pair of identical inverters 1, 2 that are cross-coupled between a first terminal 3 and a second terminal 4 with the output of each inverter being connected to the input of the other inverter. A first switch and a second switch in the form of a first and a second N channel pass transistor 5, 6 is provided at the terminals of the storage element. One terminal of the channel of the first pass transistor 5 is connected to the first terminal 3 of the storage element and one terminal of the channel of the second pass transistor 6 is connected to the second terminal 4 of the storage element. A clock source (not shown), for controlling the pass transistors 5, 6, is connected by a conductor C to the gates of the two pass transistors 5, 6.

A data source (not shown), supplying data bits to be stored in the latch, is connected by a conductor D to the storage element. The conductor D is connected to the input of an inverter buffer 7 and the output of that buffer 7 is connected to the input of the first pass transistor 5, thereby connecting the data source to the first terminal 3 of the storage element. The output of the inverter buffer 7 is also connected to the input of a second inverter buffer 8, and the output of that second inverter buffer 8 is connected to the input of the second pass transistor 6. In that way the data source is also connected to the second terminal 4 of the storage element of the latch.

Further inverters 9, 10 are connected to the first and second terminals 3, 4 of the latch respectively, and the output terminals of those two inverters provide logic level outputs on conductors Q and QZ depending on the value stored in the latch.

In use, the data source supplies data bits in the form of digital signal levels to be stored in the latch.

A signal level between 0 and 1.5 Volts represents a "0" and a signal level between 3.5 and 5.0 Volts represents a "1". A signal which is the inverse of the signal from the data source is supplied from the inverter 7 to the input of the first pass transistor 5. In this context, the inverse signal is a signal which has a voltage falling within the range representing the alternative bit to that represented by the signal from the data source.

For example, when the signal from the data source has a voltage representing the bit "1", then the inverse signal has a voltage representing the bit "0".) A signal corresponding to the signal from the source is supplied at the same time as that signal from the inverter 8 to the input of the second pass transistor 6.

The clock turns on the pass transistors 5, 6 and the data bit is written into the latch.

When the clock signal occurs and a data bit is written into the latch, signals are supplied to the two terminals of the storage element simultaneously, the signal supplied at one terminal being of the inverse logic level to that of the signal at the other terminal.

Because signals are supplied to both sides of the storage element they enable the data bit stored in the latch to be changed without the need for one inverter to produce an output large enough to overcome the output of the other inverter. In contrast to the prior art circuit, there is therefore no need to have one inverter stronger than, and therefore of different geometry from, the other inverter in the latch. It is not, however, essential for the inverters to be identical, but of course the use of identical structures for the two inverters will simplify manufacture of the latch.

The circuit has two output terminals with two outputs Q and QZ respectively. The logic level of the output Q corresponds to the logic level of the original data signal stored in the latch while the output QZ has a logic level that is the inverse of the original data signal. In non-toggle mode, the output of the latch does not change.

Even at low supply voltages, the circuit shown in Fig. 1 correctly stores the supplied data. Suppose the supply voltage is 3V, a voltage of between 0 Volts and 1 Volt represents a "0", a voltage of between 2 Volts and 3 Volts represents a "1" and the voltage drop across the N channel pass transistors is 0.5 Volts (all voltages being measured with respect to a predetermined reference value). Suppose also that the data source supplies a signal of logic level "1", in which case the signal supplied to the input of the first N channel pass transistor 5 is of logic level "0" and the signal supplied to the input of the second N channel pass transistor 6 is "1".If the signal representing a "1" supplied to the second pass transistor 6 is between 2 Volts and 2.5 Volts then the voltage drop across the transistor leads to an output signal of below 2 Volts in which case the output signal does not represent a "1" and the transistor fails to pass on correctly the signal to one side of the latch. Even in such circumstances, the data bit is still correctly stored in the latch because the "0" supplied to the first pass transistor is correctly passed on to the other terminal of the latch.

To switch the latch only requires one side to be pulled down by a pass transistor, so that the latch can function at very low supply voltages, for example, of 2.0 Volts and below.

Fig. 2 shows a two-stage, master-slave latch circuit. The circuit comprises two latches in cascade, the first latch, known as the master latch, is indicated generally by the reference numeral 11, and the second latch, known as the slave latch, is indicated generally by the reference numeral 12. As in the single phase latch, the master latch 11 and the slave latch 12 each comprise a basic cell, indicated generally by the reference numerals 13 and 14 respectively.

The basic cell 13 in the master latch 11 consists of a bistable, storage element in the form of a pair of inverters 15, 16 cross-coupled between first and second terminals 17, 18, a first and a second switch in the form of first and second N channel pass transistors 19, 20 connected to the first and second terminals 17, 18 respectively of the cross-coupled inverters 15, 16, and a clock source (not shown) connected by a conductor MC to the gate of each of the first and second pass transistors 19, 20.Similarly, the basic cell 14 in the slave latch 12 consists of a second bistable storage element in the form of a pair of inverters 21, 22 cross-coupled between third and fourth terminals 23, 24, third and fourth switches in the form of third and fourth N channel pass transistors 25, 26 connected to the third and fourth terminals 23, 24 respectively of the cross-coupled inverters 21, 22, and a second clock source (not shown) connected by a conductor SLC to the gate of each of the third and fourth pass transistors 25, 26.

The basic cell 13 in the master latch 11 is connected to the basic cell 14 in the slave latch 12 by a pair of inverter buffers 27, 28. Each terminal 17, 18 of the cross-coupled inverters 15, 16 in the basic cell 13 of the master latch 11 is connected to the input of a respective inverter 27, 28, the output of which is connected to the input of the corresponding pass transistor in the basic cell 14 of the slave latch 12.

A data source (not shown) is provided for supplying a signal to the two-stage latch. The data source is connected by a conductor D to the inputs of the two pass transistors 19, 20 in the master latch 11 in a similar way to that shown in the single-stage latch described above.

Similarly, the two-stage latch has two output terminals, on conductors Q and QZ, which are connected to the terminals 23, 24 of the cross-coupled inverters 21, 22 in the slave latch 12 in the same way as described for the single-stage latch described above.

In the same way as described above for the single stage latch, data bits are supplied from the data source and are written into the master latch 11 at intervals when their clock signal triggers the pass transistors 19, 20 for the master latch 11. A data bit stored in the master latch 11 is transferred to the slave latch 12 when their clock signal triggers the pass transistors 25, 26 in the slave latch 12. The master latch 11 has two outputs and the data bit stored in the master latch 11 is transferred from the master latch 11 in the form of two signals to the slave latch 12. The slave latch 12 receives a signal at each of the terminals 23, 24 of the storage component and accordingly there is no need for one inverter in the storage element of the slave latch 12 to overcome the other inverter. The two clock signals occur alternately so that a data bit is transferred from the master latch 11 to the slave latch 12 before a new data bit is written into the master latch.

The pair of inverters 27, 28 connected between the master latch 11 and the slave latch 12 act as buffers to prevent signals from the slave latch 12 from being fed back to the master latch 11. The inverters 27, 28 could be omitted if the storage element in the master latch 11 had larger inverters, producing more current, than the slave latch 12.

As for the single stage latch, the logic level at the output Q corresponds to the logic level of the original signal in the data source.

In contrast with the prior art, the two-stage latch according to the invention requires two pass transistors per clock. The size of each of the N channel pass transistors can, however, be smaller than the single N channel pass transistor used in the prior art circuit, because each transistor only has to be able to pull down one side of the latch.

The two-stage level-triggered latch described above shares the advantage of low clock input capacitance, and hence low power consumption, with the known two-stage level-triggered latch described above, in spite of the fact that the circuit has two pass transistors for each clock instead of one. The clock input capacitance remains low because, for each clock, the two pass transistors to which the clock is connected are connected in parallel. The clock input capacitance depends on the size of the pass transistors and, because the pass transistors can be made smaller than the pass transistor needed in the prior art circuit, the input capacitance, and hence the power consumption, can be kept low.It has been found that the power consumption of a circuit comprising the two-stage latch shown in Fig. 2 in nontoggle mode is lower than the power consumption of the prior art two-stage latch in corresponding circumstances (0.4 WW compared with 1.2 WW in 0.8 Wm technology).

A circuit similar to that shown in Fig. 2 but in which the inverter 8 and the inverter buffers 27, 28 that connect the master latch 11 and the slave latch 12, are each replaced by a suitably connected single transistor, is shown in Fig. 3 where transistors 29, 30 and 8' are shown in place of the buffers 27, 28 and the inverter 8 respectively. Although the circuit shown in Fig. 3 has a slower switching speed than the circuit of Fig. 2, as a result of the use of the transistors in place of the inverter buffers, an inverter buffer is larger and consumes more power in operation than a single transistor, and so the circuit of Fig. 3 has advantages in certain applications.In addition, when the supply voltage is less than 2.5 Volts, the performance benefit of retaining the P channel transistors in CMOS inverter buffers is marginal due to the Vt drop across the N channel pass transistor so that the single transistor version is better for ultra-low voltage operation.

Fig. 4 shows a two-stage, master-slave latch circuit with connections for a scan data source suitable for scan testing applications. The circuit has a master latch, indicated generally by the reference number 31, and a slave latch, indicated generally by the reference number 32, connected in cascade. In this circuit, a data bit can be written into the master latch 31 from two different sources. The slave latch 32 comprises a basic cell as described above with reference to Fig. 2, and the same reference numerals are used in Fig. 4 for the same components in the slave latch 32.As before, the master latch 31 comprises a bistable storage element in the form of a pair of inverters 33, 34 cross-coupled between a first and a second terminal 35, 36, a first and a second switch in the form of a first and a second N channel pass transistor 37, 38 connected to the first and second terminals respectively of the cross-coupled inverters 33,34, and a clock source (not shown) connected to the gates of the first and second pass transistors 37, 38. In this case, however, the latch includes a further pair of pass transistors 39, 40 for use in supplying a data bit to the master latch 31 from the scan data source. One terminal of the first scan pass transistor 39 is connected to the first terminal 35 of the crosscoupled inverters 33, 34 in the master latch 31 and the second scan pass transistor 40 is similarly connected to the second terminal 36 in the latch.The gates of the transistors 39, 40 are connected to a scan clock that controls the pass transistors 39, 40. The scan data source is connected to the input of an inverter buffer 41 and the output of that buffer is connected to the source of the first pass transistor 39, thereby connecting the data source to the first terminal 35 of the storage element in the master latch. The output of the inverter buffer 41 is also connected to the input of a second inverter buffer 42, and the output of that second inverter buffer 42 is connected to the source of the second pass transistor 40. In that way the data source is also connected to the second terminal 36 of the storage element of the latch.

The master latch 31 is connected to the slave latch 32 by two inverter buffers 43, 44 connecting the two terminals of the storage element in the master latch 31 to the input terminals of the pass transistors 25, 26 in the slave latch 32, in exactly the same way as described above with reference to Fig. 2.

In normal operation, the scan test clock is turned off and data bits are written into the master latch 31 from the master data source and transferred to the slave latch 32 in the same way as described above with reference to the circuit shown in Fig. 2. In test mode, the master clock is turned off and data bits are written into the master latch 31 from the scan data source.

Again, the scan data is transferred from the master latch 31 to the slave latch 32 when the slave clock, which is out of phase by half a period from the scan test clock, turns on the pass transistors 25, 26.

The inverter buffers in the circuit shown in Fig. 4 can be replaced by N channel transistors to achieve, for example, a reduction in area occupied by the circuit, to reduce the power consumption or if the circuit is to be used at very low voltages, as explained above. A circuit in which the inverter buffers 8, 42, 43, 44 have been replaced by transistors 45, 46, 47, 48 is shown in Fig.

Claims (11)

1. A circuit including a latch comprising a bistable element in the form of two cross-coupled inverters connected between a first and a second terminal, a first and a second switch, each switch having an input terminal and an output terminal, the output terminal of the first switch being connected to the first terminal of the bistable element and the output terminal of the second switch being connected to the second terminal of the bistable element, each switch being controllable by a clock signal, the circuit also comprising a first input for a data signal having a voltage within a first one of two predetermined voltage ranges representing a data bit to be stored in the latch, and a second input for the inverse of the data signal and having a voltage within the second of the voltage ranges, the first input being connected to the input terminal of the first switch and the second input is connected to the input terminal of the second switch.

2. A circuit as claimed in claim 1 including a second bistable element comprising two further inverters crosscoupled between a third and a fourth terminal, a third and a fourth switch, each switch having an input terminal and an output terminal, the output terminal of the third switch being connected to the third terminal and the output terminal of the fourth switch being connected to the fourth terminal, each switch being controllable by a clock signal, wherein the second bistable element is so connected to the first and second terminals of the first bistable element to receive, in use, through the third and fourth switches, data signals from the first bistable element representing the data stored in that first bistable element.

3. A circuit as claimed in claim 2 wherein a first buffering means is connected between the first terminal of the first bistable element and the input terminal of the third switch and a second buffering means is connected between the second terminal of the first bistable element and the input terminal of the fourth switch.

4. A circuit as claimed in claim 3 wherein the buffering means consists of a suitably connected N-channel fieldeffect transistor.

5. A circuit as claimed in any one of claims 1 to 4 wherein each switch is an N-channel field-effect transistor, and wherein, in use, the or each clock signal is or are applied to the gates of the appropriate transistors.

6. A circuit as claimed in any one of claims 1 to 5 wherein the pair of cross-coupled inverters in the or each bistable element are identical to each other.

7. A circuit as claimed in any one of claims 1 to 6 wherein the inverse of the data signal is produced by an N-channel field-effect transistor connected as an inverter with the data signal applied to the gate of the last-mentioned transistor.

8. A circuit substantially as hereinbefore described, with reference to and as illustrated by any one of the Figures of the accompanying drawings.

9. A method of entering binary coded data into a latch comprising two cross-coupled inverters in which each bit of the data is provided as logic levels in both upright and inverted forms which are applied at the same time respectively to the inputs of both inverters of the latch.

10. A method according to claim 9 in which the logic levels representing a bit of the data are applied to the inverters of the latch through respective pass transistors that are opened at the same time by a clock signal.

11. A method substantially as hereinbefore described with reference to any one of the Figures of the accompanying drawings.