GB2135804A - Alpha numeric display device and visual display arrangement employing such display devices - Google Patents

Abstract

An alpha-numeric 'starburst' display device comprises twelve elongate elements in place of the normal fourteen, arranged as a cross (6, 7, 8), a diagonal cross (9, 10, 11, 12), and a parallelogram (1, 2, 3, 4, 5) which may be a rectangle. The bar (6) of the cross and the side (2) of the parallelogram may each be subdivided into two parts connected to function as one element, enabling a standard 14-element starburst display to be used. A full alpha-numeric set of characters can be displayed. When the elements are connected in a matrix, particularly in a multiplexed liquid crystal display, 4 x 3 is sufficient in place of the normal 4 x 4. <IMAGE>

Description

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SPECIFICATION

Alpha-numeric display device and visual display arrangement employing such display devices.

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The invention relates to an alpha-numeric display device comprising a plurality of elongate elements arranged to form a cross and a diagonal cross within a parallelogram. The invention also relates to a 10 visual display arrangement including a plurality of alpha-numeric display devices.

In such a display element in which the parallelogram is often substantially rectangular, commonly called a starburst display there are typically fourteen 15 elongate elements arranged two to each arm of each of the crosses, two to each vertical side of the rectangle and one to each horizontal side.

When a plurality of display elements are used to provide a multicharacter display it is usual to 20 multiplex the drive to the display to reduce the number of external connections required. The method of interconnection with displays made from light emitting diodes is to connect together all those elements that have the same location in each display 25 device and then to address each display device individually. However, this method of time division multiplexing is not widely used with liquid crystal displays because of limitations in the electro optic response of liquid crystals which, at present, prevent 30 the effective sequential address of more than three of four display devices. To produce liquid crystal displays having a greater number of characters each display can be configured as a matrix. A description of a matrix addressed display array is given in an 35 article entitled "Multiplexing Liquid-Crystal Displays" by Paul Smith which appeared in Electronics dated 25th May 1978 at pages 113-121, the contents of which are hereby incorporated by reference.

The fourteen element display device is normally 40 used when a full alpha-numeric display is required and in order to drive such a device a four by four matrix is needed. Thus four terminals are required for each character in a multicharacter display plus four terminals for the common connection to all the 45 characters.

A number of proposals have been made for display devices with fewer than fourteen elements. Examples of such display devices are shown in U.S. Patents Nos. 3971012 (Morokawa), 4184319 (Kuma-50 ta), and 4264966 (Terzian). However, the devices disclosed in these patents are not capable of displaying a full alpha-numeric character set but instead eliminate elements which are not required to display the limited number of characters which are to be 55 displayed. These display devices are shown as suitable for use in calender watches to show abbreviations for days of the week and thus only a limited number of letters are required to be displayed to indicate the required codes. Consequently while the 60 number of connections to each display device has been reduced this has been atthe expense of the display capability of the display devices.

It is an object of the invention to provide a display device which is capable of displaying a full set of 65 alpha-numeric characters and which requires a smaller number of connections than the fourteen element display device.

The invention provides an alpha-numeric display device as described in the opening paragraph characterised in that single elongate elements form three sides of the parallelogram, that a single elongate element forms the arm of the cross between the two opposite sides of the parallelogram formed by single elements, that the other side of the parallelogram is formed by two serially arranged elements, that the other arm of the cross is formed by two serially arranged elements, and that both arms of the diagonal cross are formed by two serially arranged elements.

The invention is based on the recognition of the factthatafull alpha-numeric display can be devised in which the central and right hand vertical elements of the star burst display are formed by single elements and consequently the highly desirable effect of reducing the number of connections and driving signals required to display a set of characters can be achieved.

One or more of the single elongate elements may be formed as two serially arranged elongate elements which are connected together so that a single driving signal operates both elements simultaneously. This enables a standard star burst display device to be easily converted into a display device according to the invention merely by electrically connecting together the connections to the two central vertical elements and to the two right hand vertical elements.

The elongate elements may be formed by liquid crystals, means being provided for selectively applying electrical signals to each element. The invention is particularly advantageous when applied to multi-character liquid crystal displays since the individual elements in such displays are usually connected and driven in a matrix form. Thus for a 14 element display a 4 x 4 matrix is required with two of the connections wasted whereas for a 12 element display 4 x 3 matrix is sufficient. Other forms of element such as light emitting diodes or incandescent lamps are not normally driven in matrix form but the device according to the invention still provides the advantage that the display driving information required to be stored is reduced in proportion to the reduced number of elements.

The invention further provides a visual display arrangement for displaying a plurality of alphanumeric characters comprising a plurality of such display devices in which the display devices are driven in time division multiplex form.

The visual display arrangement may be such that each display device is electrically arranged as a four row by three column matrix, that electrical driving signals are applied to the four rows of each display device simultaneously from a common source, and that the electrical driving signals applied to the three columns of each display device are generated from separate information sources.

Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:

Figure 1 shows a first embodiment of a display

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device according to the invention,

Figure 2 shows an alpha-numeric character set which can be generated with a display device according to the invention,

5 Figure 3 shows examples of alternative characters which can be generated with a display device according to the invention,

Figures 4a and 4b show the electrodes and their interconnections in a display device according to the 10 invention when produced as a liquid crystal display device.

Figure 5shows in schematic form the electrical connection of the display device shown in Figure 4 as a four by three matrix,

15 Figure 6 shows some waveforms of electrical driving signals for the display device of Figure 4,

Figure 7 shows in block schematic form a visual display arrangement according to the invention, Figure 8 shows a logic diagram of a first type of 20 multiplex waveform generator used in the arrangement of Figure 7, and

Figure 9 shows a logic diagram of a second type of multiplex waveform generator used in the arrangement of Figure 7.

25 Figure 1 shows in schematic form a display device comprising twelve elongate elements, of which elements 1 to 5 form a rectangle, elements 6 to 8 form a cross, and elements 9 to 12 a diagonal cross. The elongate elements may be formed in any 30 convenient manner and could be, for example light emitting diodes, liquid crystal cells or bars of material having faces of contrasting colours, the bars being selectively positionable to show a desired coloured face.

35 Figure 2 shows an alpha-numeric character set which can be displayed by appropriately energising the twelve elements of the display device shown in Figure 1. It can be seen from Figure 2 that a recognisable character can be generated to repre-40 sent each numeral from Oto 9 and each letter of the alphabet, the only ambiguity in this character set being between the letter S and the numeral 5. This ambiguity can be eliminated by substituting the character shown as Figure 3d in the character set 45 shown in Figure 2 as the letter S.

Figure 3 shows some further alternative characters which may be generated instead of those shown in Figure 2. Figure 3a shows an alternative form for the letter B, Figure 3b) and c) show alternative forms for 50 the letter J, Figure 3e) shows an alternative form for the letter V, Figures 3f) and g) show alternative forms for the letter Y, and Figures 3h) and i) show alternative forms for the numeral 4.

It is not essential that each elongate element is 55 rectangular but instead the elements may be shaped to provide a more aesthetically pleasing or more readable character. Further it is not essential that the elements 1 to 5 form a perfect rectangle, the displayed character typically may slope to the right. 60 Figure 4a) and b) shows the electrodes and their connections for a display device formed from liquid crystal elements and configured as a matrix for addressing. Figure 4a) shows the separate connections for each character while Figure 4b) shows the 65 common connections for all the display devices in a serial array.

For each display device (character) in the serial array a first connection A1 is arranged to be connected to a first electrode of elements 1,2,11, and 70 3; a second connection A2 is arranged to be connected to a first electrode of elements 4,5,9 and 10; and a third connection A3 is arranged to be connected to a first electrode of elements 12,7,8 and 6. In the serial direction of the array four connections 75 B1, B2, B3 and B4 are connected as a highway and in each display element B1 is connected to a second electrode of elements 1,10 and 8; B2 is connected to a second electrode of elements 9,6, and 2; B3 is connected to a second electrode of elements 5,7 and 80 11; and B4 is connected to a second electrode of elements 4,12 and 3.

Depending on the signals applied to the first and second electrodes of the elements the liquid crystal forming the elements will become either transparent 85 or opaque and hence by selectively applying appropriate signals to the connections A1, A2, A3, B1, B2, B3 and B4 the display devices can be operated to display a desired character.

With a matrix addressed liquid crystal display, 90 each element together with its associated backplane is electrically equivalent to a lossy, non-linear, voltage-dependent capacitor. Thus each display device may be represented schematically as row and column conductors inteconnected at each intersec-95 tion by a capacitor as shown in Figure 5. The reference numbers of the capacitors are the same as those of the elements which they represent. A series of select pulses drives each row while a series of data pulses drives each column. Figure 6b), c), d) and 100 e) shows the waveforms of the select pulses applied to the backplane terminals B1, B2, B3 and B4 respectively. The basic waveform of period T is shown as Figure 6a). Each period T is divided into eight sub-periods t.-i to t_8. Each row is selected for a 105 quarter of the period T by taking the basic waveform shown in Figure 6f) and modifying it to provide a positive going pulse in the first half of the period T and a negative going pulse in the second half of the period T. The positive going pulses occur for one 110 eighth of the period T the periods t1y t.2,t.3 and t.4 corresponding to the periods of the positive going pulses for the rows B1, B2, B3 and B4 respectively. Similarly the negative going pulses also occur for one eighth of the period T, the periods t.5, t.6, t.7 and 115 t_8 corresponding to the periods of the negative going pulses for the rows B1, B2, B3 and B4 respectively.

Examples of data pulses which may be applied to thecolumns A1, A2 and A3 are shown in Figure 6f) to 120 j). Referring to the line A1 waveform f) will cause all the elements 1,2,11,3 to be OFF; waveform g) will cause element 1 only to switch ON; waveform h) will cause element 2 only to switch ON; waveform i) will cause element 11 only to switch ON; and waveform 125 j) will cause element 3 only to switch ON. It will be readily apparent that these waveforms f) to j) may be combined to select more than one of the elements simultaneously.

In a particular construction the amplitude of the 130 waveforms in Figures 6a) to j) may be as shown in

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the Figure. The liquid crystal elements are operated by a.c. signals and the contrast ratio is dependent on the r.m.s. voltage of the a.c. signal across the element. Using the waveforms shown in Figure 6 it 5 can be derived that the r.m.s. voltage across an element which is switched OFF is 1 volt and that across an element which is switched ON is 1.73 volts. Other voltages may be used dependent on the requirements of the liquid crystal cells used. 10 Figure 7 shows in block schematic form an arrangement for driving an n character display, where n is an integer, for example sixteen. Such a display may, for example, be used on a telephone instrument to display the numberdialled orto 15 display simple messages such as NUMBER ENGAGED.

The arrangement shown in Figure 7 has an input terminal 100 to which input data in the form of characters to be displayed is fed. The input data may 20 be in the form of a serial ASC II code which is clocked into a shift register 101 under the control of a clock signal on a line 102 which is generated in a clock signal generator 103. The clock signals produced by the generator 103 must either be synchronised with 25 the input data or some means must be provided to synchronise the clock and data. When a character has been received it is fed in parallel to a decoder 104 over lines 105-1 to 105-/7. The decoder 104 which may be in the form of a read only memory (ROM) 30 produces outputs which are fed via an appropriate one of the lines 106-1 to 106-/7 to an encoder 107 which converts the decoded character into an element code which indicates which elements of a display device are to be driven to display that 35 character. The encoder 107 may also be formed by a ROM and may be combined with the ROM 104 to produce the element drive code directly from the input code. The output of the encoder 107 is fed via lines 108-1 to 108-n and clocked into a register 109 in 40 parallel under the control of clock signals from the clock signal generator 103 over a line 110. A further clock signal causes the data to be read out of the register 109 into a selected one of a plurality of registers 111-1 to 111-/7, the particular register being 45 selected by means of address signals generated in the clock generator 103 and fed to the registers 111-1 to 111-/7 over lines 112-1 to 112-/7. The outputs of the register 111-1 to 111-/7 are fed via lines 113-1 to 113-/7 to inputs of respective multi pi ex waveform gener-50 ators 114-1 to 114-/7. The multiplex waveform generators 114-1 to 114-/7 are also fed with clock signals from the clock generator 103 over lines 115-1 to 115-/7. The multiplex waveform generators 114-1 to 114-/7 produce three separate waveforms at three 55 separate outputs, the three waveforms being for application to lines A1,A2 and A3 of each individual display device. These waveforms are fed via respective driver circuits 116-1 to 116-/7 to the A1, A2 and A3 inputs of each device within a display unit 117. 60 The clock pulse generator 103 is connected via a line 118 to a further multiplex waveform generator 119 which generates the four waveforms which are applied via a driver circuit 120 to lines B1, B2, B3 and B4 of the display unit 117, the lines B1, B2, B3 and B4 65 of each display device in the display unit 117 being serially connected.

In operation the characters to be displayed are encoded and fed to the input 100 and read into the shift register 101. If the encoded characters are presented in parallel form then a parallel input register will be used instead of the shift register 101. When a data word corresponding to a single character has been read into the shift register 101 a clock signal on line 102 causes the parallel outputs of the shift register 101 to be connected to inputs of the decoder 104 which converts the ASC II code to individual characters and causes one of the lines 106-1 to 106/7 to be activated to address the encoder 107. The individual characters are encoded by the encoder 107 into a code which indicates which of the twelve display elements are to be operated to form the character. The encoder 107 produces a twelve bit binary code for that purpose and this code is read into the register 109 under the control of clock signals from the clock signal generator 103 over the line 110. The output from the register 109 is fed under the control of further clock signals on line 110 to a selected one of the registers 111-1 to 111 -/7, the particular register being selected by an address generated in the clock signal generator 103. Normally the registers 111-1 to 111-/7 will be addressed sequentially whenever information to be displayed is changed and the addresses generated will allow for the display of blank characters e.g. to mark the end of complete words. For this purpose the address generator section of the display needs to have an indication of when a new character or set of characters is available and is/are to be displayed. This would be derived from the source of the characters, e.g. when push buttons are depressed or from outputs of a computer. It should be noted that the registers 111-1 to 111-/7 are only addressed when the information to be displayed is altered.

The outputs of the registers 111-1 to 111-/7 are connected to respective multiplex waveform generators 114-1 to 114-/7 which generate the waveforms required to drive the corresponding individual character display devices. These waveforms are generated with the aid of clock signals from the clock signal generator 103 which are conveyed to the multiplex waveform generators over the lines 115-1 to 115-/7. The multiplex waveform generators produce waveforms such as those shown in Figure 6f) to j), the precise waveform produced being dependent on the contents of the registers 111 associated with it. Each multiplex waveform generator 114 produces three separate waveforms which are for application to the A1, A2 and A3 lines of its associated display device via respective driver circuits 116.

A further multiplex waveform generator 119 generates the waveforms which are applied to the B1, B2, B3 and B4 lines of all the display devices in the display unit 117. The waveforms generated by the multiplex waveform generator 119 are not dependent on the character to be displayed and are generated with the aid of clock pulses fed from the clock pulse generator over the line 118. The signals produced by the multiplex waveform generator 119 are fed to the display unit 117 via the driver circuit 120.

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Figure 8 shows part of one of the multiplex waveform generators 114-1 to 1141 n each multiplex waveform generator comprising three of the circuits shown in Figure 8. As shown in Figure 8 a first 5 terminal 201 is connected to the first input of an AND gate 211 and to the first input of an AND gate 221. The output of AND gate 211 is connected to a control input of an analogue switch 231 while the output of the gate 221 is connected to a control input of an 10 analogue switch 241. The pole of switch 231 is connected to a first input 251 of a single pole eight way analogue switch 2.60 while the pole of switch 241 is connected to a second input 252 of the switch 260. Afirstterminal of switch 231 is connected to OV 15 while a second terminal is connected to 2V. Afirst terminal of the switch 241 is connected to 3V while a second terminal is connected to 1V. As can be seen from Figure 8 three further identical arrangements are provided to which input terminals 202,203 and 20 204 are connected and which are connected to inputs 253-258 of the switch 260. The pole 259 of the switch 260 is the output of the multiplex waveform generator and is connected to the line A1. The timing signals t.-| to t_8 are also connected to a control input 25 261 of the switch 260 and are operative to cause the pole 259 of the switch to be connected to selected inputs at the appropriate time, i.e. to input 251 during time t_i, to input 252 during time t_s and so on.

Thus to produce the waveform shown in Figure 30 6g) a logical 'V is applied to terminal 201 and a logical '0' to terminals 202,203 and 204. As a result of this the AND gate 211 produces a logical 'V at its output during the time t_i and causes the pole of switch 231 to be connected to OV. Hence OV is 35 applied to input 251 of the switch 260. During the period t_i the pole 259 of switch 260 is connected to input 251 and hence OV is applied to line A1. During the periods t.2 to t.4 the pole of switch 260 is connected to inputs 253,255 and 257 in turn. As the 40 inputs 202,203 and 204 are at a logical '0' the poles of switches 232,233 and 234 are all connected to 2V and hence during the periods t.2 to t.4 the line A1 carries 2V. Similarly during the period t_5 the pole of switch 241 carries 3V and hence this voltage is 45 transferred to the line A1 during the time t_5 but during the periods t.6 to t.8 the poles of switches 242 to 244 are connected to IV and hence line A1 is at IV from t.6 to t.8.

Similarly if a logical '1' is applied to terminal 202 a 50 voltage of OV will be applied to line A1 during the period t_2 and during the period t.6 a voltage of 3V will be applied to the line A1. The signal applied to terminal 203 will determine the voltages applied to line A1 during the periods t_3 and t.7 and the signal 55 applied to terminal 204 will determine the voltages applied to line A1 during the periods t_4 and t8.

To complete the multiplex waveform generators 114-1 to 114-/; two further identical arrangements are provided which produce the outputs for lines A2 60 and A3 from the other eight bits of information received from the registers 111-1 to 111 -/7, the arrangement shown using the first four bits from the respective register 111.

The multiplex waveform generator 119 which 65 provides the driving waveforms shown in Figure 6b)

to e) produces unchanging waveforms, i.e. waveforms which do not change with the characters to be displayed. Consequently the multiplex waveform generator 119 receives only a clock signal input and 70 not data inputs. The multiplex waveform generator 119 comprises four similar cirucits, the only difference between the circuits being the timing signals applied to them. The first circuit comprises two controlled single pole changeover switches 301 and 75 302 the switching of which is controlled by timing signals t_i and t_5 respectively. The poles of switches 301 and 302 are connected to first and second inputs of a further controlled single pole changeover switch 303, the pole of which is connected to line Bl.The 80 control input of switch 303 is connected to the output of an RS bistable circuit 304 which is set by the timing pulse t^ and reset by the timing pulse t_s.

In operation when the pulse t.i occurs switch 301 is set so that the movable contact connects the pole 85 of 3V and bistable 304 is set so that the pole of switch 303 is connected to the pole of switch 301. Consequently during the period t.-i 3V is applied to theline B1. At the end of the period tn the pole of switch 301 is connected to 1V but the state of switch 303 90 remains unchanged and hence 1V is applied to the line B1 until the start of the period t_5. At the start of the period t.5 the pole of switch 302 is connected to OV and the bistable 304 is reset thus causing the pole of switch 303 to be connected to switch 302. 95 Thus during the period t.5 OV is applied to the line B1. At the end of the period t_5 the pole of switch 202 is connected to 2V but the state of the switch 303 remains unchanged and hence 2V is applied to the line B1 for the periods t_6 to t_8. Consequently the line 100 B1 is at 3V during t.i, IV from t.2 to t.4,0V during t.5, and 2Vfrom t_6to t,8. Similarly switches 311,312 and 313, bistable 314, and timing pulses t.2 and t.6 produce the waveform on line B2; switches 321,222 and 323, bistable 314, and timing pulses t_3 and t_7 105 produce the waveform on line B3; and switches 331, 332 and 333, bistable 334, and timing pulses t.4 and t.8 produce the waveform on line B4.

The clock signal generator 103 comprises an oscillator and a number of divider and decoder 110 stages to produce the required timing and address waveforms. It is not necessary for the input data clocks, i.e. the clocking of shift register 101, register 109 and registers 111-1 to 111-/7 to be synchronised with the waveforms of the multiplex waveform 115 generators. The clock rate for the registers may be chosen to suit the speed of the technology chosen to implement them and the rate at which the character data is applied. Clearly if the character data is received serially the shift register 101 must be 120 clocked at the data rate. Similarly there must be external inputs to the clock signal generator to enable the appropriate counters or registers to be reset when new display information is to be received so that the information can be routed to the approp-125 riate display device.

The switches shown in Figures 7 and 8 are in the form of solid state switches which may take different forms dependent of the technology used to produce the display arrangement, e.g. bipolar or MOS inte-130 grated circuits using small, medium or large scale

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integration. Such switching arrangements are well known to those skilled in the art.

The form of the display devices shown in Figures 1 and 4 enables a full alpha numeric character set to be 5 displayed while reducing the number of connections required to the display device compared with the conventional 14 element display orthe 5 x 7 dot matrix display. In particular the number of connections to a 16 character display is reduced from 68 to 10 52. Further the display information required to be stored is reduced by approximately 14%. When producing a display arrangement in the form of an LS1 circuit in combination with the display unit a significant overall saving in chip area can be 15 achieved together with a reduction in the number of pins in the package leading to a less expensive total system.

While the detailed embodiment has been described with reference to display devices of liquid 20 crystal from any other form of display element could be used though the driving circuitry would be re-designed to suit the characteristics of the particular display device. The advantage of fewer connections and a smaller quantity of stored information 25 required would still exist. A standard 14 segment display could be used with the driving arrangement described by connecting together the two elements which correspond to each of the elements 2 and 6.

Claims (7)

30 CLAIMS

1. An alpha numeric display device comprising a plurality of elongate elements arranged to form a cross and a diagonal cross within a parallelogram 35 characterised in that single elongate elements form three sides of the parallelogram, that a single elongate element forms the arm of the cross between the two opposite sides of the parallelogram formed by single elongate elements, that the other 40 side of the parallelogram is formed by two serially arranged elongate elements, that the other arm of the cross is formed by two serially arranged elongate elements, and that both arms of the diagonal cross are formed by two serially arranged elements. 45

2. A device as claimed in Claim 1, characterised in that one or more of the single elongate elements is/are formed by two serially arranged elongate elements which are connected together so that a single driving signal operates both elements simul-50 taneously.

3. A device as claimed in Claim 1 or 2, in which the elongate elements are formed by liquid crystals and means are provided for selectively applying electrical signals to each element.

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4. An alpha numeric display device substantially as described herein with reference to Figures 1 to 3 or to Figures 2 to 4 of the accompanying drawings.

5. A visual display arrangement for displaying a plurality of alpha numeric characters comprising a

60 plurality of display devices as claimed in any of Claims 1 to 4 in which the display devices are driven in a time division multiplexed form.

6. An arrangement as claimed in Claim 5, characterised in that each display device is electrically

65 arranged as a four row by three column matrix, that electrical driving signals are applied to the four rows of each display device simultaneously from a common source, and that the electrical driving signals applied to the three columns of each display device 70 are generated from separate information sources.

7. A visual display arrangement for displaying a plurality of alpha numeric characters substantially as described herein with reference to the accompanying drawings.

Printed in the UK for HMSO, D8818935,7/84,7102.

Published by The Patent Office, 25 Southampton Buildings, London,

WC2A1 AY, from which copies may be obtained.