GB2133641A - AC solid state relay circuit and thyristor structure - Google Patents

Abstract

The relay has two separate and identical power thyristors 210 and 211 connected in anti-parallel arrangement. The powerthyristors are each optically switched, lateral conduction devices and both are switched by illuminating their surface by reflected illumination from an LED 225. Each thyristor is provided with a respective control circuit which includes a MOSFET transistor 230-231, for clamping its respective thyristor gate whenever the voltage across the thyristor exceeds a given absolute value or whenever there is a high dV/dt transient across the thyristor. The control circuit for the control transistor includes a capacitance divider 236-239, one element of which is the distributed capacitance 238, 239 of the control transistor; a resistor 234, 235 and a zener diode 232, 233. The control circuit components may be integrated into the thyristor chips. Each of the two identical power chips and the LED chip are spaced from one another and mounted on an alumina substrate. <IMAGE>

Description

SPECIFICATION A.C. solid state relay circuit and thyristor structure Background of the invention This invention relates to a.c. solid state relays, and to a novel thyristor which can be used in a solid state relay.

Solid state a.c. relays are well known. Such relays, with optical isolation between input and output, are also well known. In existing devices, many discrete components are commonly required to complete the a.c. circuit. Thus, it may take thirty or more discrete thyristors, transistors, resistors and capacitors to manufacture a single device. Attempts have been made to integrate the various parts of the entire solid state relay, but these have met only limited success due to the mix of high voltage and high power components.

Solid state relays made in the past have also employed zero voltage crossing circuits to ensure turn on of the thyristor only when the a.c. voltage is within some small "window". These circuits have also been relatively complex and difficult to integrate into the main power chip. Thus, zero cross firing circuits have required the use of a discrete resistor connected across the power terminals. These resistors have not been easily integrated into a single chip because of the difficulty of forming this resistor on the chip surface.

It has also been difficult to provide so-called "snubberless"operationfortherelayunderanyindu- tive or resistive load. Thus, while solid state relays may operate well under resistive or slightly inductive loads, they may tend to "half wave" or "chatter", which is a condition wherein a relay turns on only for one-halfofa cycle, under a highly inductive load. This has occurred in the past because the relays are commonly provided with conditioning circuits for suppressing fast turn on of the circuit under some fast transient or high dV/dt condition. When the device is operated under a very highly inductive load, however, voltage transients are commonly generated repetitively during device turn on.When the signal conditioning circuit misinterprets this as a transient signal, it shuts offthe power output during a particular half phase of the operation. The circuit will then appear to turn to normal during the next half wave and the relay will turn on. This condition repeats so that the relay turns on only during one or another of the half waves of the full cycle. To avoid this condition, relays of the past have been formed with reduced firing sensitivity and this has required reduction of sensitivity to optical firing.

Since prior art relays have been relatively complex, they have required substantial volume for their housings. Moreover, solid state relays of the past have been limited to a maximum temperature rise of about 1 0 C., thus limiting their current-handling capability.

Finally, solid state relays of the past have been relatively expensive in view ofthe need for large numbers of discrete components and large housings.

Optically fired lateral thyristor devices which can be used alone or in such relays are also known. Such devices, however, are expensive and have a relatively high forward drop and are relatively insensitive to input radiation. One thyristor device of this type is shown, for example, in U.S. Patent 4,355,320, dated October 19, 1982, entitled LIGHT-CONTROLLED TRANSISTOR.

A first aspect of the present invention provides a solid state a.c. relay comprising first and second thyristors each having respective anode and cathode electrodes and a respective gate circuit, characterized in that each of said thyristors is formed in separate respective first and second semiconductor chips and is ofthe lateral conductivity type, wherein said anode and cathode electrodes of each of said thyristors are on the same first surface of their said first and second chips respectively; said first surface of said first and second chips being optically sensitive, whereby said first and second chips can be switched to conduct current by illuminating said one surface; said solid state relay further comprising a light emitting diode arranged to illuminate said first surfaces upon its energization; a pair of a.c. terminals; said anode and cathode electrodes of said first and second thyristors connected to said pair of a.c. terminals and in antiparallel relation with one another; a pair of control terminals insulated from said a.c. terminals and connected to said light emitting diode; and first and second control circuits connected to said gate circuits of said first and second thyristors respectively for clamping said first and second gate circuits respectively to prevent firing of said first and second thyristors when the voltage between said pair of a.c. terminals exceeds a given value and for clamping said first and second gate circuits in response to transient pulses having a dV/dt greater than a given value.

A second aspect of the present invention provides a lateral thyristor which is optically fired, comprising a chip of semiconductor material having a junctionreceiving surface of one conductivity type; an anode region of the other conductivity type and a base region of said other conductivity type each formed into said surface and laterally spaced from one another; characterized by an emitter region of said one con ductivitytype formed in and totally contained within said base region and extending therein from said surface; anode and cathode electrodes connected to said anode and emitter regions respectively and radiation means for illuminating at least a portion of said surface for turning on said thyristor; and an auxiliary region of said other conductivity type formed in said surface and laterally spaced from and surrounding said base region.

A third aspect of the present invention provides an optically triggered thyristor comprising a semiconductor substrate of one of the conductivity types, characterized in that said substrate has at least first and second spaced, parallel base regions ofthe other of the conductivity types extending into the surface of said substrate; respective emitter regions of said one of said conductivity types extending into said surface of at least first and second parallel base regions and being completely contained within their said respective base regions; respective elongated anode regions of said other of said conductivity types extending into said substrate and disposed on opposite elongated sides of and laterally spaced from each of said parallel base regions and extending at least coextensively with said base regions; an anode contact connected to said anode regions; a cathode contact connected to said emitter regions; and radiation generating means energizable to generate minority carriers in said substrate which act as a base drive to turn on said thyristor when appropriate bias voltages are applied to said anode and cathode contacts.

Brief description of the invention In accordance with the present invention, two identical and novel thyristor power chips are provided for an a.c. relay wherein the power chips are both of lateral construction with both cathode and anode electrodes at one surface of each device and wherein each of the chips can be optically fired and has an optically sensitive upper surface which, when illuminated, will permit the device to become conductive between its anode and cathode electrodes.

The gate circuit of each of the thyristors is connected to a novel control circuit, formed either of discrete components or of components merged within the body of the semiconductor material forming the thyristor. The control circuit is operable to prevent turn on, even though the surface is illuminated, when the voltage across the device exceeds a value greater than some predetermined window value, or when high dV/dt transients appear across the device. This control circuit includes a clamping transistorwhich can be turned onto clampthe gate of its respective thyristor and a capacitive divider circuit connected across the main power electrodes. The capacitive divider applies a control signal to the control transistor.

One of the capacitors of the capacitive divider includes the distributed capacitance of the control transistor. So long as the control transistor is on, its respective power thyristor cannot turn on even though its surface is illuminated. The capacitive divider is arranged so that the control transistor is normally turned on for all absolute voltages across the main device greater than some relatively small window value. Thus, the power thyristor cannot turn on outside of this small window value or zero cross value.

The novel capacitance divider, in combination with the control transistor, will now operate to suppress both fast transients and still allow the device to function under its normal load condition. Thus, voltage transients which are generted repetitively during device turn on under highly inductive load conditions will not be misinterpreted as a fast transient and the powerthyristorchipwill be permitted to turn on in its normal manner under even highly inductive loads.

The novel signal conditioner of the invention also allows for substantial improvement in optical sensitivity of the device without misfiring. Note that currently available optically isolated triac drivers and the like are always limited either in dV/dt capability or optical sensitivity because of their inability to separate low level command signals from transients.

A novel housing is provided for the two chip arrangement in which the two chips are easily and inexpensively connected in parallel with one another and are protected from the outer environment. An alumina substrate or other suitable heat conductive but electrically insulative substrate is provided with suitable conductive patterns thereon for receiving the various chips of the switch and for connecting the chip electrodes to suitable output leads. The two identical thyristor chips which are to be connected in anti-parallel are symmetrically secured to respective conductive pads on the substrate and are in alignment with one another and with the terminal ends of two conductive patterns on the substrate.Two continuous wires are then stitch-bonded to the thyristor pads and conductive leads in such a manner that one lead wire is electrically connected to the anode pad of one chip, the cathode pad ofthe second chip and one of the conductive patterns which is connected to an input a.c. lead. The other wire is similarly connected to the other electrodes and conductive pattern to conduct the thyristors in anti-parallel.

A small LED chip is also connected to the alumina substrate at the same time the power chips are connected. The LED is connected appropriately to two input leads which are well insulated from the a.c.

ouput leads.

A plastic cap covered by a white illumination reflected material then is secured to the substrate and covers the region of the substrate containing the LED and the two power chips. The cap may consist of a transparent silicone which encloses and encapsulates the surfaces of the chips and their interconnecting leads with a white silicone painted outer surface.

If the control circuitforthe powertransistoris car- ried out in discrete form, the discrete components may also be suitably connected to this substrate. Preferably, however, these components are integrated into the individual power chips so that the entire solid state relay will consist of two power chips and their controls, the LED chip and the various support structures previously described.

Each thyristor of the relay has a novel structure and is formed in a single chip which has a low forward voltage drop and a relatively high current capacity and is highly sensitive to input radiation so that a noncritical LED triggering source can be provided to cause the thyristor to conduct. The relay circuit control components including parallel connected control MOSFETs, a resistor, zener diode and capacitor may also be provided in the single chip. The relay control components permit thyristor turn-on only when the anode-to-cathode voltage is less than a given value.

Moreover, false turn-on due to a transient is prevented under all circuit conditions, if the LED is off.

In accordance with the invention, a plurality of individual lateral thyristors, each of which may be optically fired, are connected in parallel with one another within a single chip. Each lateral thyristor has a respective base with emitter elements formed in the base. A novel anode region consisting of a plurality of spaced anode region fingers which envelope the end and two sides of each base make parallel connection of the elements easily possible. The thyristor base zone contains spaced parallel emitter regions and the base zone is surrounded by an auxiliary P region. An auxiliary region for a lateral opticallytriggered thyris- tor is shown in US Patent 4355320.The novel auxili ary regions of the invention, however, loop around and fully enclose the individual base regions and are resistively connected to a conductive polysilicon field plate which is solidly connected to the metallic cathode electrode.

The novel resistive connection may be obtained by making spaced connections from the field plate to the auxiliary region. By using a resistive connection in this manner, more carriers which are injected from the anode region and which travel laterally toward the emitter will reach the emitter. This improves the forward drop of the device by a significant amount (for example, from 1.45 volts to 1.15 volts) which signficantly decreases power dissipation during the operation of the device.

In accordance with further features of the invention, the anode region may be relatively heavily doped in comparison to the emitter doping to further reduce the forward drop. The emitter doping concentration at the emitter region surface is also controlled to a point found to be optimum for improving injection efficiency. In particular, very good operation is obtained when using a surface concentration of 1 x 1020to6 > ( 1020 phosphorus ions/cc atthe emitter surface.

Finally, in making the surface contacts for the device, thin lines of relatively thick aluminum are used to expose a maximum amount of silicon.

Brief description of the drawings Figure 1 is a cross-sectional view of the junction pattern of a single lateral thyristor which employs some features of the present invention.

Figure 2 is a plan view of the metallizing pattern on the surface of a single chip which employs the lateral thyristor of the present invention.

Figure 3 is a plan view of the silicon surface of the chip of Figure 2 and shows the junction patterns which come to the device surface.

Figure 4 is an enlarged view of one of the parallel elements or loops of figure 3.

Figure 5 is a cross-sectional view of Figure 3 taken across the section line 5-5 in Figure 3.

Figure 6 is a cross-sectional view of Figure 4 taken across section line 66 in Figure 4.

Figure 7 is a cross-sectional view of Figure 3 taken across section line 7-7 in Figure 3.

Figure 8 is a cross-sectional view of the polysilicon resistor which is shown in Figure 3.

Figure 9 is a circuit diagram of the thyristor and its control circuit as produced by the junction pattern and interconnections of the device of Figures 2 through 8.

Figure 10 is a circuit diagram of the novel a.c. relay of the present invention.

Figure 11 illustrates the two power thyristor chips of Figure 10 and an LED mounted on a ceramic substrate.

Figure 12 is a side view of Figure 11.

Figure 13 is an elevation view of the assembly of Figure 11 with an enclosing capforenclosing the LED and power chips.

Figure 14 is a top view of Figure 13.

Detailed description of the drawings Referring first to Figure 1, there is shown therein in cross-section the junction pattern and metallizing of a lateral thyristor chip which is manufactured in accordance with some of the principles of the present invention. The chip containing the lateral thyristor of Figure 1 can have any desired size and configuration, and is a chip of mono-crystalline silicon.

The various junctions shown in Figure 1 are formed in N(--) layer 20. Layer 20 may have a resistivity of about 20 ohm-centimeters. Spaced Ptype regions 21, 22 and 23 are formed in the upper surface of chip 20 by any desired process. A further P type region 23a, which is inactive, may enclose the periphery of region 23. Regions 21, 22, 23 and 23a can be boron-diffused regions of sufficient concentration so that the sheet resistance of the P regions will be about 1,600 ohms per square at the chip surface. They may also be formed, for example, by an ion implantation and drive-diffusion process employing 5 x 103 boron atoms per square centimeter dose so that it is relatively lightly doped. Region 21 is preferably more heavily doped than the other P regions. Regions 21, 22, 23 and 23a may have the same depth of approximately 4 microns.P type region 23 contains an N(+) region 24 to complete the laterally spaced junctions of the lateral thyristor.

The facing edges of regions 21 and 23 should be as close together as possible while still being able to block a selected voltage. In the present application, the device preferably blocks about 400 to 500 volts and a spacing of 105 microns is used.

Region 21 istheanode region, region 23 isthegate or base region, region 24 is the emitter or cathode region while the N( - -) body 20 is the main blocking region ofthethyristorshown in Figure 1. Region 22 is a known type of floating guard region which permits an increase in the blocking voltage between junctions 21 and 23 to as high as 400 to 500 volts without danger of breakdown at the surface of the chip.

The upper chip surface is covered by a thin silicon dioxide layer 30 which can have a thickness, for example, of about 1 micron. Polysilicon field plates 31 and 32 are formed atop the oxide layer 30 as shown, using conventional polysilicon deposition and masking techniques. The entire upper surface of chip, including the polysilicon field plates, and the oxide 30 is covered with a conventional glassy, phosphorus doped silicon dioxide layer35. Spaced gaps 36 and 37 of known structure may be placed on either side of the floating guard region 22 to prevent lateral polarization effects within the phosphorus doped oxide layer 35 from interfering with the field distribution at the surface of region 20 adjacent the floating guard region 22.

Suitable openings are formed in the oxide layers 30 and 35 above emitter region 24 and anode region 21 to permit contact to the various regions and field plates. Thus, aluminum cathode electrode 40 and anode electrode 41 are applied to emitter region 24 and anode region 21, respectively, as shown. Other openings which are formed in the oxide layer 35 permit connection from the cathode 40 to the field plate 31 and from the anode 41 to the field plate 32. Both cathode electrode 40 and anode electrode 41 are rela tively thin and can, for example, be about 4 microns in thickness.

Region 23a is preferably resistively connected to the cathode 40. Thus, region 23a can be connected to cathode 40 only at spaced points along their peripheries.

The lateral thyristor of Figure 1 is turned on by injection of carriers from emitter region 24 into gate region 23. Suitable injection can be obtained by applying radiation to the upper surface of the device which will generate carriers (holes) in the body 20.

These holes drift to region 23 and are collected by the emitter junction between regions 23 and 24to act as a base drive to turn the device on. A suitable source of radiation can be the schematically illustrated LED 45 which is arranged to illuminate the surface of the device.

It has been found that a device employing the structure of Figure 1 is capable of blocking from 400 to 500 volts. During forward conduction, the forward voltage drop was about 1.15 Volts at about 1.5 amperes forward current.

The arrangement of the lateral thyristor of Figure 1 can be implemented in any number of desired geometries. A particularly efficient geometry is that disclosed in Figures 2 to 9 which are now described and show an arrangement in which a plurality of devices, such as that of Figure 1, are connected in parallel.

Referring to Figures 2 and 3, there is shown a plan view of a single chip containing a single thyristor device and its control circuit components. The chip of Figures 2 and 3 is one of a large number of chips on a common wafer which are separated after common processing is completed. The chip is shown in Figure 2 after metallizing of the cathode and anode terminal electrodes.The junction patterns on the chip surface are shown in Figure 3.As will be described in detail, a plurality ofseparate thyristor elements are connected in parallel, using novel junction patterns for the anode, base and emitter regions (Figures 3 and 4) which extend along a path hereinafter designated either a serpentine or interdigitated path, so that they will have the longest possible length, thus permitting a a high current capacity for the device.

In the embodiment of Figures 2 and 3, the chip may have a width of 82 mils, a length of 113 mils and will have a forward current-carrying rating of 1.5 amperes with a 1.15 volts forward voltage drop. The bisymmetrical blocking voltage capability of the device is about 500 volts peak. Therefore, the thyristor chip of the invention can be employed with an identical anti-parallel connected thyristor chip and used in a solid state relay for controlling an a.c. circuit which might have an RMS voltage of up to 280 volts.

The basic metallizing pattern of Figure 2 employs the cathode 50 and anode 51 configured as shown. A control circuit, not shown in Figure 2, is contained within the chip body. The circuit is shown in Figure 9.

Metallized sections 60 and 61 in Figure 3 are electrodes oftwo respective capacitors shown in Figure 9.

Capacitor 60 will be described later in connection with Figure 7.

The capacitors including electrodes 60 and 61 are connected in parallel as shown in Figure 9 and are connected between the anodes ofthyristors 64a, 64b, 64c and 64d and gates of control MOSFETS 76,77,78 and 79, respectively. Thyristors 64a, 64b, 64c and 64d are in parallel and have common cathodes and anodes, shown as cathode 50 and anode 51 in Figures 2 and 6.

Also provided integrally with the chip of Figure 3 is a 100 K resistor 70 which is formed of polysilicon and is electrically connected between the cathodes and gates of each of thyristors 64a, 64b, 64c and 64d. The detailed structure of resistor 70 will be later described in connection with Figure 8.

Additionally provided and formed integrally in the chip of Figure 3 is a zener diode 71 which, as shown in Figure 9, is connected in series with capacitors 60 and 61 between the anode and cathode terminals 51 and 50 of the thyristors shown. There is also shown in Figure 9 an inherent distributed capacitance 75 in parallel with zener diode 71.

The zener diode 71 may be formed in the inactive P region 82 and can consist ofthe N+ region 71 a shown in Figure 3. One zener terminal 71 b may be formed directly atop the N + region 71 a, and the other terminal may be formed of a metal contact 71c which is connected to the cathode electrode.

A plurality of control MOSFETs 76, 77, 78 and 79, shown in Figure 9, and which will be later described in Figures 3 and 4, are also contained on the chip and operate with thyristors 64a, 64b, 64c and 64d, respectively. Each control MOSFET is disposed immediately adjacent its respective main thyristor element so that operational delay times are limited and circuit symmetry is assured.

The circuit of Figure 9 is implemented in a novel way, as will now be described in connection with Figures 2 to 8. Note that, while the embodiment disclosed herein uses four parallel thyristor elements 64a, 64b, 64c and 64d, any desired number of elements could be used.

Referring to Figures 3 to 6, the entire integrated device is formed in a relatively high resistance N(- -) substrate 80 which can have a resistivity of about 20 ohm-centimeters.

A number of individual Ptype regions are formed in substrate 80 by any desired process. The first ofthese is the P+ type anode region 81 which corresponds to anode region 21 in Figure 1. As shown in Figures 3 and 4, anode region 81 has main body section from which three parallel fingers 81 a, 81 b and 81 c extend.

Figures 81a and 81b are shown in more detail in Figures 4 and 6.A rectangular anode region frame having legs 81 d, 81 e and 81f surrou nds the periphery ofthe chip as shown in Figure 3. Legs 81 d and 81 e are seen in Figure 5.

The second P type region shown in Figures 3 to 8 is "inactive" P type auxiliary region 82. Inactive region 82 has loop sections 82a, 82b, 82c and 82d (Figure 3), which enclose the bases of four respective thyristors as will be later described and serve the purpose of auxiliary ring 23a of Figure 1. Loop section 82b is shown in Figure 6.

Fourequallyspaced, elongated Ptype base regions 83a, 83b, 83c and 83d (Figures 3, 4 and 6) are also formed in region 80. These base regions correspond to the base region 23 in Figure 1. Base region 83b is shown in enlarged detail in Figure 4. Note that the base regions 83a, 83b, 83c and 83d are almost fully enclosed by auxiliary ring loops 82a, 82b, 82c and 82d, respectively.

A further P type region is formed, consisting of a floating guard ring 84, shown in Figures 3to 6. Guard ring 84 follows a sinuous path and divides in half the N(- -) region 80 which reaches the device surface in Figures 3 and 4.

Each of the thyristor bases 83a, 83b, 83c and 83d receives two parallel N+ emitter regions 85a-85b, 86a-86b, 87a-87b and 88a-88b, respectively (Figures 3,4 and 6). Emitter regions 86a and 86b are shown in enlarged detail in Figure 4.

From the above, it will be seen that the junction pattern in Figure 3 forms the basis for the four thyristor elements 64a, 64b, 64c and 64d of Figure 9 and makes possible the parallel connection ofthedevices.

The thyristor element defining thyristor 64b is shown in Figures 4 and 6 and is now described. The thyristor base consists of active P region 83b containing parallel emitter regions 86a and 86b. Thethyristor anode region is comprised of the anode region fingers 81a and 81b which symmetrically enclose the base 83b. The thyristor body consists of the N(--) region 80. The base is also almost completely surrounded by auxiliary loop region 82b which has the benefit previously described of increasing collection efficiency. The novel junction pattern also makes possible the parallel connection of he plural thyristors on the chip.

In forming the junction pattern shown, the lateral spacing between the confronting edges of base regions 83a, 83b, 83c and 83d and the respective adjacent anode fingers 81a, 81b and 81c (and the outer anode legs 81d and 81e) was about 105 microns. The depth of each of the P type regions was about 4 microns.

Each of base regions 83a, 83b, 83c and 83d had a length of about 40 mils and a width of about 75 microns.

During the formation of the various P regions, a further P type guard ring 90 (Figures 2 and 5) is preferably formed around the periphery of the chip. Ring 90 is spaced from the outer periphery ofthe P + anode 81e by about 38 microns.

Also during the formation of the various junctions, and as shown in Figures 3 and 4, N(+) source and drain regions 91a-91b, 92a-92b, 93a-93b and 94a-94b are formed for the control MOSFETs 76, 77, 78 and 79, respectively, in Figure 9. These are formed in the enlarged inactive Ptype region 82. As is shown in Figure 4 for the case of control MOSFET 77, a suitable gate oxide having a thickness of about 0.1 micron, and a polysilicon gate electrode (not shown) are arranged over the gap between regions 92a and 92b. An extremely thin oxide can be used for the control MOSFETs because the gate is at the potential of the node between capacitors 60 and 61 and capacitor 75. Thus, the potential difference between the control MOSFET gates and the cathode of the main thyristors is very low. Therefore, transistors 76 to 79 can be very high gain transistors.

The source region 92a is connected to the inactive base, while drain region 92b is electrically connected to the thyristor base region 83b through the conductive strip 95 (Figures 4 and 6). Strip 95 is preferably metal. A similar arrangement is provided for each of the thyristor elements with a conductive strip connecting bases 83a, 83b, 83c and 83d to control MOS FET source electrodes 91 b, 92b, 93b and 94b, respectively. The conductive strips are then all connected together as by a polysilicon connection strip, partly schematically shown in Figure 4 by dotted line 95a.

Capacitors 60 and 61 are also implemented in the inactive P region 82 as shown in Figure 7 for capacitor 60. Thus, capacitor 60 is formed by depositing a metal layer atop an area of the P type base 82 which is isolated from the chip by causing a rectangular ring 96 having appropriately radiused corners and of the N(- -) material 80 to reach the chip surface. Note that the metal layer 60 overlies thermal oxide layer 97 to form a field plate.

The resistor 70 is also implemented in inactive P type region 82 as shown in Figure 8. Thus, in Figures, a polysilicon strip 70a is deposited atop oxide layer 97 and is overcoated with a deposited silicon dioxide layer 98. Therefore, resistor 70 is formed of a resistive layer which is completely insulated from the chip body by insulation layer 97. The resistor is thus an ideal resistor which will be free of parasitic interaction with other circuit components. Openings are then formed in layer 98 and resistor terminal connections 99 and 100 are made to the resistor. These terminals are appropriately connected to the thyristor cathode and to the source electrodes of control MOSFETs 76, 77, 78 and 79.

The upper surface of the chip shown in Figures 5 and 6 is further processed to have the desired metallizing. Before metallizing, an appropriate thermal oxide 110 exists in place, or is applied to the device surface to a thickness of about 1 micron. After conventional masking and etching steps, metals are applied in the necessary sequence. The upper surface is then covered with a deposited oxide coating 111 which may have any desired thickness.

Novel polysilicon field plates 112 and 113 are deposited on the thermal oxide 110. Note that all polysilicon strips or layers may be deposited in any desired sequence.

Field plate 112 is an elongated, sinuous plate which is disposed atop and follows the path of the junction between P(+) anode region 81 and N(--) region 80.

Field plate 113 similarly is an elongated, sinuous plate which follows a path parallel to that of plate 112 and overlies the junction between auxiliary region 82 and the outwardly disposed N(--) region 80.

At the time field plates 112 and 113 are deposited, an outer equipotential ring 115 (Figure 5) may also be disposed around the outer periphery of the chip. Ring 115 is connected to substrate 80 in the usual manner.

Each of field plates 112 and 113 and ring 15 may have a width of about 20 microns. The guard ring region 84 may have a width of 8 microns and is centrally located between the opposing edges of plates 112 and 113 which edges are about 44 microns apart.

Similarly, P type region 90 (Figure 5) is centrally located between plates 112 and 115, the edges of which are about 44 microns apart.

The anode electrode 51 is then formed as shown and engages the P type anode region 81, as shown in Figures 2 and 6. Cathode electrode 50 is also formed as shown in Figures 2, 5 and 6.

The lateral thyristor of Figures 2 through 9 is turned on by radiation from LED 45 (Figures 6 and 9) which is arranged to illuminate the exposed surface of the chip. Since the chip is extremely sensitive, the LED 45 is not critical in size, output or location.

The patterns described in Figures 2 through 8 will form the electrical circuit shown in Figure 9 and define one-half of the solid state relay which is later described. Turn-on of the thyristor is clamped against firing by transients when no light is present. Voltage division obtained between capacitors 60-61 and 75 defines the voltage window at which turn-on is possible. Significantly, the capacitive voltage divider permits a very low gate voltage for the control transistors and very low function leakage current. The capacitors also provide shielding from input light or radiation.

The novel lateral thyristor shown in Figures 2 to 8 can be made by any desired process. The device provides a maximum effective current carrying area between the anode region 81 and the base region 83 for a given chip area. The pattern configuration is also arranged to reduceforwardvoltagedroptoas large a degree as possible while maintaining high light sensitivity so that the LED 45 is not critical.

A significant feature of the novel geometry is the novel P type auxiliary regions 82a, 82b, 82c and 82d which loop around each base region 83a, 83b, 83c and 83d, respectively. This geometry makes it possible to connect together all N + cathodes. Thus, regions 82a, 82b, 82c and 82d and main region 82 are constant potential regions in which all thyristor bases are embedded. By spreading out into region 82 at the ends of the bases, a large area is made available for metallizing to connect regions in parallel.

Preferably, a resistive connection is made from the cathode 50 to the loops 82a, 82b, 82c and 82d as by using spaced dot type connections, schematically shown as connection points 120 in Figure 4, extending along the length of the P type loop 82b. The connection can also be made by a short contact strip 121, shown in Figure 4. By using a resistive connection between the auxiliary loops and the cathode electrode 50, and as shown in Figures 4 and 6, carriers which are injected from the anode regions 81a and 81 b during turn-on of the device will tend to move to the emitter regions 86a and 86b rather than being collected by the auxiliary regions 82a, 82b, 83c and 82d. This increases the collection efficiency of the emitter and substantially decreases the forward voltage drop of the device.By way of example, by making the resistive connection between auxiliary loop regions and cathode 50, the forward voltage drop at 1.5 amperes forward current was reduced from about 1.45 volts to about 1 .l5volts. This results in a signific- ant reduction of power dissipation during forward conduction.

During processing of the device of Figures 3 to 6, the anode region 81 and all its segments are preferably heavily doped as compared to the doping of P type regions 82,83 and 84. Byway of example, anode region 81 can be doped to the point where it has a resistivity of 50 ohms per square as compared to 1600 ohms per square for regions 82,83 and 84. This sets a high gain and thus high light sensitivity for the inherent lateral transistor consisting of regions 81,80 and 83. Furthermore, by more heavily doping the anode region, the forward voltage drop of the device is reduced.

A further important feature of the invention lies in the control of the doping of the emitter regions, such as regions 86 and 86b in Figures 3 and 6, so thatthe N type concentration at the surface ofthe device is atan optimum value of 1 > < x 10 21002 to 6 x 102 phosphorus ions/cc. This can be done as by diffusing phosphorus through a thin oxide during the formation of the regions 86 or by control of the various gas flows during the diffusion process. By reducing the N type concentration at the surface of regions 86, the injection efficiency of the device is improved, thus further reducing the forward voltage drop and substantially increasing the sensitivity of the device to turn-on by photons from the source 45.

Referring next to Figure 10, there is shown a circuit diagram ofthefull a.c. relay of the present invention.

The relay of Figure 10 employs two identical thyristors 210 and 211 connected in anti-parallel relationship with respect to one another between main a.c.

power terminals 212 and 213, respectively. Schematically illustrated thyristors 210 and 211 are each ofthe type shown in Figures 1 to 9 and are provided with gate circuits schematically illustrated by the gates 216 and 217, respectively. Thyristor chip 210 has, on its upper surface, anode electrode pad 220 and cathode electrode pad 221, while chip 211 has an identical anode pad 222 and cathode pad 223 (Figure 11).

Thyristors 210 and 211 are electrically connected together so that anode 220 of one is connected to cathode 223 ofthe other and so that anode 222 of one is connected to cathode 221 of the other. Thus, the devices are connected in the anti-parallel relationship shown in Figure 10.

A single LED 225, which can be a conventional commercially available gallium aluminum arsenide device having terminals 226 and 227 in Figure 10, is arranged as will be later described to flood the photosensitive surfaces of chips 210 and 211 in order to permit turn on of the chips if other circuit conditions are appropriate. Good electrical isolation is provided between the input circuit connected to terminals 226 and 227 and the a.c. power circuit connected to terminals 212 and 213.

Identical control circuits such as those described previously are provided for controlling the turn on of thyristors 210 and 211 respectively and include respective MOSFET transistors 230 and 231, zener diodes 232 and 233, resistors 234 and 235 and capacitors 236 and 237. Capacitors 236 and 237, like capacitors 60and 61 ofFigurn# serve as one component of respective capacitive dividers. The second component of the capacitive dividers consists of the distributed capacitance 238 and 239 of devices 230 and 231, respectively.

The circuit components 230-239 could be implemented as discrete components. Preferably, however, these circuit components are implemented integrally with the semiconductor chips defining thyristors 210 and 211, as described in connection with Figures 1 to 9.

Transistors 230 and 231 are connected to the gates 216 and 217 of thyristors 210 and 211, respectively. So long as transistors 230 and 231 conduct, orare on, the application of illumination to the surfaces of devices 210 and 211 from LED 225 cannot turn on the device.

Transistors 230 and 231 will turn on when their respective gates 240 and 241 are appropriately charged to a suitable threshold voltage Vth. Thus, when the nodes 242 and 243 reach the threshold turn on voltage of transistors 230 and 231, respectively, and if suitable drain to source voltage is provided, the devices will conduct and clamp the respective gates 216 and 217 of thyristors 210 and 211.

The voltage at each of nodes 242 and 243, termed VO, will be Vo = VccCp/(Ci+Cp).

In the above, Vcc is the voltage across terminals 212 and 213, Cp is the capacitance of distributed capacitors 238 and 239, respectively, and Cl is the capacitance of capacitors 236 and 237, respectively.

From the above, it will be seen that the voltage Vo at nodes 242 or 243 will be greater than the threshold voltage of the transistors 230 and 231 when the instantaneous a.c. voltage between terminals 212 and 213 is more positive, or is more negative than some "window" value. Consequently, transistors 230 and 231 clamp thyristors 210 and 211 when this window voltage is exceeded. This arrangement then permits a zero detection circuit without requiring a resistor extending between the main terminals of the device.

The novel capacitive divider circuit is also useful in suppressing the firing of devices 210 and 211 due to fast rising pulses such as transient noise or high dV/dt signals. Such high transient pulses will apply a suitably high voltage across parasitic capacitances 238 and 239 that the transistors 230 and 231 respectively turn on to clamp its respective thyristor. Thus, the thyristorwill not be fired in response to fast rising transient pulses.

For relatively slow rising pulses, such as those produced by highly inductive loads connected to the relay terminals 212 and 213, these pulses will not be sufficiently fast to turn on the control transistors and unintentionally clamp the thyristors 210 and 211, thereby to avoid single phasing or chattering of the relay on highly inductive loads. Note also that this is accomplished without having to reduce the optical sensitivity ofthe device. Thus, the thyristors 210 and 211 can be designed to have optimum optical sensitivity for firing without concern for false operation by relatively slow rising transients.

A A further advantage of the circuit shown in Figure 10 is in the design of resistors 234 and 235. Thus, the temperature coefficient of the resistor is balanced against the sensitivity of its respective thyristor. That is, if the resistor has the usual negative temperature coefficient, it is possible that the resistor would clamp its respective controlled rectifier when hot. However, by balancing the resistance temperature coefficient of resistors 234 and 235, this clamping action can be avoided.

There is next described in Figures 11 to 14 a structurefor housingthe chips 210 and 211 and LED 225 of Figure 10. Referring first to Figures 11 and 12, there is shown a ceramic substrate support 260 which can be of alumina but may be of any desired electrically insulative, thermally conductive material. By way of example, the alumina slab 260 can have a thickness of 0.025 inch, a length of about 0.9 inch and a width of about 0.25 inch. A plurality of conductive patterns is formed on one surface of substrate 260, including patterns 261 to 267. Each of these patterns may be formed by gold plating onto the substrate where the gold plating has a thickness greater than about 150 microinches.Each of thyristor chips 210 and 211 is then suitably soldered or otherwise mounted down onto conductive pads 265 and 264, respectively, so as to be in good thermal contact with the alumina body 260. Each ofthe chips 210 and 211 may have a size of approximately 82 x 116 mils for a typically sized device. The LED chip 225 is mounted down on one end of conductive pattern 262.

Chips 210 and 211 are so mounted that their anode and cathode leads are generally in line with one another and with one end of conductive patterns 266 and 267. Consequently, one single wire 270 is conveniently used to electrically connect conductive pads 223 of thyristor 211 and 220 of thyristor 210 and the ends of conductive pattern 267. This can be done in a stitch-bonding process of relatively simple nature which lends itself to high speed automated techniques. Thus, a bonding head is simply brought down onto the wire 270 to electrically attach the wire at the three spaced points corresponding to the location of pads 223, and 220 and the end of conductor 267. In a similar manner, a second parallel wire 271 is stitchbonded to conductive pads 222, 221 and the end of conductive pattern 266. The stitch-bonding of conductor 271 is shown in Figures 11 and 12.Each of conductive wires 270 and 271 may be of aluminum wire having a diameter of about 6 mils.

As a result of the above, the power terminals 212 and 213 are connected to the thyristor devices 210 and 211 in Figure 11 in the manner shown in Figure 10 with the thyristors in anti-parallel relationship with respect to one another. Note that, since the chips 210 and 211 also contain their respective control circuits, the control circuits are also connected in place with this single stitch-bonding operation.

The LED 225 is shown disposed atop one end of conductive pattern 262 which is connected to lead 226. The other electrode of LED 225 is electrically connected to one end of conductive pattern 261 by the wire 280. Wire 280 which may be an extending lead of the LED 225 is bonded to the end of conductive pattern 261 in any desired manner.

Conductive pattern 261 is then electrically connected to spaced conductive pattern 263 either by the direct shorting connection of wire 281 or by a resistor 282. The selection of the shorting wire 281 or resistor 282 depends upon the power available at terminals 226 and 227 and the characteristics of the LED 225.

Wires 280 and 281 may be gold wires having diameters of about 1 mil. Notethatthe leads212,213, 226 and 227 extend from the periphery of substrate 260, to define a dual in-line pin type of package.

An optical cap or enclosure 291 is then placed atop the LED 225 and thyristors 210 and 211 and encloses the area shown in dot-dash lines 290 in Figure 11. The cap is shown in Figures 13 and 14 as cap 291 and may be composed of any desired reflective plastic material capable of withstanding the temperatures which are produced during device operation. A white coloured plastic has been used. The plastic selected may be disulphone. The plastic preferably is white so that light will reflect from its interior surface. The cap can also consist of a suitable silicone such as RTV having titanium oxide powder mixed therein. The titanium oxide powder uniquely remains in dispersion within the silicone. The mixture can be oven cured at about 115 C. for about 15 minutes.

The cap 291 has a sloped side 292 above the location of the LED 225 with this sloped edge tending to reflect light toward the region of the chips 210 and 211, as can be seen in Figure 13.

Cap 291 can be cemented in place, as shown in Figure 13 or if desired, can be arranged to overlap the substrate and snap over the substrate edge. A clear silicone is then loaded into the interior of cap 292 through the filling holes 293 and 294 of Figures 13 and 14in orderto completely encapsulate all ofchips 225, 210,211 and their connecting leads while permitting illumination from LED 225to reach the photosensitive surfaces of thyristor chips 210 and 211.

After the cap 291 is secured in place and filled with silicone, the entire substrate 260 along with the cap 291 can be mounted within a lead from which provides the leads 212,213,226 and 227. The device may then be completely housed within a molded housing which could, for example, be formed by a transfer molding process or the like. Leeds 212, 213, 226 and 227 will extend from the package to define a dual in-line pin package of relatively small size and volume. The device, however, will be capable of a continuous current rating of 1-1/2 amperes or greater at voltages of 240 volts a.c.

Although the present invention has been described in connection with a preferred embodiment thereof, many variations and modifications will now become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.

Claims (34)

1. A solid state a.c. relay comprising first and second thyristors each having respective anode and cathode electrodes and a respective gate circuit, characterized in that each of said thyristors is formed in separate respective first and second semiconductor chips and is of the lateral conductivity type, wherein said anode and cathode electrodes of each of said thyristors are on the same first surface of their said first and second chips respectively; said first surface of said first and second chips being optically sensitive, whereby said first and second chips can be switched to conduct current by illuminating said one surface; said solid state relay further comprising a light emitting diode arranged to illuminate said first surfaces upon its energization; a pair of a.c. terminals; said anode and cathode electrodes of said first and second thyristors connected to said pair of a.c.

terminals and in anti-parallel relation with one another; a pair of control terminals insulated from said a.c. terminals and connected to said light emitting diode; and first and second control circuits connected to said gate circuits of said first and second thyristors respectively for clamping said first and second gate circuits respectively to prevent firing of said first and second thyristors when the voltage between said pair of a.c. terminals exceeds a given value and for clamping said first and second gate circuits in response to transient pulses having a dV/dt greater than a given value.

2. The solid state relay of claim 1, wherein said first and second control circuits include first and second control transistors respectively, each having an output circuit and a transistor control circuit operable to switch its respective control circuit between a conductive and a non-conductive condition; and further comprising first and second capacitor dividers; said first and second transistor output circuits connected between said gate circuit and said anode electrode of its respective one of said first and second thyristors, whereby, when said first or second transistor output circuit is conductive,the respective one of said first or second thyristors cannot fire in response to illumination of its said first surface; said first and second capacitor dividers connected across said pair of a.c.

terminals and having respective nodes between capacitors connected to said control circuit of the respective control transistor, whereby the voltage at said nodes renders its respective transistor conductive so long as the voltage between said pair of a.c.

terminals exceeds a given value to prevent turn on of the respective one of said thyristors when the a.c.

voltage exceeds a given window voltage, and whereby fast rising transient pulses turn on said transistorsfortheirdurationto prevent turn on of said thyristors by transient high dV/dt pulses.

3. The solid state relay of claim 2, wherein said first and second control circuits are further character- ized in including first and second zener diodes respectively connected from said nodes of said first and second capacitor dividers respectively to the anode electrodes of said first and second thyristors respectively.

4. The solid state relay of claim 2 or 3, which is further characterized in including first and second resistors connected between said gate circuit of said first and second thyristors respectively to the anode electrode of said first and second thyristors respectively.

5. The solid state relay of claim 2, 3 or 4 wherein said first and second transistors are metal oxide semiconductors field effect transistors and wherein said transistor control circuits include the gate circuit of said transistors.

6. The solid state relay of claim 5, which is further characterized in that said second capacitor of each of said first and second capacitor dividers is the distributed capacitance of said first and second transistors respectively.

7. The solid state relay of claims 1 to 6, which further includes an electrically insulative but thermally conductive ceramic substrate for mounting said first and second chips and said light emitting diode; said first and second chips and said light emitting diode being fixed to the same surface of said substrate and spaced from one another; said optically sensitive surfaces of said first and second chips facing away from said substrate; said light emitting diode being in a position which enables illumination of said first and second chips by reflection of its light output from reflecting surfaces.

8. The solid state relay of any of claims 1 to 7, which is further characterized in that said first surface of each chip constitutes a junction-receiving surface of one conductivity type; an anode region ofthe other conductivity type and a base region of said other conductivity type each formed into said surface and laterally spaced from one another; an emitter region of said one conductivity type formed in and totally contained within said base region and extending therein from said surface; said anode and cathode electrodes connected to said anode and emitter regions respectively; said anode region being more heavingly doped than said base region in order to reduce forward voltage drop and increase light sensitivity.

9. The solid state relay of any of claims 1 to 7 which is further characterized in that said first surface of each chip constitutes a junction-receiving surface of one conductivity type; an anode region of the other conductivity type and a base region of said other conductivity type each formed into said surface and laterally spaced from one another; an emitter region of said one conductivity type formed in and totally contained within said base region and extending therein from said surface; said anode and cathode electrodes connected to said anode and emitter regions respectively; said emitter region being relatively lightly doped at said surface to a level which would be obtained by diffusion through a thin oxide layer in order to increase the radiation sensitivity of said lateral thyristorto turn on by radiation from said radiation means.

10. The solid state relay of claim 8 or 9 which further includes a guard ring of said other conductivity type formed into said surface and disposed between and laterally spaced from said anode and base regions; said guard ring being out of contact with said cathode and anode electrodes and floating electrically with respect to said electrodes.

11. The solid state relay of any of claims 1 to 7 which is further characterized in that said first surface of each chip constitutes a junction-receiving surface of one conductivity type; an anode region of the other conductivity type and a base region of said other conductivity type each formed into said surface and laterally spaced from one another; an emitter region of said one conductivity type formed in and totally contained within said base region and extending therein from said surface; said anode and cathode electrodes connected to said anode and emitter regions respectively; and an auxiliary region of said other conductivity type formed in said surface and laterally spaced from and surrounding said base region.

12. The solid state relay of any of claims 8 to 11 which is further characterized in that said base region has an elongated shape terminating at said surface; said emitter region comprising at least one elongated rectangular shape contained within said base region; said anode region having a digitated pattern, the fingers of which envelope said base region.

13. The solid state relay of claim 11 which is further characterized in including means for resistively connecting said auxiliary region to said cathode electrode.

14. A lateral thyristor which is optically fired, comprising a chip of semiconductor material having a junction-receiving surface of one conductivity type; an anode region of the other conductivity type and a base region of said other conductivity type each formed into said surface and laterally spaced from one another; characterized by an emitter region of said one conductivity type formed in and totally contained within said base region and extending therein from said surface; anode and cathode electrodes connected to said anode and emitter regions respectively and radiation means for illuminating at least a portion of said surface for turning on said thyristor; and an auxiliary region of other conductivity type formed in said surface and laterally spaced from and surrounding said base region.

15. The thyristor of claim 14 which is further characterized in that said anode region is more heavily doped than said base region in orderto reduce the forward voltage drop and increase light sensitivity.

16. The thyristor of claim 14 or 15 which is further characterized in that said emitter region is relatively lightly doped at said surface and has a surface concentration which would be obtained by diffusion through a thin oxide layer.

17. The thyristor of claims 14, 15 or 16 which is further characterized inthata guard ring of said other conductivity type is formed into said surface and disposed between and laterally spaced from said anode and base regions; said guard ring being out of contact with said cathode and anode electrodes and floating electrically with respect to said electrodes.

18. The lateral thyristor of claim 17 which is further characterized in that said emitter region, said base region and said guard ring are relatively thin regions having coextensive portions.

19. Thethyristorofanyofclaims 14to 18 which is further characterized in including means for resistively connecting said auxiliary region to said cathode electrode.

20. An optically triggered thyristor comprising a semiconductor substrate of one of the conductivity types, characterized in that said substrate has at least first and second spaced, parallel base regions of the other of the conductivity types extending into the surface of said substrate; respective emitter regions of said one of said conductivity types extending into said surface of at least first and second parallel base regions and being completely contained within their said respective base regions; respective elongated anode regions of said other of said conductivity types extending into said substrate and disposed on opposite elongated sides of and laterally spaced from each of said parallel base regions and extending at least coextensively with said base regions; an anode contact connected to said anode regions; a cathode con tact connected to said emitter regions; and radiation generating means energizable to generate minority carriers in said substrate which act as a base drive to turn on saidthyristorwhen appropriate bias voltages are applied to said anode and cathode contacts.

21. The thyristor of claim 20 which is further characterized in that said anode regions consist of parallel elongated fingers extending from an enlarged area of said other of said conductivity types which extends into said substrate surface and which is disposed adjacent one of the ends of said base regions.

22. The thyristor of claim 20 or 21 which is further characterized in including a plurality of auxiliary regions of said other of said conductivity types which extend into said substrate surface and which loop around and are laterally spaced from the elongated sides and one end of respective ones of said base regions and being disposed between their respective bases and said elongated anode regions associated therewith.

23. The thyristor of claim 22 which is further characterized in that said plurality of auxiliary regions extend from an enlarged region of said other of said conductivity types which is disposed adjacent one end of said base regions.

24. The thyristor of claim 20 which is further characterized in that said elongated anode regions and said plurality of base regions are separated from one another by a continuous, elongated, serpentine strip of said material of said one of the conductivity types.

25. The thyristor of claim 24 which is further characterized in including a guard ring of said other of the conductivity types which is disposed centrally of and is coextensive with said elongated serpentine strip and which extends into said substrate surface.

26. Thethyristor of claim 24 or 25 which is further characterized in including first and second field plates which are spaced from one another and are disposed above and are coextensive with the opposite edges of said elongated serpentine strip.

27. The thyristor of any of claims 27 to 30 which is ther characterized in including a respective control transistor for each of said at least first and second base regions; each of said control transistors comprising spaced source and drain regions extending into said surface of said substrate and laterally spaced from their respective said base regions; and contact means supported on said substrate and electrically connecting each of said base regions to said drain region of their respective control transistor; said drain regions of each of said control transistors connected to said cathode contact; respective gate insulation layers overlying said substrate in the space between said source and drain regions of each of said control transistors; and gate electrode means atop each of said gate insulation layers.

28. The thyristor of claim 27 which is characterized in further including first and second capacitors formed on said substrate and connected in series between said anode and cathode contacts and defining a capacitive divider; said gate electrode means of said control transistors connected to the node between said first and second capacitors; said first and second capacitors being sized to apply only a small fraction of the voltage between said anode and cathode contacts between said gate electrode means and said substrate, whereby said gate insulation layer can be very thin and of the order of 0.1 micron.

29. The thyristor of claim 28 which is further characterized in that said first capacitor is a distributed capacitance and said second capacitor consists of a capacitor junction in said substrate and a capacitor electrode atop said capacitor junction; said capacitor electrode connected to said anode contact.

30. The thyristor of claim 29 which is further characterized in including zener diode means formed in said substrate and connected between said node between said first and second capacitors and said cathode electrode.

31. The thyristor of any of claims 20 to 26 which is further characterized in including integral resistor means connected across said source and drain regions of each of said control transistors; said resistor means including a strip of polysilcon deposited atop a given region of said substrate; a layer of silicon dioxide disposed between said given region of said substrate and said strip of polysilicon, whereby said resistor is electrically isolated from parasitic currents in said substrate; and first and second terminals extending from spaced points on said polysilicon strip; said first terminal connected to each of said contact means which are connected to said bases; said second terminal connected to said cathode contact respectively.

32. An optically triggerable lateral thyristor sub stantially as hereinbefore described with reference to Figure 1 of the accompanying drawings.

33. An optically triggerable lateral thyristor substantially as herein before described with reference to Figures 2 to 9 of the accompanying drawings.

34. An a.c. relay substantially as hereinbefore described with reference to Figures 10 to 14 of the accompanying drawings.