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GB2120487A - Signal discriminating apparatus - Google Patents

Signal discriminating apparatus Download PDF

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Publication number
GB2120487A
GB2120487A GB08313816A GB8313816A GB2120487A GB 2120487 A GB2120487 A GB 2120487A GB 08313816 A GB08313816 A GB 08313816A GB 8313816 A GB8313816 A GB 8313816A GB 2120487 A GB2120487 A GB 2120487A
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GB
United Kingdom
Prior art keywords
signal
signals
value
circuit
sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB08313816A
Other versions
GB8313816D0 (en
GB2120487B (en
Inventor
John Frederick Brentnall
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems PLC
Original Assignee
British Aerospace PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by British Aerospace PLC filed Critical British Aerospace PLC
Priority to GB08313816A priority Critical patent/GB2120487B/en
Publication of GB8313816D0 publication Critical patent/GB8313816D0/en
Publication of GB2120487A publication Critical patent/GB2120487A/en
Application granted granted Critical
Publication of GB2120487B publication Critical patent/GB2120487B/en
Expired legal-status Critical Current

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0038Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller (comparing pulses or pulse trains according to amplitude)

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Picture Signal Circuits (AREA)
  • Amplifiers (AREA)

Abstract

Signal discriminating apparatus for receiving a plurality of analog signals and for selecting therefrom a particular signal of which the value bears some predetermined relationship to the values of the other signals, for example the median value signal, comprises a sequence of extreme value selector circuits each operable for receiving the signals or a sub-set thereof and for picking out an extreme-value one of the received signals, and disabling means for causing all but the first selector circuit in the sequence to be non-responsive to signal(s) selected by previous selector circuits. <IMAGE>

Description

SPECIFICATION Signal discriminating apparatus This invention relates generally to signal discriminating apparatus for receiving a plurality of analogue electrical signals and for selecting, from those signals, one of which the value has some predetermined relationship to the values of the others.
For example, the apparatus may be operable for selecting the median of an odd number of signals, the median being the signal whose value exceeds the values of as many of the other signals as it is exceeded by.
According to the invention, there is provided signal discriminating apparatus comprising a plurality of extreme value selector circuits each of which is operable for considering a plurality of analogue input signals and for selecting, from amongst those signals, one of which the value represents a limit of a value range just containing the values of all the considered signals, the apparatus further including disabling means for controlling each of at least all but one of the said selector circuits so that it removes from those which it considers one or more of a plurality of signals which it actually receives, the circuits all being arranged to receive the same plurality of analogue input signals and said disabling means being operable, in effect, to order the circuits into a series sequence with said one circuit as the first in the sequence and each other circuit controlled to remove from consideration thereby any received signal which has been selected by a circuit preceding it in the sequence.
Each extreme value selector circuit may be operable to select the signal of which the value is the highest of those considered.
Advantageously, each selector circuit comprises a plurality of comparator amplifier circuit cells arranged to receive respective ones of said received plurality of signals, and a common amplifier feedback line connected to all of the cells such that the feedback signal on this line is derived from the cell receiving said signal of which the value represents the limit of the range of values of the considered signals.
Said disabling means may then comprise a plurality of switch elements for disabling the feedback loop in respective comparator amplifier circuit cells and respective interconnections for causing each switch element to be controlled in dependence upon a signal formed in an associated cell of the next preceding selector circuit in the sequence.
For a better understanding of the invention, reference will now be made, by way of example, to the accompanying drawings, in which: figure 1 is a partly simplified circuit diagram of an analogue median value finding apparatus, figure 2 is a circuit diagram of a modified comparator amplifier cell which may be used in the figure 1 apparatus.
The apparatus shown finds the value of the median of an odd number N of analogue input signals, the median being the signal which is greater than each of half the remaining signals and less than each of the other half, i.e. the (N + 1 )/2to highest signal. The apparatus comprises a row of (N + 1)/2 maximum value selector circuits 1 each of which comprises N cells 2. The cells of each circuit are the same as each other and the same as the cells of each other circuit. Thus the cells form a matrix of rows and columns, each column forming one maximum value selector circuit and each row being operable to deal with a particular one of the N input signals. The N input signals are received at respective ones of N input terminais 3, each terminal 3 being connected to an input of each cell 2 in a respective row thereof.Within each cell, the appropriate input signal is received at the noninverting input of a comparator amplifier 4 of which the output is connected to the anode of a diode 5. The cathode of diode 5 is connected to one side of a resistor 6 and to the cathode of a further diode 7. The anode of diode 7 is connected to a line 8 to which there is also connected the anodes of the corresponding diodes of all the other cells in the same column and the inverting inputs of the comparator amplifiers of all the cells in that column. Thus, there is a respective line 8 for each column of cells and each of these lines is supplied with a current signal from a respective constant-current source 9.
A connection 10 is made between the output of the amplifier 4 in each cell, apart from those in the last or (N + 1)12th column, to the other side of the resistor 6 of the cell in the same row but the next adjacent column. The other sides of the resistors 6 in the cells of the first column are not so connected because of course there is no preceding column. Instead, the resistors 6 in the first column are all connected to one side of a common resistor 11 of which the other side is connected to a source of negative potential -V.
Considering now the cells in the first column, i.e. the first maximum value finder circuit, each amplifier 4 thereof receives a respective one of the input signals at its non-inverting input while its inverting input receives a common feedback voltage from the associated line 8. Consideration of the arrangement will show that this feedback voltage is derived from which ever of the amplifiers is receiving the highest input signal voltage -- this amplifier alone will be operating in a closed-loop manner while the output from each other amplifier will go negative. Thus, the connections 10 from the first column cells which were not receiving the highest value will each carry a "low" signal while the connection 10 from the first column cell which did receive the highest input signal will be "high".This "high" signal causes the diode 7 in the next cell of the same row to cut-off. This diode acts as a disabling switch element which when cut-off breaks the feedback loop around the associated amplifier and disables it. As a follow-on from this, all the other cells in that row will also be disabled.
The cells in the second column act in the same way as those of the first column except that since the highest input signal value cell has been disabled, the amplifier in the cell which is receiving the second highest input signal will be the only one operating in closed-loop manner and the feedback signal on the associated line 8 will be derived from the output of this amplifier. This amplifier thus also produces a high signal on the relevant connection 10 disabling the next cell and hence also each other cell in the same row.
The sequence continues as above with the cells in the third column sensing the third highest input signal value, the cells in the fourth column (if there is one) sensing the fourth highest value and so on.
In the last column the (N + 1)/2th highest signal is sensed, i.e. the desired median value. This value appears on the associated line 8 from which a connection is made to an output terminal 12.
In the first column of cells, all the resistors 6 are fed with a common enable signal via resistor 11 as mentioned earlier. Since none of these cells need to be disabled at any time, the construction of each could take the simplified form shown in figure 2. Here, the output of each amplifier 4 is again connected to the anode of a diode 5 and, via a connection 10, to the resistor 6 of the cell in the next column. However, no resistor 6 is provided in the first column cell and nor is there any diode 7.
Instead, the cathode of diode 6 is connected, along with the cathodes of the diodes 6 of the other first column cells, to a common line 20. The inverting inputs of the amplifiers 4 of the first column cells are also connected to this line 20 and it is coupled via resistor 21 to the negative voltage source -V. The resistor 21 replaces the resistor 11 of figure 1 and in addition the figure 2 cell is not coupled to any current source 9.

Claims (5)

1. Signal discriminating apparatus comprising a plurality of extreme value selector circuits each of which is operable for considering a plurality of analogue input signals and for selecting, from amongst those signals, one of which the value represents a limit of a value range just containing the values of all the considered signals, the apparatus further including disabling means for controlling each of at least all but one of the said selector circuits so that it removes from those which it considers one or more of a plurality of signals which it actually receives, the circuits all being arranged to receive the same plurality of analogue input signals and said disabling means being operable, in effect, to order the circuits into a series sequence with said one circuit as the first in the sequence and each other circuit controlled to remove from consideration thereby any received signal which has been selected by a circuit preceding it in the sequence.
2. Apparatus according to claim 1, wherein each said extreme value selector circuit is operable to select the signal of which the value is the highest of those considered.
3. Apparatus according to claim 1, wherein each selector circuit comprises a plurality of comparator amplifier circuit cells arranged to receive respective ones of said received plurality of signals, and a common amplifierfeedback line connected to all of the cells such that the feedback signal on this line is derived from the cell receiving said signal of which the value represents the limit of the range of values of the considered signals.
4. Apparatus according to claim 3, wherein said disabling means comprises a plurality of switch elements for disabling the feedback loop in respective comparator amplifier circuit cells and respective interconnections for causing each switch element to be controlled in dependence upon a signal formed in an associated cell of the next preceding selector circuit in the sequence.
5. Signal discriminating apparatus substantially as hereinbefore described with reference to the accompanying drawings,
GB08313816A 1982-05-20 1983-05-19 Signal discriminating apparatus Expired GB2120487B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB08313816A GB2120487B (en) 1982-05-20 1983-05-19 Signal discriminating apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8214711 1982-05-20
GB08313816A GB2120487B (en) 1982-05-20 1983-05-19 Signal discriminating apparatus

Publications (3)

Publication Number Publication Date
GB8313816D0 GB8313816D0 (en) 1983-06-22
GB2120487A true GB2120487A (en) 1983-11-30
GB2120487B GB2120487B (en) 1985-11-27

Family

ID=26282883

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08313816A Expired GB2120487B (en) 1982-05-20 1983-05-19 Signal discriminating apparatus

Country Status (1)

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GB (1) GB2120487B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0130383A1 (en) * 1983-06-03 1985-01-09 Hitachi, Ltd. Signal selection circuit
EP0625755A2 (en) * 1993-04-30 1994-11-23 American Telephone and Telegraph Company Median value detection technique

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1285742A (en) * 1968-06-28 1972-08-16 Post Office Voltage detector

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1285742A (en) * 1968-06-28 1972-08-16 Post Office Voltage detector

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0130383A1 (en) * 1983-06-03 1985-01-09 Hitachi, Ltd. Signal selection circuit
EP0625755A2 (en) * 1993-04-30 1994-11-23 American Telephone and Telegraph Company Median value detection technique
EP0625755A3 (en) * 1993-04-30 1995-08-09 American Telephone & Telegraph Median value detection technique.

Also Published As

Publication number Publication date
GB8313816D0 (en) 1983-06-22
GB2120487B (en) 1985-11-27

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PCNP Patent ceased through non-payment of renewal fee