GB2183374A - Sequential access memory - Google Patents

Abstract

The memory includes individual FET memory cells (R) (Figure 2) arranged in a matrix with a common set of column bit lines driven by transistors (PT1, PT2 ...) to prepare the cells for read or write. The rows of cells are selected by a pointer register (PR), a shift register in which a defined bit condition circulates to select the cells in the columns sequentially. The data input (IN) is offered to all cells in the first column, and the cells outputs and inputs are merged so that the whole device acts as a serial shift register. When a cell (e.g. R31) is selected for read-out, its neighbour (e.g. R21) is selected for write-in, the selection using the appropriate gate (e.g. G3) primed from the shift register. As a result of the merging of inputs and outputs a bit read from one cell goes to the cell in the next column therefrom and one up from the cell in the signal column. Thus the data is progressed through the array to the output (OUT). The output may be retimed to the clock original (Figure 4), with writing from the first column being to the row three places above. A filter frame store (Figures 6a, 6b), for echo cancellation may be provided. <IMAGE>

Description

SPECIFICATION Sequential access memory This invention relates to memory arrangement for use, for instance in digital signal processing (DSP) equipment.

DSP systems are often "memory intensive" as a high proportion of the circuitry is used to store input data and intermediate results. Hence a VLSI implementation should use a storage mechanism which is as areaand power-efficient as the technology allows. Main implementations to date in DSP systems use random-access memory (RAM) and shift register storage.

Often a DSP system does not need the full random addressing capabilities of a convention RAM, since data is often accessed regularly, e.g. sequentially in the order of entry. Thus the addressing circuitry is often superfluous. Further, a dynamic RAM needs refresh circuitry, which adds to the "overheads" on the chip.

Finally, itis oftern desirable to be able to write data in atthe same time as othervalues are being read,and even to read and write several values simultaneously. A conventional RAM cannot meet these requirements.

Shift register storage more closely meets the needs of a DSP system in terms of output ordering and multiple read and write capability, but at the cost of area and power consumption, loading of clock lines, etc.

An objectofthe invention isto provide a memorywhich minimizes or even overcomesthe above-mentioned disadvantages ofthe prior art.

According to the invention, there is provided a sequential access memory array, which includes a number oftransistorised memory cells arranged in a co-ordinate array with the cells interconnected by bit lines each interconnecting the outputs of the cells in one column of the array, a pointer register formed by a shift register with a cell for each rowofthe array, which shift register contains a single bitconditionwhich circulatesthereintoselectthe rows sequentially, a common write inputforthe array applied to all cells in a first one ofthe columns ofthe array, connections from the outputs ofthe cells in each ofthe columns to the inputs of the cells in the next adjacnet ones ofthe columns, further connections each extending between the read input of one cell and the write input of a preceding cell in the same column ofthe array, outputsfromthe pointer register each of which goes to said further connections for all cells ofthe same row ofthe array, and a connection from the outputs of cells ofthe last one of said columnsto a common outputforthearray, wherein in each clock pulse period one cell in each said column is prepared for read-out and another associated cell is prepared forwrite-in via the appropriate output connection from the pointer register, and wherein due to the said row-wise connections between the outputs and the inputs ofthe cells and the cells in successive columns ofthe array each clock pulse period causes the bits in a said column of the array to be transferred along the arrayin a row-wise direction to an adjacent column but with the bits shifted column-wise, such thatthe array functions in a manneranalogousto a shift register.

Such an arrangement can be configured to be functionally equivalent to a shift register butwith large savings in area and power consumption. Thus the sequential access memory (SAM) may use a dynamic RAM concept, but operates by constantly moving the stored data, which satisfies the sequential access requirements, and eliminates the need for the complex addressing and refresh circuits usually used with dynamic RAMs.

Embodiments of the invention will now be described with reference to the accompanying drawings, in which: Figure 1 is the basic storage element for a SAM embodying the invention.

Figure2 is a simplified schematic of a SAM which embodies the invention, used in shift register manner, Figure 3 shows how data movementthrough a SAM such as that shown in Figure 2 occurs.

Figure 4shows a modified version of Figure 3.

Figure 5shows how two shift registers can be implemented in one SAM array.

Figure 6a shows how a SAM array is used to provide a data frame store for a transversal filter and Figure 6b is an explanatory diagram therefor.

Figure 7 shows the use ofthree SAM sub-arrays with data rate converters.

In the arrangements described herein, the basic cells use n-channel transistors, and the pre-charge devices on the bit lines are p-channel. As shown in Figure 2 and subsequent figures, p-channel transistors are each shown with a small circle on the gate connections.

The basic storage cell, Figure 1, includes a storage transistor TI, a writetransistorT2, and a read transistor T3, all n-channel devices. it functions by storing charge capacitively at node A, at the gate of Ti ,when the write input goes high and then low. This allows an information pulseforstorageto enterthe cell at its input IN. The stored information has to be refreshed at frequent intervals, at 1 OKHZ to 1 OOKHz for atypical 3 microns CMOS device. However, in the arrangements to be described herein, the data in the SAM is kept in motion, so that it is in effect maintained by a 'self-refresh' process. A pulse of similar characteristics on the RD input, and so on the gate of T3, causes read out of stored data.

Where static memory cells are used, refresh is not required, and the pre-charge arrangements described below are not needed.

The timing input to a SAM, Figure 2, is a simple square wave input at its clock input CK, which is applied via a pu Ise ti m er PT to the gates of the pre-charge transistors PT1, PT2, etc., each of which serves one bit line,the column lines being the bit lines. The clock pulses are also applied via delays included in the timer PTto gates such as G1, , ..., one per rowofthe array. Thus the LOW clock pulses as applied to PT1, PT2,... do not overlap intimethe HIGH pulses applied to the gates such as Gi, The blocks R in Figure2 each representa storage cell such as that shown in Figure 1. These are controlled by the pre-charge transistors PT1, PT2...

mentioned above, and by a pointer register PR, the latter's control being exercised via the gates Gl,G2... As already mentioned, if static memory cells are used, these pre-chargetransistors are not needed. The pointer register PR is a shift registerwith a "1 " bit in one stage, and is also controlled by the clock pulses from the input CK. Hence the 1 bit circulates repeatedly to enable the rows of the array one at a time. Note that the clock pulses which drive PR are in synchronism with those applied to the gates such as G1,but not with those applied to the pre-charge transistors. Changes in the memory state are caused by the positive-going edges of the clock pulses.

In Figure 2, the period when CK is low is used to pre-charge the bit lines via the p-channel transistors PT1, PT2 ... The remainder ofthe clock period, i.e. when CK is high, is used to selectively discharge the bit lines.

Note that a bit line is discharged if the stored bit for that column is HIGH, i,e, if the data input previously applied to DATA IN is HIGH.

Duetothecirculation ofthe 1 bit in PR, in each clock period one cell in each column is enabledforreading, and the cell directly above it is enabled for writing. Thus, for example, when the 1 bit in PR is in the second stage down, the gate G3 is enabled and passes the clock pulse to the RD input of the cell R31 , so that the cell is read. In addition, the WR inputofthe cell R21 is enabled via G3.Thus an information pulse on the input DATA IN, which is offered to all cells in the first column via a transfer gate represented schematically by a transistor Pi and an amplifierAl, is applied via the cell's input IN (Figure 1 )tothetransistorT2 ofthatcell.Thuswegeta simultaneous read outfrom R31 and write into R21 of a new information pulse.

The inputs and outputs of the cells in adjacent columns are merged, as shown, and this, with the read-write selection just mentioned, means thatthe intelligence read from R31 is written in to R22 in the next column.

This follows since, due to thetimings discussed above, when a pulse is read from R31 all cells in the preceding row, i.e. R21, R22 ..., are selected for writing.

To summarise the above operation, each clock pulse sees the transfer of a column of bits one place to the right and one place up. Any bit transferred from a cell of the top row gets transferred to a cell ofthe bottom row to complete the connection of all cells into a single sequence. There is a data inversion between columns, but this can be compensated for at the output if the total number of inversions is odd, no compensation being needed ifthetotal number of inversions is even.

The arrangements represented by the input p-channel device P1 ensure that the input data pulses have a complete clock cycle of propagation time from their source to the input ofthe buffer amplifier Al. The output n-channel device N2 enables the output of data to be synchronised to take place in the "inter-pulse"gapsof the clock pulses applied to the bit lines. Thus each output data pulse is valid in the HIGH pulse period, and is available during the succeeding LOW pulse period. Such a sample and hold technique prevents pre-charge from getting through, and allows later sampling at destination.

In Figure 2 and in certain ofthe other drawings column driving amplifiers and possibly rowdriving amplifiers may be used, but these have not been shown to avoid unnecessarily complicating the drawings.

Figure 3 gives an example of data shifting through a SAM array arranged as a ten bit shift register, the arrows indicating the positions of the pointer. Note that for the extreme end positions, two arrows are shown.

The input is shown below the first column, the number identifying the input bit in the input sequence, and the values on the bit lines are shown above the columns. It will be seen thatwith suitable connections multiple outputs can be obtained with in put-output delays that are 1 plus an integral multiple of 3 (number of rows less 1 ) clock cycles. Memory locations are written once every (N + 1 ) clock cycles. This, as already mentioned with reference to Figure 1, avoids the need for separate connections for refresh.

Notethatwith the arrangement described, we in effect lose one cell per column, since at any time one cell is effectively slaved to its predecessor.

The one-clock cycle delay due to the half-latch formed by the input connections to the SAM shown in Figure 2 can be nuisance, since often outputs are needed which are delayed by integral multiples of some number.

In addition, if, as may be the case with large arrays, the full clock period is needed for bit-line discharging, then no time is left for propagation ofthe SAM output(s) to other circuitry. To allow a full clock period for propagation delay, the SAM output is re-timed to the clock signal, which gives an extra clock period delay on the output.

These extra delays can be compensated for by reducing the latency, i.e. the number of clock cycles between input and output of a bit, of the first column by two clock cycles. To do this, writing is to the rowthree places above the one being read, instead oftheone above, as in Figure 1. ASAM modified in this way is shown in Figure 4.

Figure4 is similarto Figure 1, exceptforthe connections to the cells from the pointer register PR for write-in. Thus, for example, when the pointer register PR has its third stage at 1, gate G4 is enabled to read cell R41 and to write into cell Ril. In addition, the read outputfrom R41 goes to R32 in the next column.

Note that other distances between the cell written to and the cell read from can be used, e.g. two orfour cells' distance. However, it is unlikely to be useful for the distance to exceed five cells.

The need for providing multiple inputs and outputs was mentioned above. To obtain multiple inputs and outputs, the input and output lines of adjacent columns can be split as shown in Figure 5. Here we see what is in effect two "sub-arrays", each with its own input and output, and both driven by the same pointer register PR. Thusthe lefthand "half" has input DATA IN1 andoutputOUTl,whiletherighthand "half" has input DATA IN2 and output OUT2. This principle can be extended so that the array provides, as seen by the inputs and outputs, three or more shift-registers. By including a multiplexer, as in Figure 6, a split SAM can be made to appear like a single shift register with selective over-write capability.

A SAM can also be used to implement the data store for a bit-serial transversal filter, as used, for instance, in some echo cancellers and in many digital signal processing applications. In such an application, one new data word is added in each data frame, the new word over-writing the oldest word in the store. During the data frame, all words in the store are sequentially output from the oldest to the most recent.

The above function is achieved in an N-word frame by using a SAM which provides N-l word-periods of delay, and feeding the output backtothe input. One column, any desired one, has a multiplexed inputsothat an external signal can control the over-writing of the unwanted data with the new data. This is shown in Figure 6a, where we see such a store implemented as a SAM. Here the multiplexer MUX has an up-dateinput applied via an inverter INV, and a direct input from the lead IN.Hence in one condition the data in the lefthand portion ofthe SAM passes directly through MUX to the righthand portion,while in the othercondition,when the UPDATE lead is energised, the data on the input IN passes into the SAM.

Figure 6b shows a simple example of how data progresses in a store used as a filterframe store; here it implements a three word SAM used as a four-word frame store. The arrows indicate new data being introduced into the first stage.

As a SAM's size increases, so its performance decreases. This is because an increase in the number of rows increases the bit line capacitances, and an increase in the number of columns increases the RDIWR line capacitance. Such increases in capacitance reduce the speeds at which the SAM can operate. For a given size of SAM, there is an optimum aspect ratio. In multiple output SAMs the tap point. In requirement determines the aspect ratio and optimum device sizes for fastest implementation. For a given SAM size there is an absolute performance limit, and to approach this limit needs large high-power peripheral devices.

Performance can be improved by splitting the SAM, i.e. increasing the number of RD/WR line drivers, or increasing the number of sense amplifiers (not shown) used to read the SAM's output. These sense amplifiers when used are connected to the column bit lines. However, the speed improvement is small, and the increase in peripheral area needed on the chip is large.

A better approach, see Figure 7, is to provide data rate converters atthe inputs and outputs of moderate-rate SAM's. Here there are three arrays, each operating at one third of the system's clock speed.

The shift registers formed by DR1, D R2 at the bottom and CR1, CR2atthetop are clocked at the fast system clock rate. The shift register SAM "sub-blocks" share an array and pointer register clocked at one third of the fast rate. The devices CR1, CR2, etc are switched in or out one every three system clock pulses at the same time so that the data is progressed through to the output DATA OUT.

In this arrangement, the bits to be inserted into the various sections of the memory enter on DATA IN and pass via DR1 and DR2 to the sections. Thus in successive steps bit 1 passes via DR1 and DR2 into the left hand section. Bit 2, following this passes via DR1 into middle section, and bit 3 directly enters the right hand section. Then bit3 passes via DR1 and DR2 into the left-hand section, bit 5 passes via DR1 into the middle section and bit 6 passes into the right hand section. Hence after nine bits have come in we have: Left-Hand Middle Right-Hand Section Section Section 1 2 3 4 5 6 7 8 9 This it does in eleven steps.

The bits leave in a somewhatsimilarway: thus bit 1 leaves via DATA OUT, bit 2 via CR2, bit 3 via CUR 1 and CR2, and so on.

This relatively simple technique enables the data access rate of a very compact storage block to be matched to the switching speed used elsewhere in the system. Hence the SAM will not form a bottle-neckon system performance.

The method can be extended to parallel data formats simply by replicating the structure of Figure 7, n times, where n is the required data width. The pointer register is still common to the whole array.

We nowconsiderthetiming, i.e. clock pulse generation, in somewhat more detail than considered above.

As already indicated, the clock signals which control the pre-charge transistors and the pointer register are made non-overlapping. This ensures that a read or write signal is never HiGH during the pre-charge period, prevents data corruption and reduces power consumption. Since there is only a pre-charge transistor per column, little area overhead is introduced by making the transistorslarger than the transistors in the same array. This reduces the pre-charge time and releases more ofthe clock period for reading. Hence it achieves reduced access times and improved performance.

There is a requirementto be ableto stop and startthe data shifting through the arrayandto maintainthe output's value. This enables sign-extended data to be represented in a compact form, for example. A signal is provided that disables all internal clocking, since storage is dynamic, the shifting cannot be halted in this implementation for more than a few microseconds. Note that where static storage cells are used this limitation does not apply.

The 1 bit in the pointer register is inserted on switch on, and is inserted by gating means. It is also periodically reset in case of 'soft' errors corrupting the contents.

It is often necessary to be able to reset the entire SAM; because ofthe inversion between columns alternate columns must be set HIGH and LOW. The following sequence is needed: (a) each second column is pulled LOW (b) all read/write lines are taken HIGH. The SAM cells whose inputs are connected to the discharged lines thus have their storage capacitance (node A, Figure 1) pulled LOW.

(c) when (b) is completed the pre-charge transistors on the remaining bit lines are turned on, with the read/write lines remaining HIGH.

The application ofthe present invention to an echo canceller was mentioned earlier in this specification.

Such an echo canceller is used in a telecommunications system in which four-wireto two-wire conversion is needed. Such an arrangement is described in our Patent No 2111 354B, which describes an echo canceller as used in a fully digital telephone system in which thesubscriberto exchange loops use twisted pair cables and convey PCM. The GO and RETURN paths at an end ofthe cable are coupled to the two wires of the loop via a hybrid, and it is then necesssaryto deal with interference caused by imperfections in the hybrid.

This interference is removed by applying a defined fraction of the outgoing signal from an encoder in the GO path via a sample-and-hold circuit and echo simulator. The latter includes coefficient generating circuits controlled by the signal in the RETURN path and by the outgoing signal. These coefficients are subtracted from the RETURN path signal fed via a filter to substantially eliminate the interference.

Intersymbol interference is removed by a feedback equaliser which controls the sample and hold circuit in the RETURN path to force to zero an adaptable weighted sum of symbol spaced estimates of the overall transmitted symbol time response from the transmitter to the detector, specifically shaped by both analogue and digital filters.

The functions mentioned above include several applications of signal processing, for which a sequential access memory can readily be used. In such a case the entire digital circuitryforan echo cancellercan be incorporated into a single integrated circuit unit.

it should be noted that the present arrangement is suited to other applications of digital signal processing.

Claims (10)

1. Asequential access memory array, which includes a numberoftransistorised memory cells arranged in a co-ordinate array with the cells interconnected by bit lines each interconnecting the outputs ofthe cells in one column of the array, a pointer registerformed by a shift register with a cell for each row of the array, which shift register contains a single bit condition which circulates therein to select the rows sequentially, a common write inputforthe array applied to all cells in a first one ofthe columns ofthe array, connections from the outputs ofthe cells in each ofthe columns to the inputs ofthe cells in the next adjacent ones ofthe columns, further connections each extending between the read input ofone cell and the write inputofa preceding call in the same column ofthe array, outputs from the pointer register each of which goes to said further connections for all cells of the same row ofthe array, and a connection from the outputs of cells ofthe last one of said columns to a common outputforthe array, wherein in each clock pulse period one cell in each said column is prepared for read-out and another associated cell is prepared forwrite-in via the appropriate output connection from the pointer register, and wherein due to the said row-wise connections between the outputs and the inputs ofthe cells and the cells in successive columns of the array each clock pulse period causes the bits in a saidcolumn ofthe array to be transferred along the array in a row-wise direction to an adjacent column but with the bits shifted column-wise, such thatthe array functions in a manner analogous to a shift register.

2. An array as claimed in claim 1, in which the connections between the stages of the pointer register and the cells in the respective columns are such that the cell enabled forwrite-in is the one immediately behind the cell enabled for read-out.

3. An array as claimed in claim 1, in which the connections between the stages of the pointer register and the cells in the respective columns are such that the cell enabled forwrite-in is more than one cell behindthe cell enabled for read-out.

4. An array as claimed in claim 1,2 or3, in which the row connections are split between an adjacent pairof the columns of cells, so that two sub-arrays of cells are formed, and in which each such sub-array has its own input and output, so that data can be entered and read out at the same time into and out of the two sub-arrays.

5. An array as claimed in claim 1,2 or 3, in which the array has splits in its row connections between two or more separated pairs of adjacent columns so thatthree or more sub-arrays of cells are formed, and in which each such sub-array has it own input and output, so that data can be entered and read out atthesame time into and outofthe sub-arrays.

6. An array as claimed in claim 4, in which the outputs of the last column of one said sub array are connected to the inputs of the first column of the other sub array via a multiplexer, in which gating means so controls the multiplexer, that data can be passed via that multiplexer between the two sub arrays, orthe multiplexer can block such passage and allow new data to enter the second sub array, so that the contents of the array can be up-dated when this is needed, and in which connections are provided whereby data can be fed back from the last column of the second sub-arraytothefirstcolumn ofthefirstsub-array.

7. An array as claimed in claim 1,2,3,4,5 or6, wherein the memory cells used are dynamic memorycells, and wherein the column bit lines are pre-charged by clock pulses in preparation for data transfer or output.

8. An array as claimed in claim 1,2,3,4,5 or 6, wherein the memory cells used are static memory cells.

9. A sequential access memory array, substantially as described with reference to Figures 2,3,4,5 6a and 6b or Figure 7 of the accompanying drawings.

10. An echo canceller integrated circuit unit which includes an array as claimed in any one of the preceding claims.