GB2158311A - Output stage for a logic circuit - Google Patents

Abstract

An output stage for a logic circuit includes a source follower first output transistor (M0) in parallel with a second transistor (M1) having a channel of the opposite conductivity type to the first transistor and connected in a common source circuit. A logic drive signal (D) initially turns on both transistors and the voltage on output line (2) rises rapidly. When the output passes a threshold value, the connection of the logic drive signal to the second transistor is disabled by a trigger circuit (11, M4), the first transistor (M0) remaining conductive until the end of the logic drive signal. The stage has a tristate condition in which all transistors connected to the output conductor are non-conducting. <IMAGE>

Description

SPECIFICATION Output stage for a logic circuit This invention relates to an output stage for a logic circuit.

In digital circuits the logic state is represented by the voltage on a conductor. Usually there are two logic states sometimes known as "high" and "low", and in so-called positive logic a "high" may be represented by a voltage greater than 2.4 volts and a "low" by a voltage below 0.8 volts. These critical voltages are set arbitrarily but are fixed for any given type of logic circuit, such as TTL, ECL and CMOS, so that different logic circuits can be interconnected in any required manner and will function satisfactorily. An important factor in the speed of operation of logic circuits is the minimum time within which the output voltage of a circuit can be changed from that representing one logic state to that representing the other logic state, in particular the "low" to "high" rise time.

In certain types of CMOS logic circuit it is necessary to have an output stage to provide the power to drive several other circuits and one form of output stage consists of a single MOS transistor connected as a source follower which means that the rate of rise from "low" to "high" on the output conductor can be no faster than that of the drive signal applied to the transistor and will probably be slightly slower because of the stray capacitance associated with the output conductor itself. It follows therefore that the response time of the circuit with such an output stage is slower as a result of the presence of the output stage.

It would be possible to reduce the rise time by the use of a supply voltage, say 5 volts, which is much higher than that corresponding to the "high" state, 2.4 volts as mentioned above, but this would result in the output voltage finally attaining that of the supply leading to a slowing down of the downward transition, from "high" to "low", due to the greater change in voltage required. In addition, the use of a larger output voltage swing than would be required by the separation between the "high" and "low" logic levels would result in an unnecessarily high power consumption since the consumption is proportional to the square of the voltage swing, if the other relevant factors are kept constant.

It is an object of the invention to provide an output stage suitable for a CMOS logic circuit capable of a faster rate of change between logic states.

According to the invention there is provided an output stage for a logic circuit on an integrated circuit having a first MOS transistor with a channel of a first conductivity type having its drain connected to a reference voltage conductor and its source connected to an output conductor, the gate of the first transistor being connected to receive a logic drive signal such as to render the first transistor conducting and produce a similar logic output signal on the output conductor, wherein a second MOS transistor is connected in parallel with the first transistor, the second transistor having a channel of a second conductivity type opposite to the first and the gate of the second transistor being connected to receive in inverted form the initial part of the logic drive signal, whereby the second transistor is rendered conducting for the initial part and enhances the rate of transition of the logic output signal on the output conductor.

The stage is particularly suitable for a CMOS logic circuit because the transistors required can be produced by the processes used to form the logic circuit itself, so that all that is required to implement the invention is a small additional chip area and some extra patterning on the masks.

The stage may include a third MOS transistor similar to the first transistor, connected from the output conductor to a second reference voltage conductor, and having its gate electrode connected to receive the logic drive signal in inverted form, the third transistor serving to discharge the output conductor to substantially the voltage of the second reference voltage conductor at the end of a logic drive signal.

The gate of the second transistor may be connected to means producing the inerted logic drive signal through a further MOS transistor having its gate connected to respond to the signal on the output conductor so that the further transistor ceases to conduct and thereby disconnects the inverted logic drive signal from the gate of the second transistor when the initial transition of the logic output signal on the output conductor occurs.

The stage may be provided with a tristate control in response to which all of the transistors connected to the output conductor are rendered non-conducting so that the output conductor can be set to any logic level by external means and the stage will provide no loading on it.

In order that the invention may be fully understood and readily carried into effect, it will now be described with reference to the single embodiment, the circuit of which is shown in the accompanying drawing.

In Fig. 1 the input binary data to the stage is fed in inverted form via a conductor 1 and appears on the output conductor 2 in erect form. The stage is powered by a 5-volt supply having its positive connection on a conductor 3 and its negative on a conductor 4. The input data on conductor 1 is inverted by inverter 5 and applied to one input of a NAND gate 6. The output of the gate 6 is inverted by inverter 7 and applied to the gate of an N-channel transistor MO. The source drain path of the transistor MO is connected from the supply conductor 3 to the output conductor. 2. The conductor 1 is also connected via a second NAND gate 8 and an inverter 9 to the gate of a second N-channel transistor M7, the source-drain path of which is connected from the supply conductor 4 to the output conductor 2.A tristate signal in inverted form is applied via a conductor 10 to inputs of the NAND gates 6 and 8 and also to the gates of an N-channel transistor M5 and a P-channel transistor M6. The source-drain path of the transistor M5 is connected from the conductor 2 to the input of an inverter 11, the output of which is connected to the gates of a P-channel transistor M2, an Nchannel transistor M3 and a P-channel transistor M4. The source-drain paths of the transistors M4 and M6 are connected in parallel between the conductor 3 and the input of the inverter 11. The source-drain path of the transistor M3 is connected from the output of the inverter 9 to the gate of a P-channel transistor M1, which gate is connected through the source-drain path of the transistor M2 to the conductor 3.The source-drain path of the transistor Ml is connected in parallel with that of the transistor MO from the conductor 3 to the output conductor 2.

In the operation of the stage described, the conductor 10 being high because the stage is not in the tristate condition, an outgoing digit "1" which appears on the conductor 1 as a low serves to turn on the transistor MO and raise the potential of the output conductor 2 to a logical high value. Typically a logical high will be above 2.4 volts and a logical low will be below 0.4 volts, although the critical values would probably be 2.0 and 0.8 volts respectively. The capacitor C shown in the figure represents the stray capacitance associated with the output conductor 2 and must be charged and discharged as the output voltage is changed.It will be appreciated that the Nchannel device MO acts as a source follower so that the voltage on the output conductor 2 can only rise at the rate at which the voltage applied to its gate rises, and will in fact be slightly slower than this because of the delaying effect of the capacitor C. When the digit "1" comes to an end, the conductor 1 goes high and the transistor MO is turned off. At this time the transistor M7 becomes conducting and serves to discharge the capacitor C to the conductor 4. The invention provides a Pchannel transistor M1 in parallel with the transistor MO so that the transistor M1 acts as a grounded source amplifier which, by virtue of its gain, does not impose the rise time limitation on the rate of rise of the voltage on the output conductor 2.The transistor Ml is turned on by a negative-going voltage applied to its gate from the output of the inverter 9 applied via the transistor M3, which is conducting when the output voltage on the conductor 2 is low. As the voltage on the conductor 2 rises, it is conveyed through the transistor M5 to the inverter 11, the falling output of which switches off the transistor M3 once the output voltage has reached the threshold between low and high. Thus the transistor M1 is conducting for only the initial part of the rise from low to high of the conductor 2 and is then turned off, but the resulting accelerated rise can occur in 3 ns.If the transistor M1 were to be kept conducting the output voltage on the conductor 2 would reach the voltage of the supply conductor 3 with the consequent slowing down of the downward transition, from high to low, mentioned above. The control of the transistor M1 is arranged to avoid this difficulty. The falling at the output of the inverter 11 also causes the transistor M2 to conduct, thus effectively connecting the gate of the transistor M1 to conductor 3 and thereby accelerating the end of the conduction of the transistor M1. The transistor M4 applies positive feedback over the inverter 11 so as to cause it to switch rapidly between states when the voltage on the conductor 2 reaches the threshold between low and high.Throughout this time the transistor M5 is maintained in a conducting state by the inverted tristate input on the conductor 10, which is high at this time. The transistor M6 is non-conducting at this time. At the end of a digit "1", the transistors M1 to M6 and the inverter 11 play no part in the discharging of the capacitor C which is effected by the transistor M7 as described above.

The stage illustrated also has a tristate condition in which the voltage of the output conductor 2 can be set to any level by an external means without the stage imposing any load on that means. In this state, the voltage on the conductor 10 is low so that the NAND gates 6 and 8 are blocked to the passage of signals, the transistor M5 is not conducting, and the transistor M6 becomes conducting. As a result of this, the input to the inverter 11 is held low so that the gate of the transistor Ml is held high by the transistor M2, and transistors MO and M7 are held nonconducting by the outputs of the inverters 7 and 9.

Claims (9)

1. An output stage for a logic circuit on an integrated circuit having an first MOS transistor with a channel of a first conductivity type having its drain connected to a reference voltage conductor and its source connected to an output conductor, the gate of the first transistor being connected to receive a logic drive signal such as to render the first transistor conducting and produce a similar logic output signal on the output conductor, wherein a second MOS transistor is connected in parallel with the first transistor, the second transistor having a channel of a second con ductivity type opposite to the first and the gate of the second transistor being connected to receive in inverted form the initial part of the logic drive signal, whereby the second transistor is rendered conducting for the initial part and enhances the rate of transition of the logic output signal on the output conductor.

2. An output stage according to claim 1, wherein the second MOS transistor receives the inverted initial part of the logic drive signal through a further MOS transistor the conductivity of which is controlled by the logic output signal on the output conductor so that the further transistor becomes non-conducting when that signal attains a threshold voltage during its transition in response to the logic drive signal.

3. An output stage according to claim 2 in which the output conductor is connected to the gate of the further transistor by means of a trigger circuit which changes state at the threshold voltage.

4. An output stage according to claim 3 including another MOS transistor responsive to the state of the trigger circuit to connect the gate of the second transistor to the reference voltage conductor when the further transistor becomes non-conducting.

5. An output stage according to any preceding claim wherein there is provided an additional MOS transistor responsive to the logic drive signal and having a channel connected from the output conductor to a second reference voltage conductor, whereby the additional transistor serves to discharge the output conductor to substantially the voltage of the second reference conductor at the end of a logic drive signal.

6. An output stage according to any preceding claim including means responsive to a tristate control signal to disconnect the logic drive signal in both upright and inverted forms from the transistor and leave all the transistors whose channels are connected to the output conductor in a non-conducting condition, whereby when the tristate control signal is applied to the stage substantially all resistive loading on the output conductor by the stage is removed.

7. An output stage according to claim 6 and including the features of claim 3, wherein the means responsive to the tristate control signal includes gating means through which the logic drive signals are applied to the transistors, a transistor connected from the output conductor to the input of the trigger circuit, and a transistor connecting the input of the trigger circuit to the reference voltage conductor.

8. An output stage for a logic circuit substantially as described herein with reference to the single figure of the accompanying drawing.

9. An integrated circuit including one or more output stages according to any preceding claim.