GB2149206A - Improvements in semiconductor devices - Google Patents
Improvements in semiconductor devices Download PDFInfo
- Publication number
- GB2149206A GB2149206A GB08425665A GB8425665A GB2149206A GB 2149206 A GB2149206 A GB 2149206A GB 08425665 A GB08425665 A GB 08425665A GB 8425665 A GB8425665 A GB 8425665A GB 2149206 A GB2149206 A GB 2149206A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- bombardment
- silicide
- region
- electron beam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 46
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 239000003870 refractory metal Substances 0.000 claims abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 238000010894 electron beam technology Methods 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 31
- 229920005591 polysilicon Polymers 0.000 claims description 24
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 10
- 229910052719 titanium Inorganic materials 0.000 claims description 10
- 239000010936 titanium Substances 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 230000005855 radiation Effects 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000000313 electron-beam-induced deposition Methods 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 239000011819 refractory material Substances 0.000 claims 5
- 230000000873 masking effect Effects 0.000 claims 2
- 238000000137 annealing Methods 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 6
- 238000005259 measurement Methods 0.000 description 5
- 229910021341 titanium silicide Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000011109 contamination Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009684 ion beam mixing Methods 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005001 rutherford backscattering spectroscopy Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- -1 also can be used Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000003746 solid phase reaction Methods 0.000 description 1
- 238000010671 solid-state reaction Methods 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/2636—Bombardment with radiation with high-energy radiation for heating, e.g. electron beam heating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Solid-Phase Diffusion Into Metallic Material Surfaces (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A process for forming a metal silicide on a region of a silicon surface comprises depositing a refractory metal on the underlying surface of single or polycrystalline silicon in the region where the silicide is to be formed and subjecting the region to bombardment with a beam of electrons. The process may be used in the formation of electrical contacts to the silicon.
Description
SPECIFICATION
Improvements in semiconductor devices
The present invention relates to the production of semiconductor devices incorporating regions made of metal silicides.
One use of silicide is in low resistance metallic contacts to a silicon substrate. These can be made by depositing a suitable metal onto contact regions of the substrate and then subjecting the deposited metal to an ion bombardment treatment such as to cause the formation of a silicide of the metal at the interface between the metal and the silicon substrate.
Unfortunately, such a process using ion bombardment causes considerable damage to the crystal structure of the implanted substrate, with a consequent deleterious effect upon its electrical properties. Conventionally, in the semiconductor art, such damage is annealed out by heating the processed substrate to a temperature and for a period sufficient for the crystal structure to re-establish itself, at least to an extent such that the effects of remaining damage is tolerable.
Such annealing normally is carried out by heating the whole wafer in a furnace for about 30 minutes. However, when relatively reactive metals such as titanium or tantalum are used to form metallic or silicide contacts to a silicon substrate, there is the possibility that significant oxidation will occur during the initial part of the heating cycle. Furthermore, the temperatures and times are such that in some areas the interdiffusion and solid state reaction processes occur more rapidly than in others, and there will be a non-uniform growth of metal silicide. This can create problems in device structures having very small lateral dimensions, for example in sub-micro interconnection lines, since there can exist high resistance spots at which little or no silicide formation will have occurred unless the processing times or temperatures have been excessive.
Another use of silicide would be as an interconnect material.
''Interconnects'' are used to couple electrically one element of a semiconductor circuit to another semiconductor element. Such interconnects commonly are formed by depositing and then etching polysilicon. Currently in the semiconductor art, polysilicon is being replaced by silicide over polysilicon (the combination being called "polycide") or by a second level which is metal interconnect. Polycide interconnects are useful because the silicide has a lower resistivity than heavily doped polysilicon. The lower resistivity improves the speed of the circuit, which can be degraded if the resistivity of the interconnect lines is too high.
in static memories, it is particularly beneficial to be able to form silicide selectively, in other words, to develop silicide on parts of an interconnect line but not on other parts. For example, part of an interconnect line without silicide can be used in a static memory as a high value resistor.
It is therefore a primary object of the present invention to develop an improved method for fabricating silicides in semiconductor circuits.
Another object is to provide a method for making silicides for use as contacts or interconnects in semiconductor circuits.
Still a further object of the present invention is to provide a method which will establish silicides selectively in a semiconductor circuit.
According to certain aspects of the present invention there is provided a process for forming a silicide region on a silicon substrate body by depositing a layer of a refractory metal on the substrate and then subjecting all or only selected parts of the refractory metal and underlying substrate to bombardment with a beam of electrons. Unlike the prior art, electron beam annealing is used in the present invention for producing silicides in semiconductors. The prior art has used ion beam mixing, which appears to be operative primarily because the ions have sufficient mass to displace atoms in the target, thereby mixing the materials which are to be combined. Electrans, however, have considerably less mass than ions, and electron beam annealing consequently would be expected to be unsatisfactory as compared to ion beam mixing for the purpose of developing silicides.The small mass of the electrons would suggest that electron beam annealing would not work for this purpose. However, it has been discovered that electron beam annealing does perform satisfactorily for developing silicides. High energy electrons such as 30 KeV penetrate the target material and lose energy by ionising the target atoms and this ionisation produces heat by way of phonons. A silicon target can be heated by bombardment of either side with similar effect as the thermal time constant of silicon is much shorter than the heating times of seconds. When a refractory metal layer on polysilicon is heated the two elements react together to form the silicide. The reaction is exothermic and this aids the combination and helps break down thin oxide layers between the metal and the polysilicon.The use of rapid transient annealing, as this form of electron beam heating is called, is suitable for VLSI structures as it avoids further diffusion of dopants in the silicon. This can be particularly important in relation to determination of gate lengths in MOSFETS with submicron dimensions. In the case of MOSFET devices adverse effect on the gate oxide can be avoided during electron beam treatment by bombarding the rear of the silicon wafer and thereby avoiding direct exposure of the structure to the electron beam.
In a further aspect of the invention, the process may also include the operation of subjecting the said region to bombardment with a beam of ions so as to cause radiation enhanced diffusion of the refractory metal into the substrate prior to the operation of subjecting the said region of the substrate to electron beam bombardment.
The substrate may or may not have a coating of silicon oxide on its surface prior to the deposition of polycrystalline silicon followed by deposition of the layer of metal.
The layer of refractory metal may be deposited by means of any convenient process. They are well known in the semiconductor art.
Examples are electron-beam deposition in which a metal source is heated by an electron beam, sputtering by ions, in radiofrequency plasma, or by chemical vapour deposition.
Preferred refractory metals are titanium and tantalum. Cobalt, which for the purposes of this application is to be considered a refractory metal, also can be used, and molybdenum and tungsten.
Although intermixing of the refractory metal and the substrate so as to cause the formation of a metal silicide interfacial layer can be made to occur as a result of thermal diffusion of radiation enhanced diffusion alone, if there is any oxide layer present on the surface of the substrate, either deliberately or as a result of oxygen contamination, then this can prevent the necessary degree of interdiffusion required to form a satisfactory metal silicide layer. Also, the presence of the oxides in the metal silicide layer which may form causes an unacceptably high sheet resistance.The electron beam treatment of the present invention quickly raises the temperature of the substrate locally to a level sufficient to disrupt any oxide layer which may be present as well as facilitating the diffusion of the metal into the substrate, thus enabling the metal silicide to form readily in those regions which have been subjected to electron bombardment, and to be substantially free from oxide contamination.
Electron beam treatment provides improved control of local heating by suitable control of the beam position, duration and energy.
The silicide is found, by Rutherford Backscattering Spectroscopy, to have a high degree of lateral uniformity. Also, the electron beam, being rapid in action and readily steerable, enables configured contacts or other structures to be made which have little migration of the metal silicide into the remainder of the substrate or elsewhere.
The present invention will now be illustrated by the following Examples. The examples described can be electron beam annealing to produce a low resistance silicide on a semiconductor surface.
Example I
A A wafer of polysilicon had a region coated with a 1000 angstrom thick layer of titanium.
The layer of titanium had been deposited by means of sputtering under vacuum. The titanium coated region of the wafer was subjected to electron beam bombardment for a period of 10 seconds. A temperature of 850 C was reached and maintained during this period.
Subsequent measurements using Rutherford backscattering techniques showed that most of the titanium had been converted into titanium silicide. Electrical measurement showed that the treated region had a sheet resistance of 1.27 ohms/square.
Example II
A second wafer similar to that used for
Example I was subjected to electron beam bombardment for the same period but at a temperature of 950 C.
Subsequent measurements again showed that excellent formation of titanium silicide had occurred. The sheet resistance was 1.11 ohms/square.
Example Ill A polysilicon wafer had a region coated with a 1000 angstrom thick layer of tantalum, deposited as for Examples I and 11. The tantalum coated region was subjected to electron beam bombardment for 10 seconds. A temperature of 950 C was reached and maintained during this period.
Again an excellent silicide was produced, which had a sheet resistance of 2.26 oh ms/s- quare.
Example IV
A polysilicon wafer coated with a 1000 angstrom thick layer of cobalt was subjected to electron beam bombardment so as to heat it to a temperature of 850 C for 10 seconds.
Similar measurements to those carried out for Examples I to Ill indicated the production of an excellent silicide with a sheet resistance of 1.31 ohms/square.
Example V
A second wafer similar to that used for
Example II was subjected to electron beam bombardment such as to raise its temperature to 950 C for 10 seconds. Again, an excellent silicide was formed. The sheet resistance was 1.38 ohms/square.
Example Vl A wafer of polysilicon had a layer of silicon oxide some 25 angstrom thick grown upon it prior to the deposition under vacuum conditions of a layer of titanium some 1000 angstrom thick. Selected regions of the wafer were subjected to electron beam bombardment such as to raise the temperature to 850 C for 10 seconds.
Subsequent measurements showed that in the region subjected to electron beam bom bardment, the silicon oxide film had been disrupted and titanium silicide had formed completely and uniformly with virtually no oxide contanination and a sheet resistance of 0.96 ohms/square. In those regions which were not subjected to electron beam bombardment, no titanium silicide had formed, indicating that the 25 angstrom silicon oxide layer was sufficient to prevent interdiffusion between the titanium and silicon even at temperature 850 C.
Thus, electron beam bomardment enables good, localised regions of metal silicides to be formed on silicon substrates, which have low enough sheet resistances to be utilised for making electrical contacts to the silicon substrate or for use as interconnects.
To use this technique for forming an interconnect, a layer of polysilicon can be deposited on a substrate (separated therefrom by a thin oxide, if desired), and a layer of refractory metal can be added thereover. The refractory metal can be tantalum, titanium, or cobalt, for example. The depth of the refractory metal layer is about 1000 angstroms.
Next an electron beam is used to bombard the entire layer of refractory metal to cause the polysilicon to mix with the refractory metal to form a metal silicide on top of the polysilicon layer. In this process, the polysilicon layer becomes thinner because some of the polysilicon has been used in the formation of the metal silicide.
Next, a mask, such as a photoresist mask, is established to cover areas that will be the interconnect lines. A standard etch technique such as plasma etching is used to etch the silicide and polysilicon except where masked, thereby leaving interconnect lines covered with photoresist which can be removed. The interconnect lines then are made up of a polysilicon layer with a layer thereover of metal silicide wherever the region had been bombarded with an elctrion beam.
Electron beams are easily controllable through electrical or magentic fields, for example, and the bombardment of the polysilicon with refractory metal thereon can be made selective. Accordingly, there will be both bombarded regions and non-bombarded regions.
Thus, an interconnect line during its fabrication according to this illustrative embodiment of the invented method can have a region which was bombarded with electrons and another region which was not so bombarded.
In the bombarded region, the layer on top of the polysilicon is a metal silicide. In the nonbombarded region, the top layer remains as a refractory metal. This metal can be etched using wet etching techniques so that the resulting interconnect lines are only polysilicon in the non-bombarded areas and polysilicon covered with metal silicide in the bombarded areas.
An alternate technique is to wet etch the intermediate product after electron beam bombardment to remove the non-reacted metal prior to definition of the interconnect lines.
Apparatus for depositing refractory metals on polysilicon are commonly known in the art.
A device for electron beam annealing which would be suitable for use in the present invention is that manufactured by Lintech of
Cambridge, England. A suitable electron beam for the bombardment is a 30 KeV beam scanned in an X-Y manner over the surface of the substrate. In this way the substrate may be heated to 850 C in 2 seconds where it can be held for 10 seconds and then the electron beam turned off. The substrate cools rapidly by radiation to room temperature.
Claims (16)
1. A process for forming a metal silicide comprising the steps of: depositing a refractory metal on an underlying surface in a region where the silicide is to be formed, the underlying surface being single or polycrystalline silicon; and subjecting a region where the silicide is to be formed to bombardment with a beam of electrons.
2. The method of claim 1 including the steps of: depositing a layer of polysilicon on a substrate and a layer of refractory metal on top of the polysilicon layer; and subjecting portions of said layers to bombardment with a beam of electrons to cause refractory metal silicide formation in the bombarded regions.
3. The method according to claim 2 wherein said refractory metal is selectively deposited.
4. The method of claim 2 wherein said refractory metal is deposited over an area which encompasses the region where metal silicide is to be formed, and wherein said electron beam bombardment is done over selected regions only.
5. The method according to claim 4 wherein said electron beam bombardment includes a step of masking to prevent electrons from bombarding masked regions.
6. The method according to claim 4 wherein said electron beam bombardment is controlled so that electrons are directed to only selected regions where silicide is to be formed.
7. The method according to claim 2 further including, after the electron beam bombardment, masking bombarded areas which are to remain and then etching.
8. The method according to claim 7 wherein only selected portions are bombarded with the electron beam and wherein the method includes etching refractory metal after the bombardment and defining silicide selectively.
9. A process for forming a contact region on a silicon substrate body comprising the steps of depositing a layer of a refractory metal on a region of the substrate body which is to be used as an electrical contact to the substrate, and subjecting the said region of the substrate to bombardment with a beam of electrons.
10. A process according to claim 1, 2 or 9 including the operation of subjecting the said region to bombardment with a beam of ions so as to cause radiation enhanced diffusion of the refractory metal into the substrate prior to the operation of subjecting the said region of the substrate to electron beam bombardment.
11. A process according to claim 1, 2 or 9 9 in which the substrate has a coating of silicon oxide on its surface prior to the deposition of polycrystalline silicon followed by deposition of the layer of metal.
12. A process according to claim 1, 2 or 9 in which said layer of refractory material is deposited by electron beam deposition.
13. A process according to claim 1, 2 or 9 in which the layer of refractory material is deposited by sputtering by ions.
14. A process acc#ording to claim 1, 2 or 9 in which the layer of refractory material is deposited in radio frequency plasma.
15. A process according to claim 1, 2 or 9 in which the layer of refractory material is deposited by chemical vapour deposition.
16. A process according to claim 1, 2 or 9 in which the refractory material comprises titanium, tantalum, cobalt, molybdenum, or tungsten.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB838327486A GB8327486D0 (en) | 1983-10-13 | 1983-10-13 | Semiconductor devices |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8425665D0 GB8425665D0 (en) | 1984-11-14 |
| GB2149206A true GB2149206A (en) | 1985-06-05 |
| GB2149206B GB2149206B (en) | 1987-04-08 |
Family
ID=10550159
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB838327486A Pending GB8327486D0 (en) | 1983-10-13 | 1983-10-13 | Semiconductor devices |
| GB08425665A Expired GB2149206B (en) | 1983-10-13 | 1984-10-11 | Improvements in semiconductor devices |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB838327486A Pending GB8327486D0 (en) | 1983-10-13 | 1983-10-13 | Semiconductor devices |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS6098620A (en) |
| GB (2) | GB8327486D0 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0259616A1 (en) * | 1986-09-12 | 1988-03-16 | International Business Machines Corporation | Silicon semiconductor device structure and process for forming same |
| US5028554A (en) * | 1986-07-03 | 1991-07-02 | Oki Electric Industry Co., Ltd. | Process of fabricating an MIS FET |
| GB2381659A (en) * | 2001-06-27 | 2003-05-07 | Agere Syst Guardian Corp | Contactless local interconnect process utilizing self-aligned silicide |
-
1983
- 1983-10-13 GB GB838327486A patent/GB8327486D0/en active Pending
-
1984
- 1984-10-11 GB GB08425665A patent/GB2149206B/en not_active Expired
- 1984-10-12 JP JP21404384A patent/JPS6098620A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5028554A (en) * | 1986-07-03 | 1991-07-02 | Oki Electric Industry Co., Ltd. | Process of fabricating an MIS FET |
| EP0259616A1 (en) * | 1986-09-12 | 1988-03-16 | International Business Machines Corporation | Silicon semiconductor device structure and process for forming same |
| GB2381659A (en) * | 2001-06-27 | 2003-05-07 | Agere Syst Guardian Corp | Contactless local interconnect process utilizing self-aligned silicide |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8425665D0 (en) | 1984-11-14 |
| GB2149206B (en) | 1987-04-08 |
| GB8327486D0 (en) | 1983-11-16 |
| JPS6098620A (en) | 1985-06-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |