GB2036390A

GB2036390A - Improvements in or Relating to Telephone Exchanges

Info

Publication number: GB2036390A
Application number: GB7847608A
Authority: GB
Original assignee: Standard Telephone and Cables PLC
Current assignee: STC PLC
Priority date: 1978-12-07
Filing date: 1978-12-07
Publication date: 1980-06-25

Abstract

Each fault in a data processing system, such as a centrally-controlled in telephone exchange, sets a 1 bit into a shift register 1 at a position appropriate to the faulty device's identity. When the central processor needs a fault report it causes a control circuit 2 to freeze the shift register and drive the data therein along the register until the first fault representing 1 bit reaches a predetermined point, eg the rightmost stage. The drive pulses also drive a counter 3 which is also stopped when the register is stopped. Thus the counter is set to a state representing the faulty circuit's identity, and this counter state is sent to the processor. Operations are then re-started to read out the identities of other faulty circuits. <IMAGE>

Description

SPECIFICATION Improvements in or Relating to Telephone Exchanges This invention relates to data processing systems which serve a relatively large number of peripheral devices.

In such a system it is usually necessary to ensure the operational integrity of the system, which means that important devices of the system have to be periodically checked. When any such device is found to be in a fault condition, the checking circuit produces a fault output.

Where, as is often the case, such a system is controlled by a central processor, it is desirable for the latter to be notified of all faults thus detected, so that the central processor can initiate an appropriate corrective action.

An object of the invention is to provide a data processing system in which faults such as described above are notified to a central processor in a relatively simple and inexpensive manner.

According to the present invention, there is provided a data processing system, which includes a number of checking circuits each of which produces a first output in the absence of a fault in the circuit which it checks and a second output in the presence of a fault in the circuit which it checks, a storage register having as its inputs the output connections from the checking circuits, so that the storage register by its contents indicates the fault conditions found by the checking circuits, a counter associated with said register and having a number of conditions at least equal to the number of fault indications which can be stored in the register, a control circuit for the register and the counter and responsive to a fault readout signal from a remote processor to cause the data in the register to be stopped until a fault indication reaches a preset point in the register, connections from the control circuit to the counter so that the latter is driven in step with the register, means responsive to a fault indication in the register reaching said preset point to stop the counter, whose condition at the time of said stoppage identifies the fault, and an enable output from the control circuit which in response to the stoppage of the counter causes a representation of the counter's condition, which identifies the fault, to be transmitted to the remote processor, whereafter in response to one or more further signals from the remote processor operation including the stopping of the register and the driving of the counter are resumed so that all of the faults whose identities have been accumulated in the register are signalled to the central processor.

The system to be described herein with reference to the accompanying drawing is intended for use in an automatic telephone exchange of the centrally controlled type. In such a case the various peripheral devices or circuits to be checked are such devices as registers and subsidiary processing devices. Thus in a system such as the now well-known TXE4 telephone exchange the devices to be dealt could be the exchange's registers, its main control units, its supervisory processing units, its interrogator and markers, and its cyclic stores and line markers.

However, the basic fault collection technique described herein is by no means limited to such systems. For instance it could be applied to a chemical plant in which there is a centralised processor, a number of "sub-processors" and a number of sensors.

We now turn to the accompanying drawing, which, as mentioned above, shows an embodiment of the invention intended for use in a processor-controlled telephone exchange.

In the circuit shown, the fault signals from the error checking circuits (not shown) are received and staticised in a shift register 1, which therefore assembles a pattern of 1 and 0 conditions indicative of the presence or absence of faults in the associated circuits. The overall operation of the arrangements shown is controlled by a Control Circuit 2, whose operation is synchronised to the rest of the system as a result of timing pulses which it receives from the clock of the central processor.

The circuit 2 controls the operation of the shift register 1 via signals on its outputs REGRESET, SHIFT CLOCK and DATA ENABLE. The last two of these controls also influence a counter 3. Reset of the arrangement shown is affected from an external signal or as a result of a decoding of an instruction from the processor. At the commencement of operations a RESET signal is produced, which causes the control circuit to emit the REGRESET signal. This clears the shift register 1, resets the counter 3 to its rest condition, and produces the DATA ENABLE pulses, which staticise the fault data into the shift register 1.

When the processor wants to know what fault data has been staticised it issues an instruction SNDFLTCD (send fault code) to the arrangement shown, where it is received by the control circuit 2. This circuit, in response to the reception and recognition of this signal SNDFLTCD initiates the following sequence of operations: (a) DATA ENABLE pulses are stopped so that the information collected in the shift register 1 is "frozen".

(b) SHIFT CLOCK pulses are generated, which shift the pattern of information in the shift register along it and also clock the counter 3.

(c) As a result of the SHIFT CLOCK pulses, the pattern in the register 1 progresses rightwards therealong until the first condition which represents a fault produces a logic 1 output at the FLTBIT output of the register 1.

(d) FLTBIT reaches the control circuit 2 over the connection shown, as a result of which the circuit 2 stops the SHIFT CLOCK pulses, with the result that the counter 3 has been stopped with its outputs giving a code which identifies the staticised fault signal.

(e) The control circuit now emits a DATA BUS ENABLE signal, which enables a set of highway gates 4 between the counter outputs and a multiwire highway which leads to the processor.

Thus the processor receives a code signal which identifies the first fault signal by the sequence of operations described above. In the present case this code is transmitted parallel~ wise, but in some cases serial transmission may be preferred. The processor may now issue another instruction, in which case the control circuit 2 causes the performance of the same sort of sequence as described above to cause the code for the next fault staticised in the register 1 to be sent out. The processor then continues in this manner until all fault conditions staticised in the register 1 have been transmitted over the highway.

Eventually the counter 3 reaches its last count, which produces a LASTCN T signal over the connection shown to the control circuit 2. This causes the control circuit 2 to stop the SHIFT CLOCK pulses, the code at the output of the counter 3 now corresponding to the last count and not to a fault. The control circuit 2 again generates DATA BUS ENABLE at the appropriate time, and the last count code is sent to the processor over the data highway. This last count code is interpreted by the processor as an "end of faults message" indication, and after its reception the processor generates a RESET signal. This, when received by the control circuit 2, causes the arrangement shown to be preferred for the next round of operation.

The control circuit 2 is not described in detail since it can follow established logic circuit design principles, and in any case its exact nature depends to some extent on the characteristics of the processor. It could, in fact, be a suitablyprogrammed micro-processor.

Earlier on in the specification it was mentioned that the fault collection arrangement described above is applicable widely, and in fact that it could be used in a chemical or other industrial plant. In such a case the circuit described can be modified by adding one or more further shift registers controlled in parallel with the shift register 1. These exact shift registers could then be used to store the values of the plant parameters. Hence when the central processor collects fault data it would also collect data on to current plant parameters.

In the specification we have indicated that wide use of the above described arrangements can be made, but at present use is in fact somewhat more limited in TXE4A.

Claims

1. A data processing system, which includes a number of checking circuits each of which produces a first output in the absence of a fault in the circuit which it checks and a second output in the presence of a fault in the circuit which it checks, a storage register having as its inputs the output connections from the checking circuits, so that the storage register by its contents indicates the fault conditions found by the checking circuits, a counter associated with said register and having a number of conditions at least equal to the number of fault indications which can be stored in the register, a control circuit for the register and the counter and responsive to a fault read-out signal from a remote processor to cause the data in the register to be stopped until a fault indication reaches a preset point in the register, connections from the control circuit to the counter so that the latter is driven in step with the register, means responsive to a fault indication in the register reaching said preset point to stop the counter, whose condition at the time of said stoppage identifies the fault, and an enable output from the control circuit which in response to the stoppage of the counter causes a representation of the counter's condition, which identifies the fault, to be transmitted to the remote processor, whereafter in response to one or more further signals from the remote processor operations including the stopping of the register and the driving of the counter are resumed so that all of the faults whose identities have been accumulated in the register are signalled to the central processor.

2. A system as claimed in claim 1, and in which the control circuit includes a microprocessor.

3. A system as claimed in claim 1 or 2, and in which the identities of the faulty circuits are sent to the remote processor parallel-wise.

4. A data processing system substantially as described with reference to the original drawing.

5. An automatic telecommunication exchange which includes a system as claimed in any one of claims 1 to 4.