GB2027242A - Improvements in or relating to alarm systems - Google Patents

Abstract

An alarm system for detecting unauthorised entry comprises a control circuit and at least one head circuit. The or each head circuit comprises an electro-acoustic transducer 1 whose output triggers a pulse-producing circuit such as a non-retriggerable mono-stable multivibrator 3 when a sound, such as a breaking window, is detected. The control circuit includes a counter 11 which receives output pulses from the pulse-producing circuit and means, such as a timer 12 for resetting the counter 11, for producing an alarm signal when the counter 11 reaches a predetermined count before the expiry of a predetermined period from an initial output pulse of the head circuit or circuits. The system is thus actuated by sounds such as the shattering of glass on the splintering of wood but is substantially insensitive to single sounds such as a bird flying into a window. <IMAGE>

Description

SPECIFICATION Improvements in or relating to alarm systems The present invention relates to alarm systems. Such systems may be used as burglar alarm systems for providing an alarm signal when an attempt is made to break into a building.

According to the invention, there is provided an alarm system comprising a control circuit and at least one head circuit, the or each head circuit comprising an electro-acoustic transducer whose output is connected so as to trgger a pulse-producing circuit for producing an output pulse when a sound is detected by the electro-acoustic transducer, the control circuit including a counter connected to receive the output pulses from the pulse-producing circuit of the or each head circuit, and means for producing an alarm signal when the counter reaches a predetermined count before the expiry of a predetermined period from an initial output pulse.

Preferably, the pulse-producing circuit comprises a non-retriggerable mono-stable multivibrator.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block circuit diagram of a head circuit of a preferred alarm system; Figure 2 is a block circuit diagram of a control circuit constituting a remote control unit of the preferred alarm system; Figure 3 is a circuit diagram of the head circuit of Fig. 1; and Figures 4 to 6 are circuit diagrams of the control circuit of Fig. 2.

The head circuit of Fig. 1 comprises an electro-acoustic transducer in the form of a microphone 1 connected via a frequency selective amplifier 2 to the trigger input of a non re-triggerable mono-stable multivibrator 3.

The output of the mono-stable multivibrator 3 is connected to a line driver 4 whose output is connected via a line 5 to the input of the control circuit of Fig. 2. A plurality of head circuits as shown in Fig. 1 may be arranged remotely from the control circuit with their outputs 5 connected to respective inputs of the control unit. The control circuit may thus, form a physically separate control unit. However, it may also be provided integrally with one or more head circuits.

The control unit shown in Fig. 2 comprises an input buffer 6 having a plurality of inputs 7 for connection to respective remote head circuits. A first output 8 of the input buffer 6 is connected to an oscillator 9 and is arranged to enable the oscillator when an open circuit is detected in any one of the lines connected to the inputs 7. A second output 10 of the input buffer 6 is connected to the output of the oscillator 9 and to a count input of a counter 11. The second output 10 is also connected to the input of a timer 1 2 whose output 1 3 is connected to the reset input of the counter 11. The counter 11 has an output 14 connected via a timer 1 5 to an output driver 1 6 for producing alarm signals.

The head circuit of Fig. 1 is shown in more detail in the circuit diagram of Fig. 3. The microphone 1 is connected via a network to the input of the frequency selective amplifier which comprises the three cascade-connected frequency selective amplifier circuits 2a, 2b and 2c. The gain of the first amplifier circuit is arranged to be voltage controllable and is controlled via a resistor 1 7 by a potentiometer 18. Coupling capacitors 19, 20 and 21 at the output of each of the amplifier circuits 2a, 2b, and 2c, respectively, have values such that the frequency selective amplifier amplifies substantially those frequencies above approximately 1 kilohertz.

The amplifier circuits 2a, 2b, and 2care built around three of the amplifiers of an integrated circuit operational amplifier device, the fourth amplifier 22 of which forms the non re-triggerable mono-stable multivibrator 3 of Fig. 1. The threshold level of the monostable multivibrator is determined by the potential divider comprising resistors 23 and 24.

The pulse width of the mono-stable multivibrator is adjustable by means of a further potentiometer 25 between 40 milliseconds and 400 milliseconds.

The output of the operational amplifier 22 is connected via a resistor 26 to the base of a transistor 29 whose collector is connected to a supply line 28. The base of the transistor 29 is connected to ground via a capacitor 261 and the emitter thereof is connected to ground via a resistor 30 and to the supply line 28 via two resistors 301, 302 connected in series. The emitter of the transistor 27 is connected via a resistor 31 to the supply line 28, and the base thereof is connected to the connection between the resistors 301 and 30.

The transistor 27 and associated components thus form a line driver, the transistor 27 acting as a constant-current source when the output of the amplifier 22 is low and being switched off when the output of the amplifier 22 is high. The resistor 26 and the capacitor 261 form a delay circuit in the positive feedback loop of the amplifier 22 so that the monostable multivibrator is triggered only after several cycles of the audio frequency signals.

Figs. 4 to 6 show in more detail the control circuit of Fig. 2. Fig. 4 shows the input buffer 6, which includes a plurality of input circuits (8 in the preferred embodiment) indicated to the left of a dashed line 32. Each input circuit comprises a transistor 33 whose base is connected via a potential divider comprising resistors 34 and 35 to a line and thence to a respective one of the remote head circuits.

The collector of the transistor 33 is connected via an AND gate to a set/reset bistable 36 whose output 37 is connected to a light emitting diode driver (not shown) for indicating which head circuit has been actuated.

Each of the input circuits include a resistor 38 connected between the collector of the respective transistor 33 and a common input of the remainder of the input buffer in the form of the base of a transistor 39. The collector of the transistor 39 is connected to the second output 10 of the input buffer and via a potential divider comprising resistors 40 and 41 to the base of a transistor 42. The collector of the transistor 42 is connected via a resistor 43 to a power supply line and via a capacitor 44 to a common line 45. The collector of the transistor 42 is also connected via a resistor 46 to the base of a transistor 47, whose collector is connected via a resistor 48 to the common line 45 and to the first output 8 of the input buffer.

Figs. 5 and 6 show in more detail the counter 11, the timer 12, the oscillator 9, and the timer 1 5 of Fig. 2. The counter 11 comprises a Johnson counter 49 in the form of a CMOS integrated circuit. Its count input 50 is connected via buffer stages comprising gates 51, 52, and 53 and transistor 54 to the output of a transistor 55 whose input is connected via a potential divider comprising resistors 56 and 57 to the second output 10 of the input buffer. The collector of the transistor 55 is also connected to the collector of a transistor 58 whose base is connected via a resistor 59 to the oscillator 9, which comprises a unijunction transistor 60, a transistor 61, a capacitor 62, and resistors 63 to 65.

The base of the transistor 61 is connected to the first output 8 of the input buffer.

A transistor 1 60 has its emitter-collector path connected between the base of the transistor 61 and ground, and its base connected via resistors 1 61 and 1 62 to the power supply line. The connection between the resistors 161 and 162 is connected via a resistor 163 to the base of the transistor 39 and the collector of a transistor 164, whose emitter is connected to ground. The base of the transistor 1 64 is connected via a resistor 1 65 to ground and via a resistor 1 66 to a keyswitch terminal 1 67.

The functions of the timers 1 2 and 1 5 of Fig. 2 are performed by a binary-counter 66 whose clock input is connected via a buffer 67 to the output of a clock generator including a transistor 68 and a unijunction transistor 69.

The outputs 70 to 73 of the counter 49 are connected to a socket 74, which allows selection of the above-mentioned predetermined number. A plug 74 for making this selection is connected to an input of an OR gate, whose output is connected to the clock enable input of the counter 49, and via a differentiating circuit comprising a capacitor 76 and resistors 77 and 78 to an input of an OR gate 79, whose output is connected to the reset input of the counter 66 and to the base of a transistor 80.

Outputs 81 to 84 of the counter 66 are connected to a socket 85 for selection of the timer period by means of a plug 86 which is connected to an input of a NAND gate 87 and to the input of a NOR gate 88. The other input of the gate 87 is connected to an output 89 of the counter 66 and another input of the gate 88 is connected via an inverter 1 88 to a plug 74'. A first input of a NOR gate 90 is connected via an inverter 91 and an integrating circuit comprising a resistor 92 and a capacitor 93 to the plug 74'.The output of the gate 88 is connected via a potential divider comprising resistors 94 and 95 to the base of a transistor 96, whereas the output of the gate 90 is connected to an input of an OR gate 97 whose output is connected to the reset input of the counter 49 and via an integrating circuit comprising a resistor 98 and a capacitor 99 to a second input of the gate 97. A second input of the gate 97 is connected to an output of an OR gate 100 which has a first input connected to a "switch-on presetting circuit" comprising a resistor 102 and a capacitor 103 connected in series between the power supply lines and a second input connected by the output of a NAND gate 101 and to an input of a NOR gate 11. First the second inputs of the gate 101 are connected to the outputs of gates 104 and 105, respectively, each of which has a first input connected to an output 106 of the counter 66.The gate 104 has a second input connected to the output of an integrating circuit comprising resistor 107 and capacitor 108. The gate 105 has a second input connected to the anode of a diode 1 09.

An output 110 of the counter 49 is connected to an input of a NAND gate 112. The "switch-on pre-setting circuit" is connected to a NOR gate 113. The gates 111 and 113 are cross connected to form a set-reset bistable whose output is connected to another input of the gate 75 and via an inverter 114 to a second input of the gate 12. The output of the gate 112 is connected via a diode 11 5 to a control input of the oscillator 9.

The cathode of the diode 109 is connected to the collector of the transistor 96 whereas the anode of the diode 109 is connected to an input of a NAND gate 116, which is cross connected with another NAND gate 11 7 to form a set-reset bistable. The anode of the diode 109 is further connected via a resistor 11 8 to one of the supply lines. An input of the gate 11 7 is connected to the output of a NOR gate 120, which has a first input connected to a second "switch-on presetting circuit" comprises a capacitor 1 21 and a resistor 1 22 and a second input connectible via a socket 1 23 to the emitter of the transistor 80.

The emitter of the transistor 80 is connected to one input of a NAND gate 124 whose other input is connected to the output of the gate 11 7 and whose output is connected via an inverter 1 25 to a reset input of the bistable 36. Another input of the gate 53 is connected via an integrating circuit comprising a capacitor 1 26 and a resistor 1 27 to the output of the gate 117.

An output 128 of the counter 66, the clock enable input of the counter 49, and the outputs 70 to 72 of the counter 49 are connected to an output socket 1 29.

The preferred system operates as follows.

When a sound is picked up by the microphone 1, it is supplied and filtered in the frequency selective amplifier 2 so that the output thereof contains substantially no frequency components below approximately 1 kilohertz. This signal is then supplied to the trigger input of the non re-triggerable monostable multivibrator 3. If the signal exceeds a certain threshold level, the output of the mono-stable multivibrator changes stage and cannot be re-triggered until the output pulse is finished and a recovery period equal to the pulse period has elapsed. This pulse period may be adjusted, between 40 and 400 milliseconds in the preferred embodiment, so that the alarm system is made less prone to false alarms.In particular, the pulse width can be adjusted so that, when a window pane is broken or a door frame is smashed, the sound continues for a sufficient time to produce several pulses, and therefore an alarm signal, whilst the system is insensitive to, for example, tapping on a window pane caused, for instance, by a bird flying into the pane.

When input pulses are supplied to the input buffer 6, the first of a series of pulses starts the timer 12 while the pulses are counted in the counter 11. When the timer 1 2 reaches a predetermined time, it produces a resetting pulse for the counter 11. If the predetermined count has been reached before the timer produces the resetting pulse, the output of the counter 11 will cause the output driver 1 6 to produce an alarm signal for a period determined by the timer 1 5. If the predetermined count has not been reached by the counter 11, the timer merely resets the counter so that the cycle can commence again.

If a break in one of the input lines to the input buffer 6 is detected, a signal is produced on the first output 8 which causes the oscillator 9 to supply pulses to the counter 11. The pulse rate of the oscillator 9 is sufficiently high to cause the counter 11 to reach the predetermined count before the timer 1 2 produces the resetting pulse, so that an alarm signal is produced indicative of tampering with the system.

The turn over frequency of the frequency selective amplifier 2 may be chosen to filter out sounds in frequency ranges other than those produced, for example, by shattering glass or splintering wood. The gain of the amplifier circuit 2a may be set by the potentiometer 1 8 so that the output of the amplifier stage 2cexceeds the mono-stable input threshold for a certain input sound level to the microphone.

Each of the input stages of the control circuit is arranged to invert the pulses supplied to its input, so that the pulses supplied to the base of the transistor 39 has a rising leading edge. The transistor 42 behaves as an inverter so that, in the absence of pulses from the head circuits, the collector emitter path of the transistor 42 short circuits the capacitor 44. Cutting of one of the lines from one of the head circuits causes the potential at the base of the transistor 33 to be reduced to zero. This results in the transistor 42 being turned off so that the capacitor 44 is charged up via the resistor 43. When the voltage across the capacitor 44 reaches a predetermined value, the transistor 47 switches off thus causing the signal at the first output 8 to fall to the voltage of the common line 45.

This causes the transistor 61 to be switched off, thus enabling the oscillator 9 comprising the uni-junction transistor 60 and associated components to produce a stream of pulses which are supplied to the counting input 50 of the counter 49.

Pulses supplied to the output 10 of the input buffer are also supplied to the counting input of the counter 49. the plug 74', by selecting one of the outputs 70 to 73 of the counter 49, determines the predetermined number of pulses necessary to cause the counter 49 to produce an alarm signal. When the selective output of the counter 49 goes "high", the clock enable input of the counter is inhibited to prevent further counting. Further a pulse is provided by the differentiating circuit comprising the capacitor 76 and the resistors 77 and 78 and this passes via the gate 79 to the reset input of the counter 66 and to the transistor 80. Thus, the counter 66 is reset and, if the socket 1 23 is set to select automatic reset, the bistable multivibrator 36 is reset.

The plug 74' is also connected via the integrating circuit comprising resistor 92 and capacitor 93 and via the inverter 91 to the gate 90 and via the inverter 1 88 to the gate 88. A signal is produced at the output of the gate 88 for a time determined by the one of the outputs 81 to 84 of the counter 66 selected by the plug 86. This signal is supplied via the transistor 96 and a diode 1 30 to an output terminal 131, which is connected to the output drive 1 6 (not shown in Fig. 6).

The clock pulse generator including the unijunction transistor 69 is allowed to oscillate after the first pulse of a sequence of pulses is received by the counter because the output 110 of the counter 49 causes the output of the gate 112 to go "high" and the diode 11 5 isolates the gate 11 2 from the clock pulse generator.

If less than the predetermined number of pulses are counted by the counter 49 by the time the output 106 of the counter 66 goes "high", a reset pulse is provided by the gate 97 for the counter 49 and another reset pulse is provided via the gate 79 to the reset input of the counter 66, the circuit operating as described above when the next pulse is received from a head circuit.

When the transistor 96 produces an output signal, the bistable multivibrator comprising the gates 116 and 117 is set so that the other input of the gate 53 is maintained "low". The gate 53 will thus pass no more pulses either as a result of a break in one of the lines or as a result of further sound. Thus, the alarm latches once it has been operated until the timer 1 5 resets the control circuit.

This resetting pulse is supplied to the transistor 80. If the socket 1 23 is in the "manual" position, the circuit remains latched. However, if the socket 1 23 is in the "automatic" position, a resetting pulse is provided via the gate 1 20 to the bistable comprising the gates 11 6 and 11 7. The gate 53 then allows further pulses from the second output 10 of the input buffer 6 or from the oscillator 9 to pass to the counting input of the counter 49.

Claims (9)

1. An alarm system comprising a control circuit and at least one head circuit, the or each head circuit comprising an electro-acoustic transducer whose output is connected so as to trigger a pulse-producing circuit for producing an output pulse when a sound is detected by the electro-acoustic transducer, the control circuit including a counter connected to receive the output pulses from the pulse-producing circuit of the or each head circuit, and means for producing an alarm signal when the counter reaches a predetermined count before the expiry of a predetermined period from an initial output pulse.

2. A system as claimed in claim 1, in which the pulse-producing circuit comprises a non-re-triggerable mono-stable multivibrator.

3. A system as claimed in claim 1 or 2, in which a frequency-selective amplifier is connected between the transducer and the pulseproducing circuit of the or each head circuit.

4. A system as claimed in claim 3, in which the frequency-selective amplifier has a high-pass characteristic with a turnover frequency substantially equal to 1 kHz.

5. A system as claimed in any one of the preceding claims, in which the alarm signal producing means comprises a bit output of the counter, on which is produced the alarm signal when the predetermined count is reached, and a timer connected so as to be started by the output pulses from the or each head circuit and arranged to produce a signal at the end of the predetermined period at an output which is connected to a reset input of the counter.

6. A system as claimed in any one of the preceding claims, in which the control circuit includes a timer arranged to be actuated when the alarm signal is produced and to maintain the alarm signal for a predetermined time.

7. A system as claimed in any one of the preceding claims, in which there is provided means for actuating the alarm signal when the connection between the head circuit or any one of the head circuits and the control unit circuit is tampered with.

8. A system as claimed in claim 7, in which the actuating means comprises an oscillator arranged to be started in response to a break in the connection, the oscillator having an output connected to the counter and a frequency of oscillation sufficiently high to cause the counter to reach the predetermined count before the expiry of the predetermined period.

9. An alarm system substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.