GB2079610A - Body-implantable electromedical apparatus - Google Patents

Abstract

A cardiac pacemaker includes a microprocessor 300 and a memory 302 capable of being programmed with a variety of processes for stimulating a heart and/of sensing and transmitting to an external device conditions of the heart or pacemaker. The microprocessor controls a multiplexer 306 to input signals from atrial and ventricular leads, the power source or a reed switch operable by an external magnet, on lines 338 a-f. The output comprises decoder 342 and latch 340 with output select switches 330 which are selectively operable to supply stimulation pulses to the leads or allow sensing. External apparatus 343 may transmit coded information to change the stored program or operation of the reed switch may select a different program starting address. The microprocessor 300 includes an address counter 307, and an auto reset oscillator circuit 344 periodically (e.g. every 0.5s) applies a reset signal to reset the address to the program starting address whereby if a noise signal (eg. from a defrillation pulse) causes an erroneous or meaningless memory location to be addressed the program will not 'hang up'. Reset circuit 344 is defeated during normal operation by a signal on line 346. <IMAGE>

Description

1 Body-lniplantable electromedical apparatus GB 2 079 610 A 1 This

invention relates to body-implantable electromedical apparatus such as internally implanted electronic devices adapted to be operated in a variety of modes for stimulating body tissue orto monitor various conditions of the device itself or of body tissue, e.g., the patient's heart.

Heart pacers such as that described in our U.S.

Patent No. 3,057,356 are known for providing electrical stimulus to the heart whereby it is contracted at a desired rate in the order of 72 beats per minute. Such a heart pacemaker is capable of being implanted within the human body and operative in such an environment for long periods of time. Typically, such pacemakers are implanted in the pectorial region or in the abdominal region of the patient by a surgical procedure, whereby an incision is made in such region and the pacemaker with its own internal power supply, is inserted within the patient's body. This pacer operates asynchronously to provide fixed-rate stimulation not automatically changed in accordance with the body's needs, and has proven effective in alleviating the symptoms of complete heart block. An asynchronous pacer, however, has the possible disadvantage of competing witlithe natural, physiological pacemaker during episodes of normal sinus condition.

An artificial pacer of the demand type has been developed wherein the artificial stimuli are initiated only when required and subsequently can be eliminated vilien the heart returns to the sinus rhythm. Such a demand pacer is shown in U.S. Patent No. 3,478,746 issued November 18, 1969 and entitled 35---CARDIACIMPLANTABLE DEMAND PACEMAKER". The demand pacer solves the problem arising in asynchronous pacers by inhibiting itself in the presence of ventricular activity (the ventricle's R wave), but by coming "on line- and filling in rn-issed-heart- beats in the absence of ventricular activity.

A problem with such prior art, implantable demand pacers is that there was no way to ternporarily increase or decrease the rate or other operating parameter at which these stimulating pulses are generated without surgical intervention. Still another problenn is the great difficulty in establishing the battery life remaining, in detecting and correcting a failing electrode, and in establishing an adequate R-wave sensitivity safety marghnin an implanted demand pacer.

Son L. irnplantable cardiac pacers presently conscructed have a rate overdrive capability but do not adequately cheek the viability of the demand func'don. Other devices are provided with a magnetic r, 5 reed syiitch arrangernrent which can deactivate 'the demand amplifierforihe purpose of checking u'le deiriand.i'uriction but are lacking in a rate overdrive capability.

[Anoiier in, proverrientirf hich has occurred since G reatbatch first disclosedthe implantable cardiac Pacei-iialcc-r is rneansto aiio,,sjthe pacema-kerto'be reprograrnmed aficer it has been implanted. In United States Patent 3,805,793 in the name of Reese Terry, Jr. et a[, entitled "Implantable Cardiac Pacer Having Adjustable Operating Parameters", which issued in 1974, circuitry is disclosed to allowthe rate of the pacemakerto be noninvasively changed after it has been implanted. The rate varies in response to the number of times a magnetically operable reed switch is closed. The Terry et al device operates by counting the number of times the reed switch is closed and storing that count in a binary counter. Each stage of the counter is connected to either engage or bypass one resistor in a serially connected resistor chain, which chain is apart of the FIC time constant controlling the pacemaker rate.

The concept of the Terry et al device has been improved upon by the apparatus shown in United States Patent 4,066,086 in the name of John M.

Adams et al, entitled "Programmable Body Stimulator", which issued in 1978, and which discloses a programmable cardiac pacemaker that responds to the application of radio frequency (RF) pulse bursts while a magnetic field held in close pro- ximity to a magnetically operated reed switch included within the pacemaker package holds the reed switch closed. In the Adams et al circuit, again onlythe rate is programmable in response to the number of RF pulse bursts applied. The use of radio frequency signals to program cardiac pacemakers was earlier disclosed by Wingrove in the United States Patent 3,933,005 entitled "Compared Count Digitally Controlled Pacemaker" which issued in 1974. The Wingrove device was capable of having both the rate and pulse width programmed. However, no pacemaker has ever been described which is capable of having more than two parameters programmed or selected features or tests programmed on command. Such a pacemaker could be cal- 10() led a universally programmable pacemaker.

One area where cardiac pacing technology has lagged behind conventional state of electronic technology involves utilization of digital electrical circuits. One reason for this has been the high energy required to operate digital circuits. However, with more recent technology advances in complementary metal oxide semiconductor (CMOS) devices fabricated on large scale integrated circuits, together with the improvements of cardiac pacemaker batteries, digital electronic circuits are beginning to be utilized in commercial pacemakers. The inherent advantages of digital circuits are their accuracy, and reliability. Typically, the digital circuit is operated in response to a crystal oscillator which provides a very stable frequency over extended periods of time. There have been suggestions in the prior art for utilizing digital techniques in cardiac stimulators and pacemakers since at least 1966. For instance, see the article by Leo F. Walsh and Emil Moore, entitled "Digital Tim- ing Unit for Programming Biological Stimulators" in The American Joumal of MedicalElectronics, First Quarter, 1977, Pages 29 through 34. The first patent suggesting digital techniques is United States Patent 3,557, 796 in the name of John W. Keller, Jr., et al, 12.5 and is entitled "Digital Counter Driven Pacer", which issued in 1971. This patent discloses an oscillator This speciuication as filed includes a corn puter pro, -gram which is not here reproduced.

2 GB 2 079 610 A 2 driving a binary counter. When the counter reaches a certain count, a signal is provided which causes a cardiac stimulator pulse to be provided. Atthe same time the counter is reset and again begins counting the oscillator pulses. Additionally, in the Keller et al patent, there is disclosed the digital demand con cept, in which the counter is reset upon the sensing of a natural heartbeat, and the digital refractory con cept, in which the output is inhibited for any certain time after the provision of a cardiac stimulating 75 pulse orthe sensing of a natural beat.

As mentioned above, digital programming techni ques are shown in both the Terry et al patent 3,805,796 and the Wingrove patent 3,833,005. Wing rove additionally discloses digital control circuitry for controlling the rate of the stimulating pulses by providing a resettable counter to continually count up to a certain value that is compared against a value programmed into a storage register. The Wingrove patent also shows provisions for adjusting the out put pulse width by switching the resistance in the RC circuit which controls the pulse width.

Other patents disclosing digital techniques useful in cardiac pacing include United States Patents 3,631,860 in the name of Micheal Lopin entitled "Var iable Rate Pacemaker, Counter-Controlled, Variable Rate Pacer"; 3,857,399 in the name of Fred Zacouto entitled "Heart Pacer"; 3,865,119 in the name of Bengt Svensson and Gunnar Wallin entitled "Heart beatAccentuated with Controlled Pulse Amplitude"; 3,631,860 in the name of Michael Lopin entitled "Var "Demand Pacer"; 4,038,991 in the name of Robert A.

Walters entitled "Cardiac Pacer with Rate Limiting Means"; 4,043,347 in the name of Alexis M. Renirie entitled "Multiple-Function Demand Pacer with Low Current Drain"; 4,049,003 in the name of Robert A.

Walters et a[ entitled "Digital Cardiac Pacer"; and 4,049,004 in the name of Robert A. Walters entitled "Implantable Digital Cardiac Pacer Having Externally Selectable Operating Parameters and One Shot Digi tal Pulse Generator for Use Therein".

Though it has been suggested that various para meters, i.e., pulse width and rate, may be changed within an internally implanted pacer, it is desired to provide a device that is capable of operating in vari ous, different pacing and/or sensing modes. The sys tems of the prior art are capable of storing by means of digital counter circuitry a programmable word indicative of desired rate or pulse width. In an inter nally implanted device, the space to incorporate a plurality of such counters whereby a number of such functions could be programmed, is indeed limited.

Further, there are considerations of the available energy to energize such counters, as well as of the life of its internal power source as a result of the imposed drain. It is well recognized in the art that the complexity of the circuit incorporated within an internally implanted device is limited by many fac tors including the drain imposed upon the battery and therefore the expected life of a battery before a surgical procedure is required to replace the device's power source, e.g., a battery.

We have proposed a body-implantable electrical stimulating and sensing apparatus comprising con trol means including a control processor and memory means, the control processor having address means for addressing a program stored within a selected storage portion of the memory means and the memory means having at least first and second storage portions for storing different first and second programs respectively, first and second select switch means arranged to be controlled by the processor and connected respectively to first and second lead means, which lead means are arranged to provide stimulating signals to body tissue andlor supply sensed signals to the control means, and means for selectively changing the address of said address means, whereby said address means applies a starting address to one of said first and

Claims (3)

second storage portions to effect the execution of said first or second program. Such apparatus is claimed in our copending application serial No. 2026870 and provides increased flexibility and adaptability of an internally implanted device, whereby a plurality of processes including tissue stimulation and telemetry may be effected. The apparatus provides an adaptable, multi-purpose implantable pacemaker capable of being programmed before or after implantation to effect a different process of stimulation (or telemetry) dependent upon the patient's present condition. It also enables the provision of an internally implanted electrical device having a communication linkto transmit signals from and to a transmitter external of the patient's body, whereby control signals may be transmitted to change the process effected by the internal device and data concerning tissue (heart) activity, as well as functions of the implanted device, may be received from the internal device. It has been found that extraneous noise such as generated by a defibrillation pulse or other source could affect the address means, e.g. an address counter, and cause it to address a meaningless or erroneous location within the memory means. According to the invention, there is provided body-implantable electromedical apparatus including memory means for storing a program of instructions and a microprocessor for executing the program, the microprocessor including address means for addressing the memory, wherein there is included resetting means coupled to said microprocessor for periodically generating a reset signal to reset said address means to a predetermined return. address, whereby if said address means inadvertently addresses a meaningless location in said memory means, the execution by said microprocesor of a sekected program within said memory will be continued by addressing the predetermined return address within the selected program. In the preferred embodiment there is provided an auto-reset oscillator circuit that is designed to reset the addressing mechanism or register of the microprocessor, whereby if an extraneous noise signal is effective to cause the address registerto address a vacant or erroneous location within the system's memory, the process will not be "hung up", but rather will be reset after a predetermined interval to start the process over again. Preferably said microprocessor includes means coupled to said reset means for periodically generat- k 3 :tc 1 ing and applying a defeat command signal to said reset means to defeat the operation of said reset means if said address means is operating correctly. If the addressing mechanism is functioning nor mally, the microprocessor provides an inhibit signal 70 periodically to the auto-reset oscillator circuit pre venting it from applying a resetto the addressing means. Certain embodiments of the invention will now be described by way of example and with reference to the accompanying drawings, in which: Figure 1 is a pictorial view of the manner in which a programmable pacemaker of the subject invention is implanted within a patient and used; Figure 2 is a functional block diagram of an inter nally implanted pacemaker, as generally shown in Figure 1. Figure 2 does not show the novel feature of the invention but is useful for a detailed understand ing of the environment in which theInvention may be employed; Figure 3A shows a circuit diagram of the particular interconnections from the pacemaker of Figure 2 to the patient's heart to implement a ventricular demand mode of pacing and sensing; Figure 313 is a circuit diagram showing the interconnections from the pacemaker of Figure 2 to the patient's heart.to implement an A-V sequential pacing of the patient's atrium and ventricle; Figure 3C is a circuit diagram of the interconnec- tion from the pacemaker of Figure. 2 to the patient's atrium and,., erglaicietoimplc-n-Qentancitrial,syrehronous, ventricular inhibited pacing (ASW1) rnode; Figure 4A is a timing diagram of ' lie activation of the st,,iitchL-s and elements ofthe circuitof Figure 3A io implement a ventricular dernand pacing model r-igure4Bisatiniingdiagran ofthe actuation of the switches and elements of Figure 2B to iniplemerit a bifocal pacing mode; Figure 4C is a timing diagrarn of the actuation of 1.0 the switches and elements ofFigure SC to Implement an ASVIP mode; Figure 5 is a flow diagram of one of a plurality of programsto be stored within the memory of the pacemaker shown in Figure 2, to implement a ven1.5 tricular demand mode of pacing in accordance with the timing diagram of Figure 4A; Figure 6 is a functional block diagram of a further embodiment of the pacemaker of this invention; and - Figures 7A and B are detailed circuit diagrams of two specific, illustrative embodiments of the 115 pacemaker shown generally in Figure 6. Referring now to the drawings and in particular to Figure 1, there is shown a pacemaker adapted to be programmed in a variety of modes in orderthatthe patient's heart including its atrium 40 and its ventricle 42 may be placed in a variety of modes and further, to sense the electrical activity of the patient's atrium and ventricle (or other body tissue) for either modifying pacemaker pacing parameters or for transmission remotely o fithe patient's body 14. In particular, the pacemaker 12 includes a body tissue and lluid resistant casing Llead17 1: raf coupled to and attached by arm electrode -'9 'lie h a a rt, S '12 c ri I-gri 140, a E-1d a c. cc e nc-, l c c d 1 S, cc,:, p e d, and tby an G B 2 079 610 A 3 cle 42. Further, there is shown an external transmitter 10 cou pled by a lead 15 to a coi 1 o r anten na 16 disposed externally of the patient's body 14, for.ransmitting RF coupled signals to the internally implanted pacemaker 12. Further, there is shown a monitor 63 coupled to the transmitter 10 by a lead 59. As will be explained in detail, the transmitter 10 may be actuated to send signals via the lead 15 and the coil 16, to the internally implanted pacemaker 12, whereby its mode of operation may be changed from one mode to another selected mode; thus, the physician can control the type of pacing imposed upon the patient's heart in accordance with the patient's altered condition. It is understood that at the time of the surgical implantation of the pacemaker 12 within the patient's body 14, that a particular mode of pacing may be desired. Subsequeritto the implantation, the patient's condition may change at which time another mode of opera- tion may become desired. Further, it is desired to transmit from the patient's body a variety of signals indicative of various conditions to be sensed and transmitted by the coil 16 and the transmitter 10 to be displayed upon the monitor 63. In addition, as shown in Figum 1, the internally implanted pacemaker 12 rnay include a further output and lead 25 coupled to a transducer 27; the transducer 27 may be of a mechanical type for sensing motion of a body organ. In add, Lion, the pacemaker 12 may have a further output and lead 21 coupled to amagnetically actuatable reed sv,, ritch 23 that may be actuated by the physi--ian by bringing an external magnet adjacent thereto to close the switch 23 to effect a change in the operation of the pacemaker 12. Lead 29 is illus- trative of a piuraHly of leads that may be coupled to various sites of the patient's heart in order to provide, for example, stimulation that would defeat an arrhythmia or to provide redundant leads to repizice, a defective lead 17 or 19. With reference to Figure 2, there is shown Ea fun tional block diagram of the pacemaker 12. which includes as its central control element a microprocessor 100, and a multiplexer 106 for receiving analog data from a first input 138a coupled via the 1 10 first lead 19 (see Figure 1) to the patient's ventricle 42 and a second input 138b coupled via the second lead 17 to the patient's atrium 40 (see Figure 1). These various analog (and digital) inputs are selected by the multiplexer 106 under the control of the microprocessor 100 in a selected manner and processed according to processes or programs stored in the memory 102. In addition, the microprocessor 100 is coupled by an address bus 112 to memory 102, whereby addresses as stored and incremented by an address col inter 107 are applied to address selected locations.%,ithir, the memory 102. The addressed data is transferred from the memory 102 via data bus 110 to the microprocessor 100. In addition, there are additional inputs 138c, cl, e and f of the multiplexer 106. The microprocessor 100 provides control signals via an input select bus 120 to the multiplexer 106, whereby one of the inputs -Ln-:ts selected for application via the conduit ep and to d:gital 4 converter 108 and the bus 114 to the microprocessor 100. As suggested in Figure 2, the output voltage Vs of a power source 126 is coupled via input 138c to the multiplexer 106 in orderto appropriately modify the pacer performance as a function of power source 70 variations. For example, it is desired to increase the pacing pulse width as supply voltage decreases to create a more constant energy pulse, orto slow the pacing rate as supply vontage decreases to indicate a need for pacer replacement or modification via external programming. The spare inputs 138d and 138e may be coupled illustratively also to the ventri cle 42 and the atrium 40 in order to redundantly sense the activities of these portions of the heart. It is contemplated that the microprocessor could choose 80 which of the inputs 138a, b, d and e that would pro vide the most efficient sensing of the atrial.and ven tricular signals, or require the least power from the power source 126, or most effectively breakup a car diac arrhythmia. Further, the input 138f may be con- 85 nected by the lead 21 to the reed switch 23, whereby the physician may dispose an external magnet to close the switch 23, whereby the microprocessor 100 is controlled to change or after the program as stored in the memory 102. The multiplexer sequentially selects or steers one of the inputs 138a to f via con duit 118, which is inputthrough an amplifier and analog to digital converter 108 and the conductor 114 to the microprocessor 100. Multiplexing is used in order to reduce the hardware required for proces- 95 sing the analog information applied to the inputs 138a to f and also to reduce the power requirements for this function. Without the multiplexer 106, each of the inputs 138a to f would require its own indi vidual scaling, amplifier and AID converter 108. Thus, the use of the multiplexer 106 reduces the power drain applied to the power source 126 as well as reduces the circuitry to be incorporated within the pacemaker 12. The microprocessor 100 applies via conduit 116 a scaler control signal to the scaling amplifier and A/D converter 108, whereby the scaling factor or gain of the amplifier within block 108 is controlled to accomodate for the various amplitudes of signals applied to the inputs 138a to f of the multiplexer 106. In this regard, it is understood that the output of the power source 126 could be illustratively in the order of 1.3 to 6 volts (initially), whereas the heart activty signals derived from the atrium 40 and the ventricle 42 would be illustratively in the order of 1 to 20 millivolts. The output of the amplifier and A/D converter 108 is a set of digital signals that are to be stored within the microprocessor 100 and in particular within the registers of the microprocessor 100. In a preferred embodiment of this invention, the microprocessor 100 could also be implemented by presently available low threshold CMOS technology, which implementation would providia relatively low power drain upon the power source 126. An essential element of the pacemaker 12 is the memory 102 which may include a non-volatile section, i.e., the read-only memory (ROM) portion 102a and a volatile portion, i.e., the random access memory (RAM) portion 102b. In the ROM or non-volatile portion 102a, the basic steps of each of a variety of GB 2 079 610 A 4 pacing modes (or other processes) are stored. On the other hand, a variety of parameters or whole programs are stored in the RAM portion 102b, and at a later point in time could be reprogrammed dependent upon the changing condition of the patient. The memory 102 may be programmed at the time of manufacture, before implantation within the body 14 of the patient, or via an external memory load interface 104, that is coupled by an RF frequency or acoustical link 105 to the memory 102. In an illustrative embodiment of this invention, a link as described in U.S. Patent Nos. 3,833,005 and 4, 066,086 (more fully identified above), may be readily adapted to be used as the interface 104. In particular, there is described a receiver filter for sensing bursts of RF pulses transmitted from an external transmitter, the bursts being coded in a mannerto reprogram a program stored within the memory 102 or alternatively, to change a parameter stored within a memory location of the memory 102. Thus, after the pacemaker 12 has been implanted within the body 14 of the patient, the physician upon observing a change in the patient's condition, may reprogram the program or specific variables of a program stored within the RAM portion 102b to most appropriately pace the patient's heart for his changed condition. Specifically, it is noted that there are various parameters of pacing such as the pulse width of the stimulating pulse, the rate or frequency of pulse application, the period between the application of a pulsing signal and the detection of the responsive heart activity during which the sensing apparatus is defeated, and the pulse amplitude. Typically, each of these parameters is determined by, for example, an eight bit word stored in a word location of the RAM portion 102b of the memory 102. Thus, if it is desired to change the pulse width, the physician may readily enter via the interface 104 and conduit 105 into a known, addressable word location within the RAM portion 102b, a new eight bit word indicative of the new pulse width at which the pacemaker 12 is desired to pace. It is contemplated that a new mode of pacing may likewise be programmed within the RAM portion 102b by inserting via the interface 104 Ibe steps of the new process. Alternatively, a mode change may be effected by inserting the starting location of the desired program from the RAM portion 102b within address counter 107 of the microprocessor 100 to initiate the addressing of the next program within the ROM portion of memory 102. For example, if the initial mode of operation of the pacemaker 12 is ventricular demand pacing and it becomes desired to initiate an A-V sequential pacingmode, the physician enters the new starting address of the A-V sequential paging mode via the interface 104 to access a different portion of the ROM portion 102a, whereby the microprocessor 100 initiates the operation of the next mode. As will be explained in detail later, it is desired to maintain constant the energy of each stimulating pulse applied to the patient's heart, even though the voltage level of the power source 126, e. g., a battery, decreases with life. As indicated in Figure 2, the multiplexer 106 periodically applies the battery voltage V, via the input 138c to the microprocessor 100, t GB 2 079 610 A 5 which underthe control of a program stored in the memory 102 comparesthe measured voltage with various predetermined voltages stored in the ROM portion 102a or the RAM portion 102b whereby an adjustment in the pulse width of the stimulating pulse is made to maintain substantially constant the energy content, i.e., the area underneath the curve of the stimulating pulse. Further, it is contemplated thatthe memory 102 may be loaded with a program that is in effect selfchoosing. In otherwords, such a program could be responsive to the heart's signals as applied to the inputs 138a and b to sense the condition of the heart and to choose one of a plurality of programs depen- dent upon the sensed condition. The distinguishing characteristics of the atrial P wave and ventricular R - wave input signals are more fully described in the publication, entitled "Electrocardial Electrograms and Pacemaker Sensing" by P. Hoezier, V. de Caprio and S. Furman and appearing in Medical Instrumentation, Vol. 10, No. 4, July, August, 1976. In this regard, the criteria with which these heart signals are to be recognized and compared, is stored within the memory 102 and if a change is noted, the microp- rocessor may automatically select a different mode of pacing appropriate for the changed conditions of that patient's heart without the need for external intervention by a physician through external memory lead interface 104. In a further mode of pacing, it is contemplated that the memory 102 of the pacemaker 12 may be programmed to operate as an automatic threshold following pacemaker, whereby the energy of the stimulating pulses applied to the patient's ventricle 42 (or atrium 40) may be decreased incrementally until capture is lost, i. e., the stimulation pulses fail to elicit a responsive ventricular contraction evidenced by an R wave sensed within a sensing period. In this mode, if the R wave is sensed within the period, a control signal is developed to decrease the pulse energy level by a given incremental amount. In particular, the pulse width is decreased until no pacemaker elicited R wave is sensed at which time the program increases the pulse width until the R wave reappears. In this fashion, the power drain placed upon the power source 126 is minimized in thatthe pulse width is adjusted for a level just sufficientto - maintain capture of the patient's heart. - Continuing with respect to Figure 2, the control output signal's of the microprocessor are applied via conduits collectively shown by numeral 131 to latch driveis 134 and by bus 132 to corresponding select switches 130, which provide appropriate pacemaker pulses via the leads 17 and 19 (or 29) to the atrium 40 and ventricle 42 of the patient's heart in accordance with the processes stored in the memory 102. In particular, conduit 131 a is coupled to a first or ventricular driver (or amplifier) 134a, which is in turn coupled to its own set of bipolarlunipolar select switches 130a. It is understood that each of the driver ampiifiers 134b, c and d is also associated with a similar set of select switches. For example, the output of driver 134b is connected to select switches 130b for driving the patient's atrium via conduits 17a, 17b and 17c. It is also understood that the drivers 134a-1 34d may include voltage increase circuitry, e.g., doublers, triplers, to raise the output voltage level to that necessary to effectively stimulate the heart tissue with a given power source voltage. The select switches 130 are under the control of signals derived from the microprocessor via bus 132 to selectively couple the output of the first driver 134a between selected of the outputs 19a, 19b, and 'I 9c. In this regard it is understood that the switches 130 are coupled via the ventricular lead 19 which may take the form of a coaxial lead connected to a tip electrode via conductor 19a and to a ring electrode 19c, as more fully shown and explained, for example, in our U.S. Patent 4,010,758. In addition, there is pro- vided a conductor 'I 9b coupled to a plate formed of the metal container or can 13 in which the pacemaker 12 is encapsulated. In normal bipolar operation, the select switches 130 connectthe negative and positive stimulating pulses via the conduc- tors 19a and 19c of the coaxial lead tothe tip and ring electrodes, respectively. If it is desired to pace in a standard unipolar mode, a negative voltage is applied via the conductor 19a to the tip electrode and a positive voltage via the conductor 19b to the plate, with the ring electrode not connected. In addition to being able to pulse in bipolar or unipolar mode, it is desired to provide a fault tolerant pacemaker whereby if it is detected that there is a faulty lead due to an improper connection of an electrode lead to the heart tissue orto the breakage or damage of a lead, the microprocessor 100 responds to provide suitable control signals via the bus 132 to the select swtiches 130, whereby a different combination of leads (or conductors of leads) are selec- tively coupled to apply the pacing pulses to the ven tricle 42. For example, the select switches 130 may be arranged to interconnect the tip and ring leads 19a and 19c together. Alternatively, the select switches 130 are selectively closed to apply the heart pulse between either one of the tip lead 19a or plate lead [9b and the ring lead 19c, whereby in the event of failure of one of the leads 1 9a or b the other could readily be used in its place and still apply the pulse across two sites of the patient's heart. Failure of one of the leads 17 or 19 can be detected by loss of capture, i.e., failure to note a heart activity signal at the input 138b after the pacing of the ventricle. Alternatively, measuring a high impedance between the conduits l ga and 'I 9b of the coaxial lead 19, indicates the failure of the lead due either to the build-up of scar tissue between one of the tip or ring electrodes and the ventricle 42, or the breaking of one of its conduits 19. Upon detection of such a failure, the microprocessor 100 selects a different one of the processes or programs stored within the memory 102 to apply signals to one of the select switches 130 to cause a re-connection of the leads 19a ' or 29) in a manner as illustrated above. An output of the microprocessor is also coupled to E. second or atrial stimulating amplifier 134b whose output is coupled to a further set of select switches 130 to be coupled via a corresponding set of leads 17 to the patient's atrium 40, as shown in Figure 1. In addition, there are included spare amplifiers 134c and 134d, which receive outputs of the microproces- 6 GB 2 079 610 A 6 sor 100 and are coupled to furthersets of select switches 130. It is contemplated that such sets of select switches 130 may be coupled by redundant leads to the patient's heart. For example, the outputs of the amplifiers 134c and 134d could also be coupled redundantly to the ventricle and atrium 42 and 40 of the patient's heart. If one of the leads 19 or 17 broke or the resistance between its electrode and the patienl!s heart became excessive, a redundant lead could be coupled in circuit between the microprocessor 100 and the patient's heart by appropriate activation of the corresponding set select switches 130. To measure the impedance as presented by one of the leads 17 and 19, it is noted that such a lead is coupled to an output circuit, as will be described with respect to Figures 3, including a charging capacitor and that an indication of the charging time of such capacitor is an indication of the impedance presented by the associated lead. In operation, the output capacitor is charged, and after charging, the output circuit is actuated to effect a discharge of the capacitor whereby a stimulating pulse is applied via the associated lead to the patient's heart. It is contemplated thatthe period required to charge the output capacitor be timed, by initiating a counter effected by a program within the memory 102, the counting continuing until the charged voltage level upon the output capacitor reaches a predetermined level. Thus, the voltage level of the capacitor will be repeatedly measured underthe control of the microprocessor 100 and if not above the predetermined level, the counting operation will continue. When the charged voltage of the capacitor has reached the predetermined level, the counting operation ceases and that count is used as an indication of the impedance of the lead. If the lead is open, the impedance of the lead will be high thereby causing the charging time period to be greater, whereas if the lead is shorted out, the time period will be relatively short. Thus, first and second time limits are established to determine whether the lead is shorted or its impedance is too high corresponding to a break of the lead. In either case, these limits, taking the form of time counts, are checked and if exceeded, a second, redundant lead is substituted for the defective one. The spare drivers 134 may be provided in orderto provide stimulation to a plurality of different sites, e.g., 5, in orderto break up arrhythmias that may be sensed by the pacemaker 12. Alternatively, the addi- tional drivers 134c and d may be used to discharge polarization voltage on the leads 17 and 19 after pacing or used quickly to charge the output capacitor for high rate pacemakers. Arrhythmias may be detected by measuring the delay between the electrical activ- EiEi- ity of a first heart site, e.g., the atrium, and the detection of heart activity at a second heart site, e.g., the ventricle. If the delay is less than a predetermined period, e.g., 100 to 200 milliseconds, there is an indication of a possible arrythmia. Arrhythmias are primarily caused by the occurrence of a second competing ectopic focus within a patient's heart, that beats in competition with the primary focus typically eccurring in the patient's atrium. The two centers of beating compete with each other to produce arrhythmia, whereby the heart!s activity becomes erratic and does not pump blood efficiently. In an illustrative embodiment of this invention, it is contemplated that a plurality of electrodes, each coupled to an amplifier 134 and a select switch 130 is coupled to a corresponding number of selected sites of the patient's heart. One such lead is selected to apply stimulating pulses to the patient!s heart, the remaining leads being coupled to sense the resultant heart activities atthe remaining sites. Time windows are established by a program stored within the memory 102 for each of the four leads in which to receive heart activity signals and if the signals are not received within the time windows, there is an indication of possible arrhythmia. If a detected signal, is not within its window, a different one of the pluralitV of leads is selected to apply the stimulating pulses, and the remaining leads sense the resultant heart activity signals. If the sensed signals do not appear within the timing windows, afterthe selec- tion of the new stimulating lead, a different lead is then selected. If the arrhythmia is not brought under control by this action, the program is designed to apply stimulating pulses to all of the leads to bring the heart's activity under control. The timing periods in which to receive the heart activity signals, are established in a manner as explained below with respect to Figures 4 and 5. It is evident by the above description, that the pacemaker 12 is an exceptionally flexible, adaptive device permitting correction or compensation for a variety of factors such as sensing difficulties, power source voltage variations with respect to time and unforeseen noise sources. For example, processes or programs are loaded into the memory 102 for sensing the R waves based upon such major features as the slope of the EKG signal, the pulse width of the R wave from the patient's ventricle 42, the amplitude of the R wave, the similarity of the R wave to a previous EKG complex, etc. In addition, the memory 102 is programmed to ignore extraneous AC noise sources or to ignore or to filter out extraneous muscle signals. The advantages of such an adaptable pacemaker 12 permit a single pacemaker to be provided that is capable of being programmed in a variety of operations and to be continuously reprogrammed as technology changes. From a manufacturing point of view, it is no longer necessary to modify each hardwire circuit to develop separate hydrid circuits which differ from each other by minor features for example, a change of the inpt filter, pulse width or pulse rate. A further advantage of the pacemaker 12 of Figure 2 is that it eliminates ' the use of a major source of failure, i.e., the rate and pulse width timing capacitors within prior art, hardware implemented pacemakers. At present, hardwire pacemakers utilize a resistor/capacitor charging scheme to accomplish the desired timing functions, such as pulse width, pulse rate and refractory timingExperience indicates that capacitors can be a major source of failure in such circuits. In this embodiment of this invention, the microprocessor 100 may take the form of a processor as manufactured by RCA Corporaton under their designation "CDP 1802 COSMAC" microprocessor V30 or the "CDP 1804 COSMAC" microprocessor (prO- 7 cessing on-chip memory). As explained above with respectto Figure 2, each of the drivers 134 is connected to its own set of select switches 130, whereby a stimulating pulse is applied by one of the leads 17 or 19 to a corresponding part 70 of the patient's heart. Additionally, the multiplexer 106 applies a selected signal derived by the leads 19 and 17 from the ventricle 42 and atrium 40 to the microprocessor 100. In Figure 3A, there is shown an illustrative arrangement of driver amplifiers 134 and 75 select switches 130 to apply the stimulating pulses via the lead 19 to the patient's ventricle 42 to effect a ventricular demand mode of pacing, the timing intervals of which are shown in Figure 4A. The num- 1,5 erals used to designate elements of Figure 3A correspond to those numerals as shown in Figure 2 to - designate like elements or blocks. In particular, a pacemaker output circuit is comprised of an output transistor Qv for coupling the voltage on capacitor Cv selectively to the ventricle 42 via the lead 19. In par- 85 ticular, an output control signal T of the microp rocessor 100 is coupled via conductor 131 a, amp lifier 134a, resistor Rv2 to the base of transmitter Q,, rendering it conductive. As a result, the previously charged capacitor Cv is discharged to ground, apply- 90 ing a stimulating pulse of a pulse width corresponding to that of signal T^ via lead 19 to the patient's ventricle 42. The select switch 130a is closed for a selected period by the control signal Tcv applied via bus 132 to recharge the capacitor Cv in the interval between successive control signals Tw, Thus, the control signal T selectively renders the transistor Qv conductive and nonconductive whereby corresponding series of stimulating pulses are applied via the lead 19 to the patient's ventricle 42. In the unipolar pacing mode, the plate or con tainer 13 of the pacemaker 12 is connected to the other terminal of the battery. As shown in Figure 3A, the ventricular lead 19 is also connected via conductor 138a to the multiplexer 105 and in particular to a switch 106a', which is closed in response to the tiffling window signal Ts thereby applying a signal indicative of the heart's ventricular activity via the amplifying and AID circuit 108 to the microprocessor 100. In particular, the ventricular lead 19 is coupled via the conductor 138a, the capacitor Cl and resistors Rl and R2 and amplifier 139to the multiplex switch 1OW. In comparing the functional block diagram of Figure 2 and the circuitry of Figure 3A (and Figures 313 and C), it should be noted that there is not a precise correspondence between the elements of these figures. Though it is indicated that certain switches notably switch 106a' is a part of the multiplexer 106, there is a difference in the circuits in that the circuit of Figure 3A (and 313 and C) includes sense amplifiers, e.g., ventricular sense amplifier 139, whereas the multiplexer 106 of Figure 2 applies a selected one of a plurality of analog inputs to a single amplifier 108. Thus, it is contemplated that the various switching functions shown illustratively in Figure 3A (and Figures 313 and C) are illustratively shown therein and could be implemented in varying manners; for example, the multiplex switch 106a'could be implemented by a select switch 130. The point of interconnection bet- GB 2 079 610 A 7 ween the resistor R2 and Rl is coupled to ground via capacitor C2. As will be noted with respect to Figure 4a, it is desired to clamp the amplifier 139 to ground during certain periods, i.e., the refractory period, in which it is not desired to sense the ventricular signal. To this end, a timing signal Tc,v is applied via the conductor 120 to a select switch 130c, whereby the point of interconnection between the resistors R2 and Rl is coupled to ground for the refractory period. The circuit formed of resistors Rl and R2, and capacitors Cl and C2 serves as a coupling circuit between the ventricular sensing amplifier 139 and the patient's heart. In particular, when the multiplex switch 106a' is closed coupling the input of the ven- tricular sensing amplifier 139 to ground, it is desired to provide isolation between ground and the patient's heart, otherwise significant damage could be caused to the patient's heart. To this end, resistor Rl and capacitor Cl are inserted between ground and the patient's heart. In addition, capacitor C2 functions as a low pass filter of noise that may be present upon the lead 19, as well as to soften the closing action of the select switch 130c. It is contemplated that the ventricular sensing amplifier may take the form of a well-known operational amplifier, and resistor R2 is coupled to its input in order to set its gain in a manner well known in the art. In Figure 4A, there is shown a timing diagram of the ventricular demand pacing mode corresponding to the output/input connections of Figure 3A, by which the system of Figure 2 is adapted to pace the patient's ventricle 42. At time t,), a ventricular pacing pulse has just been applied via lead 19 to the patient's ventricle 42. Thereafter, the RV amplifier 139 is clamped to ground by closing the select switch 130c forthe refractory period from t. to t, Also during the refractory period, the capacitor C, is recharged by applying the control signal Tc, to close the select switch 130a, whereby the potential of V, is applied to and recharges the capacitor C, Typically, the refractory period is in the order of 325 milliseconds at the time the pacemaker 12 is implanted within the patient and the battery or potential power source 126 is fresh. During the refractory period, the heart activity of the ventricle 42 is not sensed in that various noise or extraneous electrical signals may be present within the ventricle 42 that are not desired to be sensed. After the refractory period beginning at time tl, the select switch 130c is opened and the switch 106a' is closed, whereby if the heart generates an R wave signal that would be applied via lead 19, conductor 138a, the ventricular amplifier 139 and the closed switch 1OW, the microprocessor 100 responds by resetting the timing cycle to t, The occurrence of the R wave signal from the ventricle 42, indicates thatthe heart activity is normal and that it is not desired to apply a competing stimulating ventricular signal. Thus, as long as the patient's heart, generates an R wave signal, the pacemaker 12 will not generate a ventricular pacing signal. However, if after the expiration of the sensing period from t, to t2 without sensing an R wave, the microprocessor 100 will generate a timing signal T that is applied via conductor 131 a, amplifier 134a, resistor RWtO the base of transistor Qv, whereby the transis- 8 GB 2 079 610 A 8 tor Qv is rendered conductive causing the capacitor Cvto rapidly discharge through the heart load (represented by resistance RJ thereby causing a pacing pulse to be applied via leads 19 and 13 to the ventricle 42. During the pacing period from t2 to t3, the ventricular amplifier 139 is clamped to ground by the closed switch 130c. It is understood from the above discussion thatthe various periods corresponding to the pulse width of the ventricular pulse between timest2and t3, the refractory period between to and t, may be adjusted or reprogrammed by entering new eight bitwords into the memory 102, as shown in Fig u re 2. There is shown in Figure 5 a flow diagram of the steps for implementing ventricular pacing. in a demand mode, the timing diagram of which is shown in Figure 4A, and the output and input circuit connections are shown in Figure 3A to the pacemaker 12 as shown in Figure 2. In one illustra- tive embodiment of this invention, the microprocessor 100 includes a plurality of pointer registersfor storing pointers or addresses to word locations within the ROM portion 102b of the memory 102. In this illustrative embodiment, there are included within the microprocessor 100 the following registers for storing the indicated pointers or addresses: R(O) = Program Counter (PC) 11(3) = Loop Counter (LC) R(4) =Time Counter (TC) R(A) =Output State Table Pointer (QP) R(B) = Time Duration Table Pointer (TP) R(C) = Voltage Transition Point Table Pointer NP) R(D) = Refractory Time Pointer (TR) R(E) = Input Pointer (VDD) Further, the flag inputs for the reed switch (EF2) and the R wave (EF1) are applied to the microprocessor as will be explained with regard to Figures 7A and 7B. The notation forthe flag inputs and the pointers and counters is used throughoutthe program listing set out below. As is conventional with microprocessors, the microprocessors 100 includes the address counter 107 which increments one for each step of the program as it is carried out under the control of the microprocessor 100 to designate the next location within the memory 102 from which information is to be read out. The steps to be explained with respect to Figure 5 to effect a ventricular demand mode of pacing, were implemented in an RCA COS- MAC microprocessor by the following machine instructions:

1 9 GB 2 079 610 A 9 Memory Symbolic Memory Step Address Notations Contents Remarks Location (Hexadecimal) (Hexadecimal) 00 0000 D = 00 200 01 LDI F8 202 02 00 00 202 03 PHI,3 B3 202 04 PLO, 3 A3 Set LC=0 202 GLO, 3 83 R(3)--->D 204 06 BNZ 3A Is LC=00 204 07 OUTPUT 3D No? Go to 204 OUTPUT State Memory Address 3D 08 LDI F8 YES? SET 206 OUTPUT State Tableto AddressAO 09 OP AO R(A) = QP 206 OA PLO, A AA 206 OB LDI F8 SET 206 0C TP A4 R(B)=TP 206 OD PLO, B AB 206 OE LDI F8 206 OF VP BO 206 PLO, C AC Set R(C) 206 =VP 11 LDI 206 206 F8 13 PLO, D AD Set R(D) 206 12 TR A3 =TR 14 LDI F8 206 VDD B6 206 16 PLO, E AE Set R(E) 206 =VDD 17 SEX, E EE SetX=E 208 18 INP 68 READ A-D 208 11 (VDD) 19 SEX, A EA SetX=A 210 1A OUT 60 M(QP)--)OUT, 210 PQ+1 1B INC B 1 B TP + 2 214 1C INC B 1 B 214 1D LDA, C 4C M(R(C))--D, 214 VP + 1 1E SEX, E EE E -X 212 1 F SM F7 VP-VDD 212 BDF 33 If DF=1 212 VP:-5VDD 21 VPVDDCom- 1B BRANCH to 214 pare VPVDD Compare 22 DEC B 2B DECREMENT 212,214 R(B) 23 DEC B 2B DECREMENT 212,214 R(C) BY2 24 DEC C 2C 212,214 BY1 LDI F8 1 216 26 03 03 216 27 PLO, 3 A3 SET LC=3 216 28 STROBE A-D 62(15) 218 GB 2 079 610 A 10 29 LDA, D 4D M(TR)--->D, 220 TR + 1 2A PLO, 4 A4 M(TR)-TC 220 213 DEC, 4 24 TC-1 238 2C GLO, 4 84 2D BNZ 3A TESTTC=O 224 2E TEST 2 32 No. to test 224 LC = 2 2F DEC, 3 23 Yes, LC-1 232 BR 30 232 31 CHECKO 05 232 (LC = 0) 32 GLO, 3 83 R(3)-D 226 33 XRI F13 226 34 02 02 Is LC=2 226 BNZ 3A 226 36 DECTC 213 LC=2, 226 BRANCH 37 BN1 3C TEST R-Wave 228 INPUT 38 DECTC 213 No R-Wave 228 INPUTBRANCH 39 B2 35 TEST REED 230 SWITCH 3A DECTC 213 YES to DECRE- 230 MENTTC 313 BR 30 No REED 230 SWITCH 3C STRT-1 01 BRANCH to STRT-1 3D SEX, A EA SETX=A,QP 234 3E OUT 60 M(QP)-OUT' 234 QP + 1 3F LDA 413 236 PLO, 4 A4 M(TP)-TC,

236 TP + 1 41 BR 30 BRANCHTO 222 42 DECTC 213 DECREMENT 222 TC Commentl Machine Assembly Language Address Comment Language Code AO QP Q REF 01 Al QPP 02 A2 P PW 04 A3 TR T REF FIF A4 TP SP 5.2V 60 A5 PW 5.2V 03 A6 SP 4.8V 60 A7 PW 4.8V 06 A8 SP 4.4V 60 A9 PW4.4V 08 AA SP4V 60 AB PW 4V 10 AC SP 3.6V 60 AD AE SPOV 60 AF PW OV 12 BO VP V5.2 52 Bi V4.8 48 B2 V4.4 44 B3 V4.0 40 SP Sense Period B4 V3.6 36 PW = Pulse Width B5 VO.0 00 B6 VDD 11 GB 2 079 610 A 11 which is reproduced below as follows:

V1 V2 V3 V4 V5 V6 HEX B3 179 = 5.2 V A2 162 = 4.8 V 91 145 = 4.4 V 128 = 4.0 V 6E 110 =3.6 V 00 = 0.0 V The next set of values of the sense time and the pulse width are obtained from the time duration table which is set out below:

T21 T31 T22 T32 T23 T33 T24 T34 In Figure 5, there is shown a flowchart of the steps representing the instructions listed above, the corresponding step for its instructions being identified under the heading "Step Location---. The program begins atthe start step 200, transferring to step 202 wherein the loop counter LC formed by the register 11(3), is setto zero as implemented by the instruction stored at the memory address 04, as shown above.

As shown in Figure 4A, the demand ventricular pac ing mode includes a refractory state corresponding to the refractory period, during which the ventricular amplifier 139 is clamped, a sensing period state dur ing which the electrical activity of the ventricles is accessed and sensed, and a pulse width state during f5 which the ventricular stimulating pulse is applied to 80 the patient's ventricle 42. As will be evident from a further description of the steps of the program, the program proceeds in loop fashion through the steps of Figure 5 three times, one for each of the three mentioned states, with the loop counter LC being decremented upon completion of each loop to indi cate that the process has moved to the next state.

Initially, the loop counter LC is setIto zero in step 204. The process now moves to step 206, wherein the pointers VP, QP, TP and TR as defined above are 90 initialized to their starting points. For example, VP, as defined above, is the voltage transition table pointer. Thus, in step 206, the register R(C) is set to the first location within the transition point table, which defines the voltages with which the output voltage V, of the power source 126 is to be corn pared. The pointer QP pointing to the output state table as stored in register R(A), points to that loca tion within the output state table identifying which of the states as shown in Figure 4a, the processor is, i.e., within either of the refractory period, the sensing or partial period orthe pulsing or pulse width period.

The output state table is reproduced below as fol lows:

Q11 01 Q21 02 Q31 04 Refractory State Sense State Pulse Width State Next, instep 208, the microprocessor 100 commands the AID converter 108 to read out a digital indication of the power source voltage V.. In step 210, the output state QP as stored within the microprocessor register R(A) is incremented by one, i.e., to move it to the next output state. Thus, at this point, the register R(A) indicates that the process is in the initial refractory period. Next, in step 212, the voltage V. is compared with the transition point voltage (VP) as pointed to by the voltage transition point table pointer VP as stored in register R(C). If the voltage V. is greater than the voltage transition point, the process moves to step 216; if not, the process moves to step 214, wherein the voltage transition point table pointer VP is incremented one to point to the next location therein to obtain the next lower value of the transition point voltage and further the time duration table pointer TP is incremented by two to designate the next two locations within the time duration table. The next value of the voltage transition point is obtained from the voltage transition point table, 475 ms V, z--- 5.2V 800 gs 475 ms 100Ogs J V, t 4.8V 475 ms V, t 4AV 1250 gs 475 ms 1550 gs T25 T35 T26 T36 V, t 4.OV 1850jus 600 ms V, t 3.8V 600 ms 2300 gs V,: 3.6V As seen in each two locations there is given first a duration for the sense period and then the pulse width fora given voltage transition point, i.e., a reference value with which the voltage Vs is to be compared. Thus, as will be explained, the program adjusts the pulse width of the ventricular stimulating pulse to maintain constant energy within the ventricu lar stimu lating pu Ise, as well as to increase the sense period abruptly, as the voltage V, of the power source 122 attenuates, to provide a step rate slow down performance at end of battery life.

In step 214, the voltage transition point is moved from V1 to V2, e.g., from 5.2 to 4.8 volts. Again, the value of V, is compared with the voltage transition point (VP) and if greater (yes), the program moves to step 216 wherein the value of the loop counter LC is loaded with the value "three" indicating thatthe oscillator is in the refractory period. Thereafter, the A/D converter 108 is strobed to read out the power source voltage V,. In step 220, the value TR of the refractory period stored at location TR is read out and stored in the time counterTC (register R(4)).

12 GB 2 079 610 A 12 Thereafter, the process moves to step 222, wherein the value stored in the time counter (TC) is decremented by one and the timing of a period is initiated to cycle through step 222 until the value stored in the time counter (TC) is counted down to zero. Next, in step 224, a decision is made whether the value of the time counter TC equals zero, i.e., its timing function has been completed, and if not, the process moves to step 226, where a decision is made to determine whether the loop counter LC equals to 2 indicating whether the process is in the sense state corresponding to the RV sensing period; if not, which is the case atthe present point, the process loops through steps 222,224,226 until the initial count (corresponding to the refractory period) as set in the time counter TC has been decremented by step 222 to zero, as detected by step 224, thus terminating the refractory period. At that point, step 224 moves the process to step 232, wherein the loop counter LC is decremented by one, to thereby indicate that the process is in the sense state, i.e., LC equals 2, whereby the process returns to step 204. At this point, the loop counter LC does not equal to zero and the process moves to step 234, wherein the out- put state table pointer QP is incremented by one, whereat at this point in time, the process is moved to the sense state. Next in step 236, the value obtained from the time duration table is placed into the time counter TC, and the time duration table pointer (TP) is incremented by one to address the next wider pulse width within the time duration table.

Thereafter, the process moves via step 222 to decrement byone the count loaded into the time counterTC and if not zero as decided by step 224, the program advances to step 226 and if in the sense state, which the process is at this instance, the process moves to decision step 228 to determine whether an R wave has been applied to the multiplexer 106. If within the time period of a single decre- ment count, the R wave is not sensed, the process moves back to cycle to again, decrementing in step 222 the count corresponding to the sense period until the count equals zero as detected by step 224. If an R wave is detected by step 228, the process moves to step 230 to check the status of the reed switch 23 and if open, the process is reset as indicated in Figure 4Ato return the process to to, i.e., to step 202 whereatthe loop counter LC is reset tozero and the process is reinitialized. The reed switch 23 is a magnetically actuable switch within the pacemaker 12. After implantation, the physician may actuate the reed switch 23 by placing an external magnetic field close to the implanted pacemaker 12 whereby the reed switch 23 is closed to initiate the asynchronous mode of operation. If the reed switch 23 is closed indicating a desire to operate in the asynchronous mode, the process continues to loop, returning to step 222 to again decrementthe time count TC, even if an R wave is detected. In this manner, the detection of an R wave is ignored and the pacemaker 12 proceeds to pace in the asynchronous mode of operation, without resetting upon detection of the R wave.

After the second sensing period has timed out, i.e., when the count stored in the time counter TC has counted down to zero as indicated by step 224, the process is again transferred to step 232 wherein the loop counter LC is decremented byone, wherein the value stored therein equals one indicating that the process is going into its third loop and is returning to step 204. Since the loop counter LC does not equal zero, the process transfers to step 234, whereby the value QP of the output state is incremented by one indicating that the process is now in the pulse width state. Next, in step 236, the value of the time duration is addressed and accessed from the time duration table and is stored in the time counter TC. The value of the time duration table pointerTP is incremented by one to point to the next location within the time duration table as set out above. At this point, the process enters into a series of cycles whereby the count within the time counterTC is decremented by one by step 222, and if not zero transfers to step 226 and not being in the sensing period, returns to be again decremented in step 222. The process repeats until the value of the count in the time counter TC has been decremented to zero as decided by step 224. At this time, the process again moves to step 232 wherein the loop counter LC is again decremented by one, the value now being zero. The process moves to step 204 and the process begins all over again with the initialization of the values of VIP, QP, TP and TR by step 206.

In the above, there has been described the manner in which the pacemaker 12 implements the program forthe demand ventricular mode as stored in the memory 102, moving first to the refractory period, then to the sense period and finally to the pacing or pulse width period before again beginning a new cycle. As indicated above, the length of each of the refractory and pulse width periods is determined by the voltage V. of the power source 226, with the aforementioned periods and in particular the pulse width period increasing as the voltage V. decreases in orderto maintain substantially constant the energy content of the ventricular stimulating pulse.

As explained, above, the memory 102 may be programmed with any of a plurality of modes of operation for pacing the patient s heart, selectably dependent upon the patient's condition, even a change of condition afterthe implantation of the heart pacemaker 12. For example as shown in Figure 4B, the pacemaker 12 maybe operated in an A-V; sequential timing mode, wherein stimulating pulses are apiplied to each of the patient's ventricle 42 andz atrium 40; after corresponding refractory periods the activity of the ventricle is sensed and if a ventricular signal does occur after eitherthe stimulation of the ventricle or the atrium, the pacer is reset. The output and input connections of the pacemaker 12 shown in Figure 2, are selected as shown in Figure 3B. With respectto Figures 313 and 4B, the patient's ventricle 47 is pulsed immediately before time to by applying a stim ulus signal via the lead 19. After to, the ventricu- tar sensing amplifier 139 is clamped by the application of the signal TC1 to the select switch 130c, whereby the input of the amplifier 139 is connected to ground for a first refractory period from to to t, Also during the first refractory period, the ventricular output capacitor Cv is recharged by applying the con- J.

13 GB 2 079 610 A 13 5( troi signal TcJothe select switch 130a,wherebythe power source voltage V. is applied to charge the capacitor Cv. In the period t, to t2, a control or timing signal t,, as derived from the microprocessor 100 is applied to close the switch 1OW, whereby a ven tricular R wave, if present, is applied via the ventricu lar amplifier 139 and the multiplexer 106 to resetthe timing operations of the microprocessor 100.

If att2no ventricular R wave has been sensed, the pacemaker 12 causes a stimulating puiseto be applied via the lead 17 to the patient's atrium 40. In particular, a pulse control signal Tw, is applied via the driver amplifier 134b and resistor RA, to the base of the output atrial transistor GA, rendering the trans istor QA conductive causing a discharge of the output atrial capacitor CA into and thereby stimulating the patient's atrium 40. Beginning attime t,, the timing control signal is applied to select switch 130c, clamp ing the input of the ventricular amplifier 139 to ground, whereby any signal in response to the 85 stimulation of the atrium is disregarded. Beginning attime t,, the atrial output capacitor CA is recharged by the application of the timing control signal TAto close the select switch 130b to apply the power source voltage V,, to the capacitor CA. In the period from 'E4tO t., again the activity of the ventricle is sensed and a timing control signal from the microp rocessor 100 applied to close switch 106a'permitting the ventricular R wave to be applied via the unclarnped, ventricular amplifier 139 and the closed stAtch 106a'to the microprocessor 100. If the ven tricular R wave is sensed during this second sensing period from t, to t,, the timing period is reset to to. If no R wave appears in the period frorn t4 to t5, a firri ing pulse V is applied from the microprocessor 100 via the ventricular driver 134a and the resistor R,, to render conductive the ventricular output transistor Qv, whereby the charged capacitor Cv is coupled to ground discharging the capacitor Cv and applying via the lead 19 a sttimulating pulse to the patient's ven-1 ricle 42. Typical values for the periods TA extending from TO to T2 and for the period TV from TO to T5 are provided below:

TV(MS) 2000 1000 850 850 750 750 650 550 TAWS) 1700 750 700 650 600 500 300 425 The A-V sequential method of operation as shown in Figure 413 may be programmed illustratively in a manner similar to that shown in Figure 5, except that the six output states and their corresponding time periods as shown in Figure 4B, are set by counter values as derived from a corresponding table stored in the memory 102. Thus initially, typical values of TV and TA are programmed for a particular patient by accessing particular locations within the corresponding tables, one for each of the six periods, After a count has been entered into the time counter, successive cycles are carried out until the count is counted down to zero to time outtliat period.

In Figure 4C, there is illustrated the timing diagram of an atrial synchronous ventricular inhibited pacemaker (ASVIP), wherein each of the ventricular and atrial activity of the patient's heart is sensed to reset the timing period. Such a mode of operation is typically used in a younger patient whose atria are beating in a normal fashion but whose ventricles may or may not be defective. It is desired to speed up the beating of the atria and to stimulate thereby the ventricular activity. A sensed atrial P wave initiates a timing cycle; however if there is a failure in the conduction of this signal to the patient's ventri- cle, a stimulating signal will in any case be applied to the patient's ventricle 42. It is desired to utilize the rate of the beating atria to synchronize the ventricular pacing which may be impaired because of a myocardial infarction or otherwise defective cardiac conduction system. As shown in Figure 4C, the cycle begins attime to with the sensing of the atrial P wave. As shown in Figure 4C, a single cycle is divided into six timing periods (and states). During the firsttiming period from to to t, (as well as the second and third timing periods to time t,) the atrial amplifier 141 is clamped to ground by a timing signal applied to close the switch 130d. Also in the initial period the unclamped ventricular sense amplifier 139 applies any R wave signal applied from the ventricle 42 via the lead 19 to a switch 106al, which is closed by an RV control signal. If during the initial period from t,, to t,, an R wave signal is sensed, the timing cycle is reset to t, In the second or pulsing period from t, tot, the atrial amplifier 141 remains clamped to ground, the switch 130d being closed, and a timing con, rol pulse T is applied via the driver amplifier 134a and the resistor R,, to the base of the ventricular output transistor Qv, whereby the previously charged ventricular output capacitor Cv discharges through transistor Qv via the lead 19 to the patient's ventricle 42. Also during the second period (also extending into periods three and four to timetIthe ventricular amplifier 139 is clamped to ground by a switch 130c to which is applied a clamp ventricular signal TC1, whereby heart activity as would appear in the post-ventricular stimulating period is ignored. In the fourth and fifth periods from t3 to t5, the atrial amplifier 141 is unclamped permitting the atrial P wave signal tobe applied thereby via a closed select switch 106Wto reset the timing process to to. From t3 to t5, a sense timing signal RA is applied to close the switch 106K In normal operation, it is contemplated that an atrial P wave signal may be sensed during the fourth and fifth timinq periods from t, to t,, whereby the timing cycle is reset to zero. If however no P wave is sensed, the ventricle is again stimulated by the application of a control pulse Tw,to the base of the ventricular output transistor Qvwhereby a pulse is applied via the lead 19 to the patient's ventricle 42, as explained above.

The ASVP method of pacing may be programmed illustratively in a manner similar to that shown with respect to Figure 5 with six periods or output states defined in a similar manner and with each of the six 14 GB 2 079 610 A 14 timing periods established by addressing or establishing pointers to corresponding tables, whereby varying values of the periods are sent into a timing counterto be decremented as the process is execuated through each of six loops.

Referring now to Figure 6, there is shown an alternative embodiment of the adaptable programmable pacemaker of this invention, wherein similar elements and circuits are identified with similar num- bers to that shown in Figure 2, except being numbered in the 300 series. For example, the microprocessor or CPU is identified by numeral 300 and is coupled to a multiplexer 306, whereby a selected one of the inputs 338a, b, e or f is applied in the form of a flag via bus 318 to the microprocessor 300. The microprocessor selectively addresses via address bus 312 a memory 302 having illustratively a plurality of sections 302-1 to 302-16. As shown in Figure 6, the memory 302 may take the form of a volatile memory such as a random access memory, or a programmable read only memory (PROM) or an erasable read only memory (EROM). The addressed data is read out from the memory 302 and applied to a data bus 310 interconnecting the memory 302, the microprocessor 300, a decoder 342 and an AID converter 308. The A/D converter 308 converts the analog value of the supply voltage V. to a digital form to be input to the microprocessor 300 via data bus 310. It is understood that the other analog val- ues, such as the P and R waves are also converted to digital form and scaled before application to the multiplexer 306; the AID converter and the scaler circuit, as would be coupled to the multiplexer 306, are similarto that described above and are not shown in Figure 6. The microprocessor 300 applies timing signals via an N bus 352 to command the decoderto initiate decoding of the signals appearing upon the data bus 310. The decoder 342 interprets the output of the microprocessor 300 to select one of a plurality of switches 1 to 16 within the block 330. In this regard each such switch of the block 330 has its own latch within block 340 that is set by the output of the decoder 342 and in turn is coupled to an amplifier and output drive circuit as described above. In this manner, flexibility is assured to provide a plurality of output circuits which may be coupled by leads to various portions of the patient s heart, as well as to assure the ability to recharge the output drive circuits and to be able to access data at various points either on the patient s heart or on other parts of the patient's body. Thus a telemetry system is provided for transmitting data from or to the programmable pacemaker as shown in Figure 6.

In accordance with the invention, an auto-reset oscillating circuit 344 is provided to reset an address counter 307 within the microprocessor 300. The address counter 307 is incremented for each step processed to address the next word location within the memory 302. It has been found that noise such as generated by a defibrillation pulse or other source could affect the address counter 307 to address a meaningless or erroneous location within the memory 302. As a result the process would become "hung up- in a meaningless location. If the address would be affected by noise to address a meaningless location, the autoreset oscillator circuit 344 resets on a regular basis, e.g., 0.5 seconds, the address to an initial starting address of the program being executed. In the eventthatthe address counter 307 is operating normally, an output is derived from the data bus 310 and is applied via the conduit 346 to resetthe circuit 344, thus inhibiting its regular reset output signal.

In a further feature of this invention, the multip lexer 306 includes an additional set of inputs 339a to 339d for receiving a binary, starting address to be placed into the address counter 307, whereby each of the plurality of blocks 302-1 to 302-16 may be selected and executed. Thus, it is contemplated that' a plurality of heart pacing modes could be stored within the memory 302. with each mode stored in a separate block and its starting point could be addressed by entering a binary number via the inputs 339a to 339d and an external link 341 taking the form of an RF (or acoustical) link, as described above.

In addition, self-checking routines or data gathering routines may be stored within the blocks of the memory 302. In Figure 3A, there is shown an indica- tion of the manner in which an exemplary selfchecking routine could be carried out to testthe continuing operability of the ventricular sensing amplifier 139. A further select switch 130g may be closed in response to a test signal Tt that is generated by such a self-checking routine or program as stored within the memory 102, to apply a reference voltage V,f in the order of 1 millivolt to the input of the ventricular sensing amplifier 139. The amplified output is in turn applied by the multiplexer 106 to the mic- roprocessor 300, whereby the amplified voltage is compared with a reference value to determine whether the amplifier 139 is operative; if not, a different output circuit and sensing amplifier could be coupled in circuit to replace the defective sensing amplifier.

In a still further mode of operation, a program could be stored within one of the blocks of the memory 302 to effect a sensing and transmission of data as coupled by leads to the implanted pacemaker. For example, the leads could be coupled to hea rt tissue, other tissue or transducers, to sense the patient's EKG, pulse rate, pulse width, the time of depolarization between the atrium and ventricle, etc. The time. of transmission of a depolarization signal is consi-.

dered to be indicative of the heart's condition and az window is established by a sensing program in accordancewith a normal transmission time. If the received signal is outside the limits of such a window, an indication thereof is transmitted externally of the pacemaker. In a data gathering mode, it is contemplated that the latches associated with the associated leads to the heart sites, tissue sites, or transducers are coupled one at a time, by selectively closing the corresponding select switch 330, whereby that data is sent by the external link 341 to an external monitoring device.

In addition, there is included an input 338f coupled to the reed switch 23 of the type that is closed by an external magnet, to alter the operation of the pacemaker shown in Figure 7. It is contemplated that i GB 2 079 610 A 15 0 a succession of signals may be generated by opening and closing the switch 23, whereby the external link 341 is enabled to receive or to transmit data to or from the pacemaker 12% for example, the address counter 307 is loaded with a new address to address the starting location of the next block of memory 302, whereby a further mode of operation is executed.

Referring now to Figure 7A, there is shown a more detailed schematic circuit of the blocks of a first specific embodiment of the apparatus generally shown in Figure 6. In particular, the microprocessor 300 is identified illustratively as the COSMAC microprocessor as manufactured by the Radio Corpora- -15 tion of America and described in the publication enti- 80 tled "USER MANUAL FOR THE CDP 1802 COSMAC MICROPROCESSOR (1976)". The multiplexer306 has a series of sixteen inputs 0 to 15 and may take the form of the CDO067 as, manufactured by FICA to provide an output to the A/D converter 308. In turn, 85 the A/D converter 308.is coupled by the data bus 310 to the microprocessor 300, and is also connected to a latch 309, whereby one of the sixteen inputs of the multiplexer 306 is selected to apply analog data to the AJD converter 308. The N timing bus 352 is shown as a bundle of conduits 352a to d and is coupled to the decoder 342 made up of a plurality of gates as manufactured by RCA under a designation CD4012. The outputs of two of the gates are applied via the conduits 356 to a convert command input, whereby the A/D converter 308 accepts data from the multiplexer 306, and to a tristate output, whereby the A/D converter 308 is commanded to apply the data converted to digital form to the data buss 310.

Further, output strobes 1 and 2 are derived from conduits 354a and b, and applied respectively to latches 342a and 342b, whereby data applied to the data conduit 310 may be selectively applied to one of a plurality of switches contained within the blocks 330a and 330b, respectively. The blocks 330a and 330b each include four solid state select switches to provide output signals to selected output drive circuits. Further, in the particular embodiment shown in Figure 7A, the detected R wave signal is applied to the fF_1 input of the microprocessor 300, and the reed switch input is applied to the fF-2 input of the microprocessor 300. In this embodiment, the microprocessor 300 acts as its own multiplexerto selectively access and operate upon signals placed to these inputs in the desired sequence. Further, the microprocessor 300 applies addresses via the address bus 312 to the memory 302 whereby data may be read out and applied to the data bus 310.

In Figure 7B, there is shown a detailed schematic circuit of a further second embodiment of the pacemaker apparatus as shown generally in Figure 6. The elements in Figure 713 are numbered with the same number as like elements of Figure 6, except in the 500 series. The input signals corresponding to the R wave, the P wave and the reed switch output are applied to the inputs 1, t0_0 and tr-2 of the microprocessor 500, which may illustratively also take the form of the CDP 1802 microprocessor manufactured by RCA. In this embodiment, the microp65 rocessor500 performs multiplexing functions whereby one of these values is processed at a time. Typically such inputs are in analog form and require conversion to digital form by the circuits shown within the dotted lines marked generally by the numeral 508. The A/D converter includes a circuit as manufactured by RCA under their designation CD4508 and receives inputs from operational amplifiers 511 to which is applied a reference signal established by the Zener diodes 513. A clock signal is applied via a flip-flop 509 and an FET517 to an input of the converter 515. The system's memory 502 is connected to outputs of the microprocessor 500 and is comprised of two blocks manufactured by RCA under their designation CDP 1822S. The microprocessor 500 supplies command signals via the N bus 552 to a decoder 542 taking the form of a chip as manufactured by RCA under their designation CD 4514 B. The decoder 542 performs decoding functions on the output of the memory 502, under control of the timing signals applied via the N bus 552. The outputs of the decoder 542 are applied to a pair of latches 540a and 540b, each taking the form of the latch as manufactured by RCA undertheir designation CD4508. The decoder 542 selects a latch go whereby a corresponding select switch within the arrays 530a and 530b is closed. The arrays of select switches may be composed of integrated circuits as manufactured by RCA undertheir designation 4066AE.

Numerous changes may be made in the above described apparatus and the different embodiments of the invention may be made without departing from the scope thereof; therefore, it is intended that all matter contained in the foregoing description and in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense. CLAIMS 1. Body-implantableelectromedical apparatus including memory means for storing a program of instructions and a microprocessor for executing the program, the microprocessor including address means for addressing the memory, wherein there is included resetting means coupled to said microprocessor for periodically generating a reset signal to reset said address means to a predetermined return address, whereby if said address means inadvertentiy addresses a meaningless location in said memory means, the execution by said microprocessor of a selected program within said memory will be continued by addressing the predetermined return address within the selected program.

2. Apparatus as claimed in claim 1 wherein said microprocessor includes means coupled to said reset means for periodically generating and applying a defeat command signal to said reset means to defeat the operation of said reset means if said address means is operating correctly.

3. Body-implantable electromedical apparatus as claimed in claim 1 and substantially as hereinbefore described with reference to the accompanying drawings.

Printed for Her Majesty's Stationery Office by The Tweeddale Press Ltd.. Berwick-upon-Tweed, 1981. Published at the Patent Office, 25 Southampton Buildings, London, WC2A 1 AY, from which copies may be obtained.