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GB2073947A - Integrated circuit encapsulation - Google Patents

Integrated circuit encapsulation Download PDF

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Publication number
GB2073947A
GB2073947A GB8012093A GB8012093A GB2073947A GB 2073947 A GB2073947 A GB 2073947A GB 8012093 A GB8012093 A GB 8012093A GB 8012093 A GB8012093 A GB 8012093A GB 2073947 A GB2073947 A GB 2073947A
Authority
GB
United Kingdom
Prior art keywords
lead frame
channel
integrated circuit
mould
strip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB8012093A
Other versions
GB2073947B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronics UK Ltd
Original Assignee
Philips Electronic and Associated Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronic and Associated Industries Ltd filed Critical Philips Electronic and Associated Industries Ltd
Priority to GB8012093A priority Critical patent/GB2073947B/en
Publication of GB2073947A publication Critical patent/GB2073947A/en
Application granted granted Critical
Publication of GB2073947B publication Critical patent/GB2073947B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A lead frame (9), comprises a series of individual device frames each having a device support (10) and leads (12) extending transversely from rails (11). Adjacent device frames are joined by parts (15, 16) which extend only outside the area (14) of the lead frame to be encapsulated. Part of each lead may be formed from a part (11a) of the rails. An integrated circuit device (18) is mounted on each device support and the lead frame is mounted in a mould which has a channel extending parallel to the longitudinal direction of the lead frame. Encapsulating material is introduced into the channel to form a strip which can be severed easily. Severing is facilitated because no lead frame material is embedded in the strip at the places where it is to be severed. Ribs in the mould form notches in the strip which further facilitate severing. <IMAGE>

Description

SPECIFICATION Methods of encapsulating integrated circuit devices, lead frames for use in such methods and integrated circuit devices encapsulated by such methods This invention relates to methods of encapsulating integrated circuit devices which are attached to device supports of a lead frame. The invention also relates to lead frames for use in such methods and further relates to integrated circuit devices which are encapsulted by such methods.
In the manufacture of integrated circuits a plurality of similar circuits is usually formed on a single wafer of semiconductor material. The wafer is then divided into individual integrated circuit devices which are both small and fragile. Each integrated circuit device has various contact areas to which electrical connections are to be made. To facilitate connecting these small contact areas to external circuitry the integrated circuit device may be mounted on a support of a lead frame which comprises a plurality of leads extending on opposite sides of the support. At this stage the leads are interconnected by tie-bars. Electrical connections, for example wire connections, are made between the contact areas of the integrated circuit device and the leads.For protection of the integrated circuit device and to add mechanical strength to the lead frame the integrated circuit device and part of the lead frame are encapsulated in a material, usually a thermosetting plastics material, so that the leads extend outside the encapsulation.
The tie-bars can then be cut to provide electrically isolated leads which separately connect with the various contact areas of the integrated circuit device.
This type of encapsulated integrated circuit device is cheap to manufacture and is widely used in domestic, commercial and industrial applications.
Lead frames used in encapsulating integrated circuit devices conventionally comprise a plurality of adjoining device frames each of which is surrounded by a continuous peripheral member. Within the peripheral member each device frame consists of a support for an integrated circuit device and a plurality of electrically conductive leads extending from the part of the peripheral member between adjacent device frames on opposite sides of the support. Generally, the support is maintained in its position relative to the leads by a bar which extends from the peripheral member to the support itself.
The peripheral member is provided with datum holes. These datum holes permit tools, which are used for example to cut the lead frames from the peripheral members, to be positioned precisely relative to the device frames. Also they can cooperate with an indexing member so that movement of the lead frame can be automated.
After the integrated circuit devices have been attached to the supports the lead frame is placed in a mould. This mould comprises a plurality of cavities into which encapsulating material can flow. Each cavity corresponds to the encapsulation of a separate integrated circuit device. The encapsulating material flows along a transfer guide and via gates into the individual cavities. The introduction of encapsulating material into the cavities is in a direction transverse to the longitudinal direction of the lead frame. When the encapsulting material has hardened the lead frame can be removed from the mould and then the unwanted encapsulating material can be discarded and the individual device frames can be separated. An example of such a method is described in United Kingdom Patent Specification (GB) 1,271,833.
A disadvantage of this method is that a relatively large quantity of encapsulating material is wasted.
All of the material which has hardened in the transfer guide and in the gates is discarded. Furthermore, a relatively large quantity of lead frame material is wasted because the entire peripheral member is discarded. Also, because the encapsulation is relatively small the gates connecting the transfer guide to the cavities are relatively narrow so that they tend to become obstructed. This hinders the flow of encapsulating material. Consequently, the yield of devices encapsulated to an acceptable standard is adversely affected and so too is the unit cost price.
According to a first aspect of the invention there is provided a method of encapsulting a plurality of integrated circuit devices including the steps of attaching the integrated circuit devices to individual device supports of a lead frame which comprises a plurality of device frames each having an integrated circuit support and a plurality of leads extending on opposite sides of said support, adjacent device frames being joined by interconnecting parts, mounting the lead frame in a mould comprising a channel which extends parallel to the longitudinal direction of the lead frame, which lead frame has such a configuration that the supports are situated in the channel and the interconnecting parts extend only outside the channel, introducing into the mould an encapsulating material which flows along the channel, removing the lead frame from the mould when the encapsulating material has hardened forming a continuous strip which encapsulates the integrated circuit devices, and dividing the strip into portions each encapsulating an integrated circuit device by severing the strip between said interconnecting parts of the lead frame.
The encapsulation of a plurality of integrated circuit devices in a single strip can be less expensive than the known method because of savings in encapsulating and lead frame material. The saving in encapsulating material which may be, for example, a thermosetting plastics material, results because a greater percentage of the encapsulating material is usefully employed in encapsulating integrated circuit devices. This is a consequence of there being no transfer guide and only one gate for a plurality of devices. The saving in lead frame material results because adjacent device frames are joined only by interconnecting parts extending outside the channel of the mould. These interconnecting parts can be made from less lead frame material than can the parts of the peripheral member between adjacent device frames of a conventional lead frame.
As the interconnecting parts of the lead frame extend only outside the channel of the mould the lead frame material does not become embedded in the encapsulating material at the places where the strip is to be severed. It has been found difficult to sever plastics encapsulating material and lead frame material in the same cutting operation. For example, in the case of sawing, the blades suitable for cutting the lead frame material become dulled by the encapsulating material. A method in accordance with the invention has the advantage that the strip can be severed easily by cutting or breaking and the interconnecting bars and interconnecting parts of the lead frame can be cut in a separate operation.
Of course the mould may comprise a plurality of channels each connected to a transfer guide via separate gates. Each channel then accommodates a separate lead frame. However, only relatively few channels are needed compared with the number of cavities required for encapsulating the same quantity of integrated circuit devices using the known method.
The mould may comprise constrictions so that the strip is fomed with notches at the places where it is to be severed. The strip can then be divided easily by breaking the strip at the area of the notches. It may be broken either manually or mechanically. Alternatively, notches which are not sufficiently deep to permit breaking may be provided when the strip is to be severed by cutting. The notches facilitate this cutting operation by reducing the amount of encapsulating material which must be cut to divide the strip into separate portions each encapsulating an integrated circuit device.
If heat sinks are to be included in the integrated circuit devices these can be inserted into the channel before mounting the lead frame in the mould. An individual heat sink can be inserted into each part of the channel between adjacent ribs so that each heat sink is accurately located with respect to the lead frame. As individual heat sinks are located between the ribs the material of the heat sinks does not become embedded in the encapsulating material at the places where the strip is to be severed.
Accoding to a second aspect of the invention there is provided a lead frame, which lead frame comprises two parallel rails extending along the length of the lead frame, a plurality of individual device frames each having a device support between the rails and leads which extend transversely from said rails on opposite sides of said device support, which leads and device support are maintained in their relative positions by interconnecting bars, adjacent device frames being joined by interconnecting parts which extend only outside the area of the lead frame to be encapsulated.
A lead frame in accordance with the invention may have a part of each lead formed by part of one of the rails. This permits a cost saving resulting from a saving in discarded lead frame material as compared with known lead frames where the whole of the continuous peripheral member is discarded.
A further saving in lead frame material can be made when the interconnecting parts comprise straps between adjacent outermost leads of adjacent device frames by arranging that the spacing of the straps from the rails is different to that of the tie-bars. This saving results because it is not necessary to provide wide lead frame parts to accommodate datum holes. Instead each datum hole is defined by the strap and the two adjacent leads of adjacent lead frame portions.
According to a further aspect of the invention there is provided an integrated circuit device encapsulated by a method in accordance with the first aspect of the invention.
An embodiment will now be described by way of example to illustrate these various aspects of the present invention, in which: Figure 1 is a cross-sectional view of part of the upper and lower halves of a mould for use in a method in accordance with the first aspect of the invention; Figure 2 is a plan view of the lower half of the mould of Figure 1; Figure 3 is a plan view of part of a lead frame in accordance with the second aspect of the invention; Figure 4 is a cross-sectional view taken along IV-IV' of Figure 3 of a plurality of integrated circuit devices encapsulated by a method in accordance with the first aspect of the invention; Figure Sis a schematic view of a single encapsulated integrated circuit device shown in Figure 4, and Figure 6 is a plan view of a modified form of the mould shown in Figure 2.
The mould of Figures 1 and 2 may be made of steel and comprises upper and lower halves 1 a and 1 b respectively. The mould comprises a channel 2 which becomes sealed when the two mould halves are brought together. The locating pins 5a on the lower mould half 1 b and the complementary holes 5b in the upper mould half 1 a ensure that the mould halves are correctly aligned when they are brought together.
Ribs 6a are provided on the upper mould half 1 a and these lie directly above the ribs 6b on the lower mould half 1 b. The ribs 6a and 6b extend across the full width of the channel 2. However, on both mould halves the ribs are lower than the peripheral walls 7a and 7b so that when the mould halves are brought together there is a gap between corresponding ribs.
This gap forms a constriction in the channel 2.
The lower half 1 b of the mould has an inset platform 8 on which a lead frame 9 can be supported. The platform 8 is of substantially the same dimensions as the lead frame 9. Vertical movement of the lead frame 9 is prevented in a downward direction by the platform 8 on the lower half of the mould and in an upward direction by the peripheral walls 7a of the upper half of the mould which engage the upper surface of the lead frame 9 and which act to clamp the lead frame when the two mould halves are brought together.
A part of a lead frame 9 for use in a method in accordance with the invention is shown in Figure 3.
This lead frame which is approximately 20.3 cm long, 2 cm wide and 0.25 mm thick and which is made of, for example copper alloy or steel alloy may comprise a series of ten individual device frames of which only one is shown fully in Figure 3. Each device frame comprises an integrated circuit device support 10 and eight leads 12 extending transversely from two rails 11 on opposite sides of the support 10.
The support 10 is 5.3 mm long and 3.1 mm. wide and the distance between the centre of adjacent leads 12 is 2.54 mm. The rails 11, which are 1 mm wide, extend along the length of the lead frame. The leads 12 and device support 10 are maintained in their relative positions by interconnecting bars 13a, 13b.
Bars 13a extend between adjacent leads of a single device frame and bars 13b extend on each side of the support between a bar 13a, in this embodiment, the central bar 13a, and the support 10 itself. The broken line in Figure 3 bounds the area 14 which is the area of the lead frame to be encapsulated.
Adjacent device frames are joined by interconnecting parts 15, 16 of the lead frame. The parts 16 are in the form of parts of the rails 11 and the parts 15 are in the form of straps extending between adjacent outermost leads of adjacent device frames. These straps are nearer to the rails 11 than are the interconnecting bars 13a. Thus datum holes 17 are bounded by the straps 15 and the two leads interconnected by the straps 15 and the rails 11.
These holes 17 permit the accurate alignment of tools with respect to the device frames and also, by co-operation with an indexing member, movement of the lead frame can be automated.
This lead frame 9 can be made by the conventional techniques of etching or punching a metal blank.
In a method in accordance with the first aspect of the invention an integrated circuit device 18 is attached to each of the supports 10 in known manner. Wire connections can be made between the various contact areas of the integrated circuit device and the lead frame. This operation is well known in the semiconductor industry and so will not be described further here. For the sake of clarity in Figure 3 the wire connections and the various contact areas of the integrated circuit device are not shown.
If heat sinks are to be included in the integrated circuit devices these are inserted into the channel of the mould. An individual heat sink (which for the sake of clarity is not shown in the Figures) is inserted into each part of the channel 2 between adjacent ribs 6b in the lower half 1 b of the mould. The heat sink has dimensions such that its movement in the channel 2 in a plane parallel to the platform 8 is prevented by the sides of the channel 2 and by the ribs 6b.
The lead frame 9 is then placed on the platform 8 of the lower half 1 b of the mould. The locating pin 3 co-operates with a datum hole 17 in the lead frame 9 so that the lead frame is accurately located in the channel 2 and so that in the plane of the platform 8 movement of the lead frame is prevented. When the upper half 1 a of the mould is brought towards the lower half 1 b the locating pins 3 and 5a co-operate with the holes 4 and 5b respectively. The two mould halves are then clamped together.
The area 14 of the lead frame to be encapsulated is situated within the channel. Thus the supports 10 are in the channel 2 whereas the interconnecting parts 15 and 16 extend only outside the channel 2. The channel 2 extends parallel to the longitudinal direction of the lead frame 9.
The assembly is heated to, for example 1850C and molten encapsulating material, for example an epoxy plastics material such as that available from Hysol Sterling Limited under the Trade Mark Hysol MH15, is introduced into the region 20 of the lower mould half 1b via the entry port 21 in the upper mould half 1 a. The epoxy plastics material is then forced under pressure through the gate 22 and into the channel 2. This may be effected using a plunger of substantially the same diameter as the region 20.
The plunger is introduced into the entry port 21 after the epoxy plastics material and thereafter it is moved in a downward direction to force the epoxy plastics material along the cavity 2. The gate may be of the same width as the cavity, for example 6.5 mm.
Because the gate is relatively wide the flow of encapsulating material into the cavity 2 is not hindered. The epoxy plastics material flows between the ribs 6a and 6b and eventually fills the channel 2.
As can be seen from Figure 1 the epoxy plastics material can flow along both sides of the lead frame 9. The flow of epoxy plastics material along the channel can be assisted by partially evacuating the channel 2 via a vacuum pipe 23.
The epoxy plastics material is then hardened by exposure to, for example, a temperature of 1 850C for 11/2 minutes. The epoxy plastics material forms a strip 24 which encapsulates the integrated circuit devices as shown in Figure 4. The strip corresponds to the area 14 of the lead frame to be encapsulated (see Figure 3). The strip has notches 25a, 25b at the places where the strip is to be severed. This facilitates the severing operation. The strip can be divided into portions each encapsulating an integrated circuit device by severing the material of the strip at the area of the notches between the interconnecting straps 15. The severing may be effected by cutting or breaking. The chain line 19 in Figure 3 represents the line along which the encapsulation is severed.
The depth of the notches 25a, 25b clearly is determined by the height of the ribs 6a, 6b. If the ribs are too high the constriction will be too great and so hinder the flow through the cavity of the encapsulating material. For a strip of encapsulating material 3.5 mm thick it has been found that ribs 1.5 mm high allow a satisfactory flow of encapsulating material through the cavity while facilitating the severing of the strip by breaking at the area of the notches formed.
Either before or after the strip 24 is severed the lead frame 9 is itself severed at the area of the interconnecting parts to separate the individual device frames. The severing of lead frame material is well known and so will not be discussed further here.
The interconnecting parts 15 and 16 are removed by severing as are the interconnecting bars 13a and 13b. In order to economize on lead frame material a part of each lead 12 can be formed by a part of a rail 11. To separate the leads therefore it is necessary to cut the lead frame as shown by the broken lines 30 in Figure 3. In this way the parts 1 1a of the rails 11 form the end parts of the leads 12 remote from the support 10.
After all the severing operations have been completed an encapsulated integrated circuit device is obtained as shown in Figure 5.
In the description given so far the lead frame comprises eight lead pins on both sides of the device support. The lead pins on the side of the support are in line with those on the other side. Of course this is not necessary and the leads on one side of the support may be displaced relative to those on the other side. Furthermore, the number of leads may be more or less than eight on either or both sides of the support.
Although the mould described has ribs 6a and 6b, these are not necessary. In their absence the strip 24 will be formed as a strip of constant thickness. At the place where the strip is to be severed there is still no material of the lead frame embedded in the encapsulating material so the strip can be divided easily into portions, for example by cutting.
Also, the interconnecting straps 15 may be provided further from the rails 11 than the interconnecting bars 13a, 13b. However, they must extend only outside the area of the lead frame to be encapsulated.
The invention is not restricted to a mould comprising a single channel. Indeed, it is possible to have a plurality of channels, each of which may accommodate different lead frames. An example of a mould layout for such a case is shown in Figure 6. Here the mould comprises four channels 31 to 34. Each channel is connected via a gate 41 to 44 to a transfer guide 40. Encapsulating material introduced into the region 50 of the mould flows into the channels 31 to 34 via the gates 41 to 44 respectively. In this example the channel 31 accommodates a lead frame comprising ten individual device frames each having sixteen leads in a dual-in-line (D.l.L.) arrangement. The channels 32,33, 34 accommodate lead frames comprising eight, twelve and nine device frames respectively and these device frames have twenty, fourteen and eighteen leads respctively, all in a D.I.L.
arrangement. The supports of the lead frame accommodated by channel 31 are situated in the channel and the interconnecting parts extend only outside it.
This is the case also for each of the lead frames in the channels 32,33 and 34.

Claims (12)

1. A method of encapsulating a plurality of integrated circuit devices including the steps of attaching the integrated circuit devices to individual device supports of a lead frame which comprises a plurality of device frames each having an integrated circuit device support and a plurality of leads extending on opposite sides of said support, adjacent device frames being joined by inerconnecting parts, mounting the lead frame in a mould comprising a channel which extends parallel to the longitudinal direction of the lead frame, which lead frame has such a configuration that the supports are situated in the channel and the interconnecting parts extend only outside the channel, introducing into the mould an encapsulating material which flows along the channel, removing the lead frame from the mould when the encapsulating material has hardened forming a continuous strip which encapsulates the integrated circuit devices, and dividing the strip into portions each encapsulating an integrated circuit device by severing the strip between said interconnecting parts of the lead frame.
2. A method as claimed in Claim 1, which further includes the step of separating the individual device frames by severing the lead frame at the area of the interconnecting parts.
3. A method as claimed in either of the preceding Claims, in which the channel comprises constrictions to that notches are formed in the strip of encapsulting material between the interconnecting parts, which method includes the step of severing the strip at the area of the notches.
4. A method as claimed in any of the preceding Claims, in which the mould comprises a plurality of channels which are each connected via a gate to a transfer guide, which method includes the step of mounting a plurality of lead frames in the mould so that each channel accommodates a lead frame whose supports are situated in the channel and whose interconnecting parts extend only outside the channel.
5. A method as claimed in any of the preceding Claims, in which the encapsulating material is a thermosetting plastics material.
6. A lead frame for use in a method claimed in any of the preceding Claims, which lead frame comprises two parallel rails extending along the length of the lead frame, a plurality of individual device frames each having a device support between the rails and leads which extend transversely from said rails on opposite sides of said device support, which leads and device support are maintained in their relative positions by interconnecting bars, adjacent device frames being joined by interconnecting parts which extend only outside the area of the lead frame to be encapsulated.
7. A lead frame as claimed in Claim 6, in which a part of each lead is formed by part of a rail.
8.A lead frame as claimed in Claim 6 or Claim 7, in which said interconnecting parts comprise straps extending between adjacent leads of adjacent device frames and the spacing of said straps from the rails is different to that of the interconnecting bars.
9. A lead frame as claimed in any of Claims 6 to 8, in which the leads on one side of the support are in line with those on the opposite side.
10. A lead frame substantially as herein described with reference to Figure 3 of the accompanying drawings.
11. A method substantially as herein described with reference to Figures 1 to 5 or Figure 6 of the accompanying drawings.
12. An integrated circuit device encapsulated by a method claimed in any of Claims 1 to 5 or Claim 11.
GB8012093A 1980-04-11 1980-04-11 Integrated circuit encapsulation Expired GB2073947B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8012093A GB2073947B (en) 1980-04-11 1980-04-11 Integrated circuit encapsulation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8012093A GB2073947B (en) 1980-04-11 1980-04-11 Integrated circuit encapsulation

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Publication Number Publication Date
GB2073947A true GB2073947A (en) 1981-10-21
GB2073947B GB2073947B (en) 1983-12-21

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0106475A1 (en) * 1982-10-04 1984-04-25 Texas Instruments Incorporated Apparatus and method for semiconductor device packaging
US4560580A (en) * 1982-09-30 1985-12-24 Phillips Petroleum Company Process for encapsulating articles with optional laser printing
FR2584862A1 (en) * 1985-07-12 1987-01-16 Eurotechnique Sa PROCESS FOR THE CONTINUOUS PRODUCTION OF MICROMODULES FOR CARDS CONTAINING COMPONENTS, CONTINUOUS STRIP OF MICROMODULES AND MICROMODULES PRODUCED BY SUCH A METHOD
US4654225A (en) * 1982-09-30 1987-03-31 Phillips Petroleum Company Laser printable polyarylene sulfide compositions process for encapsulating articles with optional laser printing
EP0251880A3 (en) * 1986-06-30 1988-08-03 Fairchild Semiconductor Corporation Reduction in power rail perturbation and in the effect thereof on integrated circuit performance
DE3814257A1 (en) * 1987-04-27 1988-11-17 Hitachi Ltd DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICES
US4810865A (en) * 1985-11-08 1989-03-07 Eurotechnique Method for recycling a card having an incorporated component, and a card designed to permit recycling
US4822988A (en) * 1985-11-08 1989-04-18 Eurotechnique Card containing a component and a micromodule having side contacts
US5065224A (en) * 1986-06-30 1991-11-12 Fairchild Semiconductor Corporation Low noise integrated circuit and leadframe
US5173621A (en) * 1986-06-30 1992-12-22 Fairchild Semiconductor Corporation Transceiver with isolated power rails for ground bounce reduction
DE4401588A1 (en) * 1994-01-20 1995-07-27 Ods Gmbh & Co Kg Method for capping a chip card module, chip card module, and device for capping

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4560580A (en) * 1982-09-30 1985-12-24 Phillips Petroleum Company Process for encapsulating articles with optional laser printing
US4654225A (en) * 1982-09-30 1987-03-31 Phillips Petroleum Company Laser printable polyarylene sulfide compositions process for encapsulating articles with optional laser printing
EP0106475A1 (en) * 1982-10-04 1984-04-25 Texas Instruments Incorporated Apparatus and method for semiconductor device packaging
FR2584862A1 (en) * 1985-07-12 1987-01-16 Eurotechnique Sa PROCESS FOR THE CONTINUOUS PRODUCTION OF MICROMODULES FOR CARDS CONTAINING COMPONENTS, CONTINUOUS STRIP OF MICROMODULES AND MICROMODULES PRODUCED BY SUCH A METHOD
EP0211716A1 (en) * 1985-07-12 1987-02-25 Eurotechnique Method for continuously producing micromodules for cards comprising components, continuous strip of micromodules, and micromodule realized by such a method
US4810865A (en) * 1985-11-08 1989-03-07 Eurotechnique Method for recycling a card having an incorporated component, and a card designed to permit recycling
US4822988A (en) * 1985-11-08 1989-04-18 Eurotechnique Card containing a component and a micromodule having side contacts
US5065224A (en) * 1986-06-30 1991-11-12 Fairchild Semiconductor Corporation Low noise integrated circuit and leadframe
EP0251880A3 (en) * 1986-06-30 1988-08-03 Fairchild Semiconductor Corporation Reduction in power rail perturbation and in the effect thereof on integrated circuit performance
US5173621A (en) * 1986-06-30 1992-12-22 Fairchild Semiconductor Corporation Transceiver with isolated power rails for ground bounce reduction
DE3814257A1 (en) * 1987-04-27 1988-11-17 Hitachi Ltd DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICES
DE3814257C2 (en) * 1987-04-27 1996-06-20 Hitachi Ltd Casting mold for the production of semiconductor elements encapsulated in synthetic resin
DE4401588A1 (en) * 1994-01-20 1995-07-27 Ods Gmbh & Co Kg Method for capping a chip card module, chip card module, and device for capping
DE4401588C2 (en) * 1994-01-20 2003-02-20 Gemplus Gmbh Method for capping a chip card module and chip card module

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