GB1521029A - Synchronous digital systems - Google Patents

Abstract

1521029 Data transmission POST OFFICE 19 Sept 1975 [20 Sept 1974] 41131/74 Heading H4P A clock system for syncronous digital signalling apparatus, e.g. a data modem, comprises an oscillator 1 connected to a clock pulse output terminal 6; an input terminal 7 for the baseband signal with which the clock is to be synchronized; means to sample a signal applied to the terminal 7, including a zero-crossing detector 9 and a counter 16 arranged to respond to a predetermined number of zero-crossings detected by the detector; a tuned circuit 10 associated with zero-crossing detectors 8, 13 and arranged to oscillate in phase with the average phase of the sampled signal; and logic circuitry 14 associated with the counter 16, the tuned circuit 10 and a start/stop gate A, the arrangement being such that clock pulses are prevented from appearing at the terminal 6 during the sampling period, but appear at the terminal in phase with the oscillations in the tuned circuit 10 at the end of the sampled signal. The system may be used to achieve initial synchronization after transmission-reception change-over in simplex or half duplex operation, employing a 15 bit pseudo random binary sequence for the signal to be sampled. The long term synchronization is effected by comparing the timing of the clock pulses with the timing of the synchronous digital signal by means of an early/late gate 17, the result of the comparison being used to control, by way of a counter 18, a circuit 3 which adds or suppresses pulses from the oscillator I, thereby ensuring the provision of synchronized clock pulses at the terminal 6.