GB1509960A - Device for synchronising clock pulses of a receiver with those of a transmitter in transmitting-receiving equipment - Google Patents

Abstract

1509960 Telegraphy SPETSIALNOE KONSTRUKTORSKOE BJURO PROMYSHLENNOI AVTOMATIKI 28 Nov 1975 49045/75 Heading H4P A clock pulse synchronizing arrangement in a transmitter-receiver comprises: (a) a circuit 1 for storing triggering signals, having one input L applying the transmitter clock signals, another input Q to which a reset signal may be applied, and first and second outputs 9, 12 connected to respective first inputs of AND gates 3, 4 respectively; (b) a pulse generator 14; (c) two pulse counters 16, 21, the first of which, 16, registers a number of pulses from generator 14 which occur during a time interval corresponding to the phase diference between received clock pulses T and the trigger signal, and the second of which, 21, counts pulses registered in the first counter, the input of the first counter being connected to the pulse generator 14 via a third AND gate 5 which also receives the second output 12 of storage circuit 1, and an input, 20, of the second counter, 21, being also connected to pulse generator 14. (d) A NOT circuit 18 coupled between the output of AND gate 4 and a reset input of counter 16; (e) a pulse shaper 33, having an input 35 connected to the output of AND gate 3, a reset input 34 connected to the output of pulse counter 21, a first output 32 connected via a NOT circuit 30 to a reset input of counter 21 and a second output 36 coupled to the input of a second pulse shaper 37; and (f) an information transcription circuit 23 interconnecting the two counters and having an input 25 coupled to the source of receiver clock pulses T. Pulses from generator 14 are counted by counter 16, the counter being periodically reset to zero by receiver pulses T. Arrival of a transmitter pulse at L changes over bi-stable trigger 1 to close gate 5 thus inhibiting the supply of further pulses from 14 so that the count is stopped at a value corresponding to the time interval between a receiver and a transmitter pulse. Bi-stable trigger 1 now enables gate 3 so that the next receiver pulse sets pulse shaper 33 to enable counter 21 by removing the reset signal from 29. The count stored in 16 is then written into 21 in inverse form, by transcription circuit 23. Counter 21 is now stepped by pulses from generator 14 until it overflows to produce an output signal which resets shaper 33. This in turn triggers shaper 37 to produce an output clock T' in phase with the transmitter clock L.