GB1501452A - Digital signal sampling circuit - Google Patents

Abstract

1501452 Semi-conductor bi-stable INTERNATIONAL COMPUTERS Ltd 23 Jan 1976 [28 Jan 1975] 3566/75 Heading H3T A digital data sampling circuit comprises a bistable 10 with complementary outputs Q, to each of which is connected an output circuit 11, 12 which produce output signals having opposite logic levels when the bi-stable is in a stable state but having a unique logic level condition when the bi-stable is in an unresolved state in which the output signals have the same logic level, means 14 for gating an input data signal into the bi-stable, preset terminal, by an asynchronous strobe signal, means to produce an output strobe signal following each input strobe signal, delay 16, 17, and a logic circuit 13 which detects the condition that the output circuits are at the unique logic level condition and which inhibits production of the output strobe signal as long as the condition persists. The delay 16 is necessary to allow for the switching time of the bi-stable 10 and the output circuits 11, 12 and is just longer than this time. The bi-stable and output circuits may be a 74 S74 integrated circuit, this having the cross couplings which made it bi-stable taken from points (Q 3 Q 13 collectors, Fig. 2, not shown) in the circuit before the outputs Q, Q. The clock input is held permanently low to render the data input inoperative, only the slave portion of this device being used. As shown the logic circuit may consist solely of NAND gates used as buffers 11, 12 or as logic gates 13, 17, 18. In another embodiment, Fig. 3, other types ofbistables can be used with an emitter follower 21, 22 connected to the complementary outputs Q, Q and logic connected to their outputs. With ECL logic it is necessary to take both Q, Q and a fraction of this Q', Q' for application to two ECL stages (33, 34, Fig. 4, not shown).