GB1591805A - Electric signal generators - Google Patents

Description

(54) IMPROVEMENTS IN OR RELATING TO ELECTRIC SIGNAL GENERATORS (71) We, THE GENERAL ELECTRIC COMPANNY LIMITED, of I Stanhope Gate, London, W1A 1EH., a British Company, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to electric signal generators.

In one form, the invention is concerned with electric signal generators of the kind which is arranged to supply a plurality of electric signals each representing a repeated sequence of binary digits, the said signals all having the same sequence pattern but being displaced relative to one another in time. In another form, the invention is applicable to apparatus utilising such repeated sequences of binary digits for scrambling binary information.

A known form of electric signal generator comprises an N stage binary shift register which is arranged for the digital information stored thereby to be shifted along the register under the control of a train of clock pulses and which has a feedback path to write into the first stage of the register a digit value that is dependent upon the digit values stored by a plurality of stages thereof, the shift register being thus arranged to take up 2N--1 I different conditions so that the output signal supplied by any one stage represents a repeated sequence of 2N-1 binary digits.Such a sequence is sometimes referred to as a "maximum length sequence Digital signals having maximum length sequences may, by virtue of their pseudorandom properties, be used in digital signalling systems as a substitute for normal traffic either when the system is undergoing test or is operating in a standby mode (i.e.

not actually carrying traffic). In a multichannel signalling system it is convenient for a plurality of such signals to be utilised, those signals all having the same sequence pattern but being time displaced relative to one another so that the starting point (say) of the sequence is approximately evenly spaced throughout the signals. This arrangement ensures that crosschannel interference is minimised. In one example it is required to have eight pseudo-random digital signals each representing a repeated sequence of 2'5-1 (i.e. 32,767) binary digits and this means that in seven of the signals the sequences start after successive delays of 2'2 (i.e. 4096) digits while the eighth signal sequence starts after a further delay of 4095 digits.If now a known form of maximum length sequence signal generator is utilised to supply one of those eight signals the other seven signals may be derived by suitably delaying the signal supplied by the generator but, in view of the number of digits involved, this arrangement would necessitate the use of large shift registers or lengthy delay lines.

It is an object of the present invention to provide an improved form of scrambling apparatus utilising delayed sequences of pseudo-random digits.

According to the present invention digital scrambling apparatus comprises a multiplicity of delay elements which together have a total delay of N units of time, a multiplicity of first means associated one with each of said delay elements to derive a signal by modulo-2 addition of two binary signals which are each supplied by one of said delay elements (or a part of such a delay element having a delay of at least one unit of time), and a multiplicity of second means each arranged to derive the input signals to one of said delay elements by modulo-2 addition of the binary signal supplied by the first means associated with that delay element and a binary signal carrying input information to be scrambled, the input signal of those delay elements (if any) not having an associated second means being supplied by the associated first means and the arrangement being such that, in the absence of any information to be scrambled, each of said delay elements supplies a binary output signal having a repeated sequence of 2N-1 digits and the time elapsed between the start of an appearance of a part of the repeated sequence at a first output and the start of an appearance of said part of the repeated sequence at a second output is approximately equal to the time elapsed between the part of said appearance of the part of the repeated sequence at the second output and the start of an appearance of said part of the repeated sequence at a third output.

In order to generate the repeated sequence of 2N-1 digits it is essential for the number of said delay elements and 2N-1 to have no common factor. To achieve this it is usual for the delay introduced by all said delay elements not to be exactly the same and preferably the delays introduced thereby differ by only one unit of time. In a particular example, all but one of the delay elements are each arranged to effect a delay equal to two digit periods of the binary input signal theretq while the remaining delay element is arranged to effect a delay equal to either one or three such digit periods.

An embodiment of the invention will now be described - by way of example with reference to the three figures of the accompanying drawings in which Figure 1 shows diagrammatically a signal generator for generating pseudo-random signals, Figure 2 shows diagrammatically scrambling apparatus in accordance with the invention, and Figure 3 shows diagrammatically descrambling apparatus for use with the scrambling apparatus of Figure 2.

The signal generator now to be described with reference to Figure 1 of the accompanying drawing is arranged to supply eight signals of the form previously mentioned herein in that each signal consists of a repeated sequence of 32,767 digits and the sequences of the eight signals are approximately evenly interlaced.

Referring to Figure 1 of the accompanying drawing, the generator comprises eight delay elements IA to 1H which are connected respectively between eight modulo-2 adders 2A to 2H and eight output terminals 3A to 3H at which the required output signals are developed. Each of the delay elements IA to IG is arranged to effect a delay equal to two digit periods of the output signals. The delay element IG, for example, is shown as two digit delay units 4 and 5 and may conveniently be formed by a two-stage shift register which is arranged in known manner to operate under the control of a clock pulse source (not shown) operating at the digit rate of the required output signals.The delay element 1H, on the other hand, is only arranged to effect a delay equal to one digit period but may again be a device operating under the control of clock pulses supplied by said source.

It will be seen from the drawings that the delay elements 1A to 1H are arranged in cyclic order as far as interconnections between the output sides thereof and the associated adders 2A to 2H are concerned.

More particularly, the input signals to the delay elements IB to 1H ae supplied respectively by the modulo-2 adders 2B to 2H and each of these adders effects modulo2 addition of the binary signals supplied by the two preceding delay elements, e.g. the adder 2D derives the input signal for the delay elements ID by modulo-2 addition of the signals supplied by the delay elements IB and IC.The adder 2A derives the input signal for the delay element IA by modulo-2 addition of the binary signal supplied by the immediately preceding delay element 1H (which only introduces a delay of one digit period) and a binary signal which is taken from the junction of the delay units 4 and 5 of the next preceding delay element 1G and which is the input signal fed to the delay element 1G delayed by one digit period.

It is understood that an electric signal generator in accordance with the invention does not necessarily have the same number of output terminals as delay elements. Thus, in the example described above, if only six output signals were required, the output terminals 3G and 3H could be omitted without affecting the number of digits in the repeated sequences of the output signals or the interlacing of the remaining sequences.

If now the signal generator of Figure 1 has eight further modulo-2 adders connected respectively between the adders 2A to 2H and the delay elements IA to 1H and each of these further adders has a unique input path which is connected to it and which carries a binary data signal (having the same digit rate as the generator), the signals developed at the output terminals 3A to 3H respectively carry the required data in scrambled form. In other words, the arrangement then. constitutes digital scrambling apparatus although it will be appreciated that, in the absence of any data signals on the input paths, it generates the eight pseudo-random binary signals as previously described. It will be appreciated that not all the eight delay elements IA to 1H need necessarily have a further modulo2 adder to supply the input signal thereto in the manner just described.

Referring now to Figure 2 of the accompanying drawings, the scrambling apparatus shown in that figure has nine delay units 21 each of which is arranged (e.g. under the control of a source of clock pulses which is not shown) to subject binary signals supplied there to the same time delay. The units 21 are connected to form four delay elements 22A to 22D which can be considered to be in cyclic order.

Each of the delay elements 22A to 22D has two modulo-2 adders 23A, 23B, 23C or 23D and 24A, 24B, 24C, or 24D connected in series on its input side. The adder 23B, for example, passes on to the adder 24B a binary signal formed by modulo-2 addition of the binary signal supplied by the next delay element, namely the element 22C, and the binary signal supplied by the first unit 21 of the delay element 22B. The adder 24B, for example, derives the binary input signals to the delay element 22B by modulo-2 addition of the signal supplied by the adder 23B and an input binary signal on a path 25B.

The apparatus under consideration operates so that output binary signals on the paths 26A to 26D carry the information of the input binary signals on paths 25A to 25D respectively in scrambled form. (The parallel signals supplied to the paths 25A to 25D may conveniently be derived by means of demultiplexer (not shown) from a single signal carrying the binary information in serial form). It will, of course, be appreciated that when there are no input signals on the paths 25A to 25D (or those signals all have the same steady value signifying that they are not carrying binary data), the apparatus operates as a pseudorandom sequence generator, the binary signals then appearing on the paths 26A to 26D each having a sequence of 511 (i.e.

2-l) bits and the timing of the four signals being approximately evenly spaced.

The binary signals on the paths 26A to 26D are combined in time division multiplex in known manner. For this purpose, a clock pulse generator 27 which operates at four times the bit rate of the signals on the paths 26A to 26D supplied a train of clock pulses to a pulse distributor 28 which distributes those clock pulses cyclically between four leads 29A to 29D. Sampling circuits 30A to 30D are arranged to sample the signals on the paths 26A to 26D in response to pulses on the leads 29A to 29D and the pulse signals passed by the circuits 30A to 30D are combined to give the required multiplexed output signal on a path 20.

Referring now to Figure 3 of the accompanying drawings, the scrambled signal (as supplied by the apparatus of Figure 2) carrying information in respect of the four binary signals is passed over a path 36 to a demultiplexer 37 which supplies to paths 33A to 33D four binary signals corresponding to those on paths 26A to 26D (Figure 2). The arrangement for descrambling the signals on the paths 33A to 33D is similar to the scrambling arrangement of Figure 2 in that there are provided four delay elements 31A to 31D which are identical to the delay elements 22A to 22D (Figure 2) and modulo-2 adders 32A to 32D which derive correspondingly binary signals to the modulo-2 adders 23A to 23D (Figure 2).The scrambled signals supplied over paths 24A to 24D (Figure 2) are passed via input paths 33A to 33D respectively to the delay elements 31A to 31D. The signals supplied by the adders 32A to 32D and the input signals on the paths 33A to 33D are combined by means of modulo-2 adders 34A to 34D so as to supply the required descrambled signals to output paths 35A to 35D.

WHAT WE CLAIM IS: 1. Digital scrambling apparatus comprising a multiplicity of delay elements which together have a total delay of N units of time, a multiplicity of first means associated one with each of said delay elements to derive a signal by modulo-2 addition of at least two binary signals which are each supplied by one of said delay elements (or a part of such a delay element having a delay of at least one unit of time), and a multiplicity of second means each arranged to derive the input signals to one of such delay elements by modulo-2 addition of the binary signal supplied by the first means associated with that delay element and a binary signal carrying input information to be scrambled, the input signal of those delay elements (if any) not having an associated second means being supplied by the associated first means and the arrangement being such that, in the absence of any information to be scrambled, each of said delay elements supplies a binary output signal having a repeated sequence of 2N-1 digits and the time elapsed between the start of an appearance of a part of the repeated sequence at a first output and the start of an appearance of said part of the repeated sequence at a second output is approximately equal to the time elapsed between the start of said apperance of the part of the repeated sequence at the second output and the start of an appearance of said part of the repeated sequence at a third output.

2. Apparatus according to Claim 1 wherein the multiplexing means is provided to derive a single signal carrying in time division multiplex the information of the signals supplied by all said delay elements.

3. Apparatus according to Claim 1 or Claim 2 wherein said delay elements introduce delays which differ by only one of said units of time.

4. Apparatus according to Claim 3 wherein all but one of the delay elements

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (5)

**WARNING** start of CLMS field may overlap end of DESC **. pulses which is not shown) to subject binary signals supplied there to the same time delay. The units 21 are connected to form four delay elements 22A to 22D which can be considered to be in cyclic order. Each of the delay elements 22A to 22D has two modulo-2 adders 23A, 23B, 23C or 23D and 24A, 24B, 24C, or 24D connected in series on its input side. The adder 23B, for example, passes on to the adder 24B a binary signal formed by modulo-2 addition of the binary signal supplied by the next delay element, namely the element 22C, and the binary signal supplied by the first unit 21 of the delay element 22B. The adder 24B, for example, derives the binary input signals to the delay element 22B by modulo-2 addition of the signal supplied by the adder 23B and an input binary signal on a path 25B. The apparatus under consideration operates so that output binary signals on the paths 26A to 26D carry the information of the input binary signals on paths 25A to 25D respectively in scrambled form. (The parallel signals supplied to the paths 25A to 25D may conveniently be derived by means of demultiplexer (not shown) from a single signal carrying the binary information in serial form). It will, of course, be appreciated that when there are no input signals on the paths 25A to 25D (or those signals all have the same steady value signifying that they are not carrying binary data), the apparatus operates as a pseudorandom sequence generator, the binary signals then appearing on the paths 26A to 26D each having a sequence of 511 (i.e. 2-l) bits and the timing of the four signals being approximately evenly spaced. The binary signals on the paths 26A to 26D are combined in time division multiplex in known manner. For this purpose, a clock pulse generator 27 which operates at four times the bit rate of the signals on the paths 26A to 26D supplied a train of clock pulses to a pulse distributor 28 which distributes those clock pulses cyclically between four leads 29A to 29D. Sampling circuits 30A to 30D are arranged to sample the signals on the paths 26A to 26D in response to pulses on the leads 29A to 29D and the pulse signals passed by the circuits 30A to 30D are combined to give the required multiplexed output signal on a path 20. Referring now to Figure 3 of the accompanying drawings, the scrambled signal (as supplied by the apparatus of Figure 2) carrying information in respect of the four binary signals is passed over a path 36 to a demultiplexer 37 which supplies to paths 33A to 33D four binary signals corresponding to those on paths 26A to 26D (Figure 2). The arrangement for descrambling the signals on the paths 33A to 33D is similar to the scrambling arrangement of Figure 2 in that there are provided four delay elements 31A to 31D which are identical to the delay elements 22A to 22D (Figure 2) and modulo-2 adders 32A to 32D which derive correspondingly binary signals to the modulo-2 adders 23A to 23D (Figure 2).The scrambled signals supplied over paths 24A to 24D (Figure 2) are passed via input paths 33A to 33D respectively to the delay elements 31A to 31D. The signals supplied by the adders 32A to 32D and the input signals on the paths 33A to 33D are combined by means of modulo-2 adders 34A to 34D so as to supply the required descrambled signals to output paths 35A to 35D. WHAT WE CLAIM IS:

1. Digital scrambling apparatus comprising a multiplicity of delay elements which together have a total delay of N units of time, a multiplicity of first means associated one with each of said delay elements to derive a signal by modulo-2 addition of at least two binary signals which are each supplied by one of said delay elements (or a part of such a delay element having a delay of at least one unit of time), and a multiplicity of second means each arranged to derive the input signals to one of such delay elements by modulo-2 addition of the binary signal supplied by the first means associated with that delay element and a binary signal carrying input information to be scrambled, the input signal of those delay elements (if any) not having an associated second means being supplied by the associated first means and the arrangement being such that, in the absence of any information to be scrambled, each of said delay elements supplies a binary output signal having a repeated sequence of 2N-1 digits and the time elapsed between the start of an appearance of a part of the repeated sequence at a first output and the start of an appearance of said part of the repeated sequence at a second output is approximately equal to the time elapsed between the start of said apperance of the part of the repeated sequence at the second output and the start of an appearance of said part of the repeated sequence at a third output.

2. Apparatus according to Claim 1 wherein the multiplexing means is provided to derive a single signal carrying in time division multiplex the information of the signals supplied by all said delay elements.

3. Apparatus according to Claim 1 or Claim 2 wherein said delay elements introduce delays which differ by only one of said units of time.

4. Apparatus according to Claim 3 wherein all but one of the delay elements

are arranged to effect a delay equal to two of said units of time and the remaining delay element is arranged to effect a delay equal to either one or three such units of time.

5. Digital scrambling apparatus substantially as hereinbefore described with reference to Figure 2 of the accompanying drawings.