GB1410396A - Means for synchronizing clocks in a time ordered communications system - Google Patents

Abstract

1410396 Master and slave clock systems BENDIX CORP 18 Sept 1973 [2 Oct 1972] 43729/73 Heading G3T In a system for periodically checking and correcting a remote station clock (e.g. in an aircraft) to maintain it synchronized with a master clock (e.g. on a ground station), the local clock is driven at a local frequency derived from a local crystal controlled oscillator 10 Fig. 1 and synchronizing pulses are transmitted by radio to the or each remote clock station. Correction is effected upon receipt of each synch pulse and is also continuously effected to compensate for oscillator drift in the periods between synch pulses, the correction being by adding or deleting pulses from the local oscillator output by means of a gate circuit arrangement 14 (detailed in Fig. 3 (not shown)). In the remote station each synchronizing signal received is decoded to produce an external reference pulse (ERP) a predetermined time, dependent upon the delay in the decoding process, after the synch pulse. In addition a digital frequency divider 16 (16a in Fig. 2 (not shown)) produces an internal reference pulse (IRP) for every n<SP>th</SP> pulse applied to it and sends out signals 18 to operate known clock equipment not described. If the local clock is exactly synchronized the IRP would be produced at the same instant as the ERP. The remote station also generates a respective time window symmetrically about each IRP from the divider 16. If an ERP occurs during the period of the window the time difference or error between the ERP and IRP therein and its sign are determined by a unit 20 including an aperture generator (32) Fig. 2 (not shown), which produces a pulse which is started by either the ERP or IRP (whichever is first) and is terminated by the other, and a pulse rate generator (34) which produces a number of pulses as a measure of the time difference and which are stored in a counter (42). A synch pulse and ERP will not be present for a large percentage of IRPs; a flip-flop (30) indicating after each window whether an ERP was received. From the measured time difference a divider (62) in a calculator 22 produces a correction signal Ea as a measure of the instantaneous misalignment of the local clock. This signal together with its sign is applied to the gate circuit arrangement 14 to add or subtract a pulse from the oscillator 10 output. Further correction is effected to correct for oscillator drift and maintain the local clock synchronized to the master in the periods between the correction signals Ea. This is effected by determining the first and second derivatives of the time difference between ERP and IRP to produce signals Eb and Ec respectively. These signals are applied to a frequency controller 24 including an offset register (75) and an offset generator (77) to produce a correction signal Ef which is a pulse train. Ef is applied continuously to the gate arrangement 14 to add or subtract pulses from the oscillator output, whereas correction pulses Ea are applied only when an ERP pulse is received.