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GB1306189A - - Google Patents

Info

Publication number
GB1306189A
GB1306189A GB2323571A GB2323571A GB1306189A GB 1306189 A GB1306189 A GB 1306189A GB 2323571 A GB2323571 A GB 2323571A GB 2323571 A GB2323571 A GB 2323571A GB 1306189 A GB1306189 A GB 1306189A
Authority
GB
United Kingdom
Prior art keywords
metallization
cells
points
faulty
interconnections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2323571A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GB1306189A publication Critical patent/GB1306189A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

1306189 Repairable integrated circuits HUGHES AIRCRAFT CO 19 April 1971 [5 March 1970] 23235/71 Addition to 1282177 Heading H1K An integrated circuit substrate comprises an array of randomly distributed good cells each provided with terminals. The array is covered with an apertured insulating layer exposing the terminals of selected ones of the good cells, and the layer is covered with a metallization layer which effectively relocates the selected cells (where necessary) to points on a predetermined master circuit pattern common to a set of substrates and which also provides conductive segments at predetermined locations to later act as oross-unders. A further insulating layer may be apertured using a mask common to all wafers of the same type and which exposes the said points and the terminations of the crossunders. Another mask common to all wafers of the same type is used to provide a predetermined pattern of metallization which links some of the points (and their associated cells) into a specific circuit arrangement and which provides the remaining points, which are associated with the remainder of the selected cells, with isolated terminal pads. Since all the interconnections are thus made accessible in the uppermost level of metallization it is possible to determine readily the identity of any cell of the specific circuit arrangement now found faulty (for example as a result of bad metallization or bad inter-level insulation) or which becomes faulty in use. The faulty cell may be isolated by laser cutting or etching away its interconnections and one of the (redundant) remainder of the selected cells is placed in circuit by, for example, soldering jumper wires between its isolated terminal pads and those interconnections severed from the faulty cell.
GB2323571A 1968-09-25 1971-04-19 Expired GB1306189A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US76245968A 1968-09-25 1968-09-25
US1686970A 1970-03-05 1970-03-05

Publications (1)

Publication Number Publication Date
GB1306189A true GB1306189A (en) 1973-02-07

Family

ID=34315864

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2323571A Expired GB1306189A (en) 1968-09-25 1971-04-19

Country Status (1)

Country Link
GB (1) GB1306189A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2418906A1 (en) * 1973-04-30 1974-12-12 Hughes Aircraft Co METHOD OF CONNECTING THE CIRCUITS CREATED IN A SEMICONDUCTOR DISC
EP0023294A2 (en) * 1979-07-30 1981-02-04 International Business Machines Corporation Method for repairing integrated circuits
GB2153590A (en) * 1984-02-01 1985-08-21 Ramesh Chandra Varshney Matrix of functional circuits on a semiconductor wafer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2418906A1 (en) * 1973-04-30 1974-12-12 Hughes Aircraft Co METHOD OF CONNECTING THE CIRCUITS CREATED IN A SEMICONDUCTOR DISC
EP0023294A2 (en) * 1979-07-30 1981-02-04 International Business Machines Corporation Method for repairing integrated circuits
EP0023294A3 (en) * 1979-07-30 1983-08-31 International Business Machines Corporation Method for repairing integrated circuits
GB2153590A (en) * 1984-02-01 1985-08-21 Ramesh Chandra Varshney Matrix of functional circuits on a semiconductor wafer

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Legal Events

Date Code Title Description
PS Patent sealed
PE20 Patent expired after termination of 20 years