GB1304742A - - Google Patents

Abstract

1304742 D.C.-D.C. converters ENCON ELECTRONICS Ltd and M C JACKSON 25 May 1971 [26 May 1970] 25172/70 Heading H2F [Also in Division H3] A pulse generating circuit comprises a first switch 31, e.g. a PUT, having two inputs 54, 56 coupled in a balanced arrangement to a D.C. source i.e. via impedances 32-35 and 29, 30, so that conduction of the switch 31 is achieved periodically in which state a signal is applied to the control electrode of a second switch 46, e.g. an SCR, for the production of output pulses and an arrangement e.g. a ganged control switch 36, 37 for adjusting the pulse rate independently of the pulse amplitude and an arrangement e.g. variable resistor 21, for adjusting the pulse amplitude independently of the pulse rate. The time constant of a charging network 32-35 determines the conduction of PUT 31 and hence the rate of the timing pulses produced, which pulses trigger a controlled rectifier 46 so that a charge stored in capacitors 39-41 is discharged via a primary winding 49, with the consequent production of high tension pulses across the secondary 50. The charging circuit for the capacitors 39-41 includes a converter formed of a ringing choke oscillator circuit comprising a transistor 26 which is turned full on when a switch 15 is closed so that the current through a primary winding 24 increases linearly until a maximum limit determined by a resistor 21 is reached when transistor 26 is turned off and a reverse voltage is developed across the secondaries 20, 28 as the magnetic field in the transformer collapses. This reverse voltage is applied via a diode 38 to charge capacitors 39-41 with the above operations being repeated periodically. A pulse lengthening circuit 42, 43, 45 enables an indicating neon tube 48 to be operating even after the discharge of capacitors 39-41 is completed.