GB1341382A - Digital signal transmission system - Google Patents

Abstract

1341382 Multiplex pulse code signalling A COOK 19 April 1971 [20 Jan 1970] 2788/70 Heading H4L In a digital transmission system including a plurality of stations interconnected by links, each station having independent clock pulse generating means, each link includes means responsive to the time of propagation of a signal in both directions over the link as measured with reference to the clock pulse generating means of the originating station to maintain substantially constant the propagation time over the link in each direction. General description.-As shown in Fig. 1, a station 1 is connected by a link 3, including GO and RETURN conductors 4, 5 to a station 2. At station 1 a pattern signal generator 6 supplies a pattern to an OR gate 7 which also receives the message signals via input 8. The output of gate 7 is supplied via a variable delay 9 and conductor 4 to the output 10 of station 2 via gate 11. The pattern signal is separated by gate 11 and returned via gate 12, 13 and conductor 5 to the station 1 where it is passed via a variable delay 14, similar to delay 9, to a time measure and control unit 15. At 15 the returned pattern signal is compared with the pattern signal generated at 6 and the number of digits delay produced by the link 3 together with the delays 9, 14 is compared with a standard number specified for the link, the error signal thus derived controlling the delays 9, 14 accordingly. A pattern recognition device 18, provides a signal indicating the arrival of the pattern signals at station 2 and the current clock reading of station 1 plus the standard delay of link 3 in one direction. Station 2 is provided with similar equipment and connected by a similar (outgoing) two-way link to station 1, and further stations may be interconnected in like manner with stations 1 and 2, Fig. 2 (not shown). System details, Fig. 3.-An incoming digital signal on link P from a station A is received via terminal TA1 at station B and jitter is removed by circuit PD1 controlled by pulses PGT from clock generator PG and gate SG1, the output of gate SG1 being supplied to a buffer store via gate CG2 and to a timing circuit comprising a multi-digit register PT1 a pattern recognition unit PTR1 and a counter SC which produces signals CCR1 at the digit times of the incoming message signal and CCR2 at the digit times of the incoming pattern signal. A gate CG1 is enabled by signals CCR2 so that the pattern signal is returned on the link via OR gate CG3 and terminal TA2. The outgoing link Q is connected via terminals TB1, TB2 and includes similar variable delays VD1, VD2 controlled by circuit TM. The pattern signal is stored at PGA under the control of signals PGT from clock generator PG and when gate GG10 is enabled by clock signals CCT2 the pattern is transmitted via OR gate CG9 and delay VD1 to the outgoing terminal TB1. The time at which the last digit of the pattern leaves generator PGA is recognized at PGR which transmits a signal circuit TM. The pattern signal is returned via terminal TB2 and passed via delay VD2 to a pattern register PT2 and passed via delay VD2 to a pattern register PT2 so that a unit PTR2 applies a signal to circuit TM which is provided with means to control the delays VD1, VD2 similarly so as to keep the propagation time to the next station and back constant. Reverting to link P, the gate CG2 passes only the message digits via gates WG1 to WGr controlled by a shift register SR1, to respective storage elements of a store VDS1. The contents of the store are read out in the same order via gates RG1 to RGr under the control of a shift register SR2 driven by the local clock signals CCT1 and passed via a gate CG7 to the switching network SW. Signals at the local clock timing from SW are supplied via a gate CG5, stored in similar manner at VDS2 and read out and passed via gate CG4 to the gate CG3 at the timing appropriate to the link P. At CG3 the message signals are interspersed with the returning pattern signals and passed to line via terminal TA2. The signal CCR2 is supplied to a time computer as time A-B-A. Similar incoming links from stations X and Y are connected to network SW and provide time signals X-B-X- and Y-B-Y which are also supplied to the computer. Corresponding outgoing links (not shown) are provided for stations X, Y so that the arrangement is symmetrical. The computer estimates the current remote clock times from the time of arrival of the patterns modified by the standard delays of the individual links and provides a mean error signal to control the local clock generator via a phase control element PC. The time signals may be weighted according to their known standards of reliability. Should an oscillator become faulty a fault indication may be produced to permit the introduction of a standby oscillator.