GB1272132A - Receiver alarm system - Google Patents

Abstract

1,272,132. Radio receivers. PYE Ltd. 18 Dec., 1970 [22 Sept., 1969], No. 46539/69. Heading H3W. A receiving system wherein two receivers RxA, RxB respectively, are provided for the reception of an R.F. signal, each receiver including a squelch circuit arranged to give an output when the carrier level at the demodulator of the receiver exceeds a threshold value, includes an alarm circuit indicating failure of either receiver. The alarm circuit comprises a first memory circuit 5 settable, via AND gate 4, only by the simultaneous presence of squelch outputs from both receivers at any time during a transmission period, a second memory circuit 6 settable from an output from the first memory circuit 5 in the SET condition, and a reset circuit 8 responsive to the presence of an output from OR gate 3, i.e. a squelch output from either receiver during a transmission period and adapted to produce a reset pulse at the termination of that transmission period, the reset pulse being applied to the first memory circuit 5 via a first delay circuit 9 having a delay time at least equal to the duration of the reset pulse, and being applied directly to the second memory circuit 6, whereby the reset pulse is unable to reset the second memory circuit 6 at the end of a transmission period when the first memory circuit 5 has been set during that transmission period. A noise suppression circuit 7 may be connected in the input to reset unit 8, comprising a delay unit so arranged that a step function applied to its input produces a step function at its output after a delay time, but no output is produced if the input reverts to its original value before the end of the delay time. To indicate the conditions of the individual receivers lamps 15, 16 are provided, operated from the outputs of further memory circuits 11, 12 respectively. Memory circuit 11 has its SET input connected to the squelch output 1 of the first receiver RxA and its RESET input connected to the output of AND gate 13, the inputs to which comprise squelch signal 1 from receiver RxA, squelch signal 2 from receiver RxB applied through an inverter and a signal from memory 5 which inhibits gate 13 from giving an output when the memory is in the " A and B ON " condition. Memory circuit 12 is correspondingly connected to the squelch outputs of receivers RxB, RxA and an output from memory 5. To provide a constant audio output, signals from receivers RxA and RxB are fed to an audio switch unit 7 which contains a combining network and an attenuator in the combined output which is switched out in the absence of the output from AND gate 4 when either receiver is inoperative. In a modification of the arrangement, a counter (18, Fig. 2, not shown) is interposed between reset unit 8 and the reset input of memory 6, the counter being driven from the output of memory 5; in this way, the alarm is only operated after a number reversals of the memory 5. In a further modification (Fig. 3, not shown), each receiver provides a first squelch circuit giving an output when the R.F. carrier level at its demodulator reaches a first threshold level, and a second squelch circuit giving an output at a higher threshold level; the first squelch circuits operate the AND gate 4 and the second squelch circuits are used to operate the OR gate 3.