GB0201334D0 - Method of measuring the accuracy of a clock signal - Google Patents
Method of measuring the accuracy of a clock signalInfo
- Publication number
- GB0201334D0 GB0201334D0 GBGB0201334.0A GB0201334A GB0201334D0 GB 0201334 D0 GB0201334 D0 GB 0201334D0 GB 0201334 A GB0201334 A GB 0201334A GB 0201334 D0 GB0201334 D0 GB 0201334D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- accuracy
- measuring
- clock signal
- clock
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB0201334.0A GB0201334D0 (en) | 2002-01-22 | 2002-01-22 | Method of measuring the accuracy of a clock signal |
DE10302233A DE10302233A1 (en) | 2002-01-22 | 2003-01-20 | Method of measuring the accuracy of a clock signal |
FR0300648A FR2835122B1 (en) | 2002-01-22 | 2003-01-22 | CIRCUIT FOR MEASURING THE PRECISION OF A CLOCK SIGNAL AND ASSOCIATED METHOD |
CN03101835A CN1434585A (en) | 2002-01-22 | 2003-01-22 | System and method for measuring clock signal accuracy |
KR10-2003-0004343A KR20030063243A (en) | 2002-01-22 | 2003-01-22 | Method of Measuring the Accuracy of a Clock Signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB0201334.0A GB0201334D0 (en) | 2002-01-22 | 2002-01-22 | Method of measuring the accuracy of a clock signal |
Publications (1)
Publication Number | Publication Date |
---|---|
GB0201334D0 true GB0201334D0 (en) | 2002-03-13 |
Family
ID=9929465
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GBGB0201334.0A Ceased GB0201334D0 (en) | 2002-01-22 | 2002-01-22 | Method of measuring the accuracy of a clock signal |
Country Status (5)
Country | Link |
---|---|
KR (1) | KR20030063243A (en) |
CN (1) | CN1434585A (en) |
DE (1) | DE10302233A1 (en) |
FR (1) | FR2835122B1 (en) |
GB (1) | GB0201334D0 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110365333B (en) * | 2019-05-30 | 2022-11-18 | 芯创智(北京)微电子有限公司 | Differential integration half-digital phase-locked loop |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4633193A (en) * | 1985-12-02 | 1986-12-30 | At&T Bell Laboratories | Clock circuit synchronizer using a frequency synthesizer controlled by a frequency estimator |
DE19842711C2 (en) * | 1998-09-17 | 2002-01-31 | Infineon Technologies Ag | Circuit for data signal recovery and clock signal regeneration |
JP2000244309A (en) * | 1999-02-18 | 2000-09-08 | Mitsubishi Electric Corp | Clock generating circuit and semiconductor device |
GB2363268B (en) * | 2000-06-08 | 2004-04-14 | Mitel Corp | Timing circuit with dual phase locked loops |
-
2002
- 2002-01-22 GB GBGB0201334.0A patent/GB0201334D0/en not_active Ceased
-
2003
- 2003-01-20 DE DE10302233A patent/DE10302233A1/en not_active Withdrawn
- 2003-01-22 CN CN03101835A patent/CN1434585A/en active Pending
- 2003-01-22 FR FR0300648A patent/FR2835122B1/en not_active Expired - Fee Related
- 2003-01-22 KR KR10-2003-0004343A patent/KR20030063243A/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
FR2835122B1 (en) | 2005-05-20 |
CN1434585A (en) | 2003-08-06 |
FR2835122A1 (en) | 2003-07-25 |
KR20030063243A (en) | 2003-07-28 |
DE10302233A1 (en) | 2003-12-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
AT | Applications terminated before publication under section 16(1) |