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FR3121261B1 - DRAM memory device configured to allow management of a rank hammering effect with a range p greater than or equal to 2 - Google Patents

DRAM memory device configured to allow management of a rank hammering effect with a range p greater than or equal to 2 Download PDF

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Publication number
FR3121261B1
FR3121261B1 FR2103164A FR2103164A FR3121261B1 FR 3121261 B1 FR3121261 B1 FR 3121261B1 FR 2103164 A FR2103164 A FR 2103164A FR 2103164 A FR2103164 A FR 2103164A FR 3121261 B1 FR3121261 B1 FR 3121261B1
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FR
France
Prior art keywords
rank
hammering
range
memory device
equal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2103164A
Other languages
French (fr)
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FR3121261A1 (en
Inventor
Fabrice Devaux
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Upmem SAS
Original Assignee
Upmem SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Upmem SAS filed Critical Upmem SAS
Priority to FR2103164A priority Critical patent/FR3121261B1/en
Publication of FR3121261A1 publication Critical patent/FR3121261A1/en
Application granted granted Critical
Publication of FR3121261B1 publication Critical patent/FR3121261B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40622—Partial refresh of memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

L’invention concerne un dispositif mémoire (100) pourvu d’un tableau de mémoire DRAM (200) et configuré pour prévenir un effet de martelage de rang susceptible de survenir entre les rangs de mémoire formant ledit tableau. Notamment, le dispositif mémoire met en œuvre des compteurs d’activation (Cai) des rangs de mémoire et un bloc logique de rafraîchissement (300) configuré pour initier des rafraîchissements préventifs dès lors qu’un critère associé au comptage du nombre d’activations de chacun des rangs de mémoire est vérifié. Dans le contexte de la présente invention, la portée du martelage de rang est supérieure ou égale à 2 de sorte que la seule comparaison du nombre d’activations de chacun des rangs avec la valeur de martelage critique M ne suffit plus à en prévenir les effets. La présente invention propose d’établir un nouveau critère de comptage basé sur la portée p du martelage de rang. Figur e 1A memory device (100) has a DRAM array (200) and is configured to prevent a rank hammering effect that may occur between the memory ranks forming the array. In particular, the memory device implements activation counters (Cai) of the memory ranks and a refresh logic block (300) configured to initiate preventive refreshes as soon as a criterion associated with counting the number of activations of each of the memory ranks is checked. In the context of the present invention, the range of the rank hammering is greater than or equal to 2 so that the mere comparison of the number of activations of each of the ranks with the critical hammering value M is no longer sufficient to prevent its effects. . The present invention proposes to establish a new counting criterion based on the range p of row hammering. Figure 1

FR2103164A 2021-03-29 2021-03-29 DRAM memory device configured to allow management of a rank hammering effect with a range p greater than or equal to 2 Active FR3121261B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR2103164A FR3121261B1 (en) 2021-03-29 2021-03-29 DRAM memory device configured to allow management of a rank hammering effect with a range p greater than or equal to 2

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2103164A FR3121261B1 (en) 2021-03-29 2021-03-29 DRAM memory device configured to allow management of a rank hammering effect with a range p greater than or equal to 2
FR2103164 2021-03-29

Publications (2)

Publication Number Publication Date
FR3121261A1 FR3121261A1 (en) 2022-09-30
FR3121261B1 true FR3121261B1 (en) 2024-03-08

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
FR2103164A Active FR3121261B1 (en) 2021-03-29 2021-03-29 DRAM memory device configured to allow management of a rank hammering effect with a range p greater than or equal to 2

Country Status (1)

Country Link
FR (1) FR3121261B1 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9431085B2 (en) * 2014-03-28 2016-08-30 Synopsys, Inc. Most activated memory portion handling
KR102403341B1 (en) 2016-03-17 2022-06-02 에스케이하이닉스 주식회사 Memory and system including the same
US10825534B2 (en) * 2018-10-26 2020-11-03 Intel Corporation Per row activation count values embedded in storage cell array storage cells
US10943637B2 (en) * 2018-12-27 2021-03-09 Micron Technology, Inc. Apparatus with a row-hammer address latch mechanism
FR3111731B1 (en) * 2020-06-23 2023-01-06 Upmem Method and circuit for protecting a DRAM memory device from the rank hammering effect

Also Published As

Publication number Publication date
FR3121261A1 (en) 2022-09-30

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