FR2922037A1 - Data i.e. bank data, securing method for e.g. static RAM of programmable electronic circuit in airplane, involves instantiating memory accesses with addresses, and providing read data at output based on result of parity control on read data - Google Patents

Abstract

The method involves dividing a memory space of each dual port RAM component into a main space (A) and an auxiliary space (B), and allocating each reading and writing access port (PortA, PortB) to the memory space. Simultaneous memory accesses with corresponding distinct memory addresses (Ad1, Ad2) are instantiated, where the accesses allow writing of data (D) i.e. bank data, with a parity bit and reading of the data on the ports, respectively. The read data is provided at a reading output (Dout) based on the result of parity control on the read data.

Description

METHOD OF SECURING DATA IN MEMORY LIVING

The present invention relates to a method of securing the RAM data, in particular with respect to so-called logical random events SEU for "Single Event Upset" and a corresponding memory architecture. A logical hazard is a phenomenon in itself nondestructive, which results in an inadvertent change in the logical state of a memory point, following collisions with heavy ions, protons, or neutrons. Programmable electronic circuits embedded in aircraft, aircraft, probes or others, or electronic circuits used in certain radiative terrestrial environments, for example in the medical or nuclear environment, and which are circuits generally subject to very high reliability constraints, are particularly exposed to these logical hazards. These hazards will affect more particularly the points of RAM, both static (SRAM) and dynamic (DRAM). These alterations of the information contained in memory can have very serious consequences, depending on the data that are reached and their functions in the application process (es) of a programmable electronic circuit. In particular, alterations on static data, such as constants, or variables having a remanence with respect to an application process, and on quasi-static data such as variables whose current value depends on previous values, can cause significant damage. In general, the reliability of the electronic circuit is degraded. For these reasons, solutions to detect and preferably also correct, errors caused by these hazards have been developed.

Among these solutions, techniques based on the implementation of error correction code such as the Reed Solomon code or the Hamming code on the memory access paths have developed. In a simplified manner, these techniques associate a correction code to each word, which enables the receiver of the data to verify the integrity of the data transferred and, where appropriate, to correct errors. The length of the code depends on the length of the data structure in memory. For a Hamming code for example, an N-bit data structure is typically associated with an n-bit correction code with 2n> N + n if it is desired to be able to correct all simple errors (1 bit). These techniques are effective but expensive in terms of processing resources (detection and correction). Their use is very well justified especially in the case where a large volume of memory is accessible temporally multiplexed on a single path (a bus). In this case, the detection / correction device is unique and is preferably located in the single path between the memories and the user device of the information contained in this or these memories.

But there are other applications in which a large number of small RAMs, typically a few kilobytes each, are used locally, by a clean path by an equivalent number of user devices, usually wired operators. This situation is typically encountered in programmable electronic circuits whose architecture includes several individually usable banks or regroupable memory banks, to form a large capacity memory space. The memory components used are then part of the particular structure of the programmable circuit chosen to implement the desired function.

For these applications, the use of an error correction code such as a Hamming code, on each specific path, to secure a small amount of data, is very poorly adapted to the investment required. (processing time and resources required). In the invention, an efficient and inexpensive technique has thus been sought, which is adapted to secure the data of low capacity RAM banks such as those present in programmable circuit architectures. More generally, we have sought in the invention an easy and inexpensive security technique to implement for RAM data of an electronic circuit. The memory devices present in the programmable circuits generally propose organizations that make it possible to encode a parity per word used: these devices offer the possibility of storing at each memory address, a word of useful bits plus at least one corresponding parity bit. In practice 9-bit devices are common, but there are other devices (18 bits, or more). The use of this possibility assumes means of managing this parity, and in particular a parity check circuit, for intercepting the data read in memory before their transmission to the requesting process: if the parity is good, this circuit will delete data. read the associated parity bit before passing it to the requesting process. In the event of a parity error, this circuit will consider the data invalid and will generate a parity error. This parity error is used to warn the risk process to use the data. 1 o Recall that the parity check consists in counting the number of bits to 1 in the data considered, and to set to 1 or 0 a corresponding parity bit. This parity bit represents the parity of the data. In even parity, the parity bit will be 1, if the word contains an even number of 1, and 0 if the word contains an odd number of 1. In the case of odd parity, it is the reverse. The parity check then consists, before transmitting the data to the process or device that requests it, to recheck the parity, on the set given + parity bit. Thus, if a bit of the data or the parity bit has been changed, for example from state 1 to state 0, the total number of 20 1 changes. If the recalculated parity does not match the stored parity, an error is detected. If two states of 1 go to 0, the error will not be detected, but the probability of this happening is very small. These memory devices which propose at least one additional column of data per word to save a parity bit calculated by stored word can thus be used to detect logical random errors. These memories used in the programmable circuits, if they make it possible to detect memory errors due to logical randomness, generally do not make it possible to correct the error, contrary to the error correction codes indicated previously. Or depending on the function of one or more data affected by an error, the process may then be forced to force a reboot with reset. This type of action is very heavy and penalizing.

An object of the invention is a method which makes it possible to improve the reliability of the data in random access memory. One idea underlying the technical solution of the invention is to use a single parity bit per memory word, and to combine this parity with a redundancy scheme that allows a correction. Note that the term memory word is used here simply to designate all the memory points at a memory position, not related to the number of memory points. The use of a single parity bit per memory word is easily achievable in an application, taking as convention that the exchanges between the RAM space and the user application processes or devices, are performed on words that have a bit less than the word of the memory structure. By way of example, if the RAM space is formed with 9-bit memory components, the application processes or devices will manipulate 8-bit words. An object of the invention is thus a method for securing data in random access memory, which uses a parity bit per memory word, combined with a redundant organization of the memory space, so as to increase the reliability of the memory. In a refinement, it advantageously incorporates a correction process in memory. The invention therefore relates to a method for securing the data of a random access memory formed by at least one memory component, characterized in that each memory component is of the configurable type in dual port access on a first port and a second port, and such that each memory address makes it possible to store n useful bits of data and at least one additional bit, characterized in that it comprises dividing the memory space of each memory component into a main space and a spare space, the allocation a read and write access port different to each space, in that each access to write data to a memory address, it instantiates two simultaneous memory access to two different addresses, access to each port , to write said data with a corresponding parity bit, and in that each read access to a memory address, it instantiates two simultaneous memory accesses to two distributed addresses. corresponding nctes, an access on each port, to read a corresponding data on each port, and provides reading output of one or the other data read according to the result of a parity check on each of said read data. The invention also relates to a memory architecture enabling the implementation of such a method, and a programmable circuit comprising a secure RAM space according to the invention. Other advantages and features of the invention are detailed in the following description with reference to the illustrated drawings of one embodiment of the invention, given by way of non-limiting example. In these drawings: FIG. 1 illustrates a method for securing RAM data according to the invention; FIG. 2 is a diagram illustrating a processing according to the invention of wide data of several bytes; and FIG. 3 is an example of a memory architecture according to the invention. FIG. 1 is an illustration of a method of securing 100.0 of data contained in a DPM random access memory component of an electronic circuit which may further comprise one or more processors and other electronic components, which can access that memory. component 20 by an external bus (BUS in the figure). The RAM space of the programmable electronic circuit may include in practice one or more memory components of the same type to achieve a certain capacity. The method of the invention which will be described applies in the same way to each of the memory components of this memory space, in its own right. The security process 100.0 according to the invention makes it possible to more reliably and simply manage the data in memory of a DPM memory component of RAM by a redundancy scheme combined with a parity error detection. . To apply this security method, the memory component DPM must have both of the following characteristics: a). allow two independent read / write simultaneous memory accesses. We are talking about dual port access. It comprises in practice two ports (interface) Port A and Port B with the associated address, data and control signals for reading or writing access to the memory space. b). include at least one additional bit per data word. These characteristics of the memory component are standard features in the state of the art. In particular, such RAM components are already present in known manner in programmable component architectures. The memory component DPM thus has a memory capacity organized in groups of n + 1 bits, for storing data of n useful bits + 1 parity bit. The n useful bits correspond to the maximum length of the data exchanged with the application processes / devices.

According to the invention, the memory space of the DPM component is divided into a separate main space and a spare space. The main space is accessed by one of the ports, eg Port A, and the spare space is accessed by the other port, in the Port B example. This is equivalent to matching each Ad address, a unique pair of distinct addresses: Adl, corresponding to the main space accessible in the example by Port A, and Ad2, corresponding to the spare space accessible in the example by Port B.

The security method 100.0 includes a 100.1 write management process and a 100.2 read management process adapted to this redundancy and parity scheme of the memory space. In practice, this security process is typically implemented by the memory controller which, in a conventional and well-known manner, provides memory sequencing and manages requests for memory access of the processes or application devices in the programmable circuit. The write management process 100.1 is activated on receipt of a request for write access W of a data item D to an address memory Ad.

It comprises the loading of the data to be written: Din = D, and a parity calculation 100.10 on this dat Din to be written, to form a write data comprising the useful bits of the data Diri plus the parity bit P; a mapping 100.11 of the write address Ad, to the two corresponding addresses Adl of the main space and Ad2 of the spare space; then two simultaneous writes of this data Din + P: a write 100.12 in the main space via Port A, with activation of a corresponding write signal LoadA, and presentation of the data to write Din + P and the address Ad1; and a write 100.12 'in the spare space via Port B, with activation of a corresponding write signal LoadB, and presentation of the data to write Din + P and address Ad2. The read management process 100.2 is activated on receipt of a read access request R at an address Ad. It comprises a mapping 100.20 of the write address Ad to the two corresponding addresses Ad1 of the main space and Ad2 of the emergency area; then two simultaneous read accesses: a reading 100.21 in the main space via Port A, with activation of a corresponding reading signal LoadNA, and presentation of the address Ad1; and a 100.21 'read in the spare space via Port B, with activation of a corresponding read signal LoadNB, and presentation of the Ad2 address.

A corresponding read data, including parity, denoted by (D + P) A, and output on Port B, corresponding to parity (D + P) B, are read out on Port A. A parity check process 100.22 and 100.22 'is enabled on each of these two data (D + P) A and (D + P) B. This parity check process controls the transmission process 100.23 of the output data Dout on the external bus, in response to the read request. The output data Dout only includes the useful part of the data, that is to say (D) A or (D) B: the parity P is removed before transmission on the bus.

If the parity check process 100.22 on the datum (D + P) A provided by Port A is positive, ie the parity is good, the datum (D) A is considered correct. ErrA error signal at the output of this process is not activated. If this parity check is negative, the data (D) A is assumed to be corrupted, and the ErrA error signal is activated.

If the parity check process 100.22 'on the datum (D + P) B provided by Port B is positive, the datum (D) B is considered correct. ErrB error signal at the output of this process is not activated. If this parity check is negative, the data (D) B is assumed to be corrupted, and the ErrB error signal is activated.

The transmission process 100.23 thus comprises a management circuit 100.23a, of combinational logic type, for managing the channel selection of an Mxout output multiplexer, which receives, as inputs, the useful data (D) A supplied by PortA, and the payload (D) B provided by Port B. The output channel Mxout provides data Dout to the bus. This circuit also generates a disability exception signal XC, as described below. By choosing by pure convention, that the error signals are active in state 1 (meaning a negative parity check = incorrect parity), the combinational logic circuit 100.23a can for example be configured so that: - If the control of parity 100.22 associated with Port A is positive (ErrA = O), it activates the control signal Sel of the multiplexer Mxout to switch as output data Dout, the data (D) A supplied by Port A, in response to the request of reading R (Ad). 15 -If this control is negative, (ErrA = 1), it activates the control signal Sel of the multiplexer Mxout to switch as output data Dout, the data D (B) provided by Port B, in response to the reading request R (Ad). If the parity check 100.22 'associated with Port B is also negative (ErrB = 1), then the data Dout = (D) B output is assumed incorrect: the transmission process 100.23 is configured to activate a signal d XC exception, to report an error to the requesting external device or process. This error reflects the impossibility to choose and therefore to provide a data considered correct, because the two parity checks are defective (ErrA = ErrB = 1). The external process or device that requested the reading is thus informed of the doubt existing on the provided data. He will then be able to appropriately manage this disability exception. This management typically depends on the functionality involved. For example, if the external process or device must periodically provide another process with the result of a computation from the data requested for reading, it may in other examples: - perform the calculation using the data provided by default, but to signal doubt as to the result of this calculation made with this datum; - signal the doubt and wait for a refresh of the data supposed to be altered to resume the calculation, and / or possibly provide the last result of the calculation deemed good; -Restart the function after re-initialization.

The RAM data security method just described thus makes it possible, in a simple manner and by using functionalities of the memory components, to create a redundancy that makes it possible, in combination with a single bit of parity, to improve very effectively their reliability. It is indeed very unlikely that the two main and backup addresses of a piece of data in memory are "at the same time" affected by a logical hazard. This is what usually provides a correct data, that of the main space or the spare space. However, if both addresses are affected by a random event, the external user process of the memory is notified. Advantageously, the security method according to the invention further comprises a correction process 100.3. This correction process 100.3 is activated each time the result of the control of one of the two parity check processes 100.22 or 100.22 'is negative, while the other is positive, to trigger a rewriting of the data. supposedly altered with the data considered correct. In this way, and since it is unlikely that a hazard affects both data simultaneously, the reliability of the data is somehow maintained: as soon as a piece of data from the main space is found to be incorrect, it can be corrected by data from the backup space and vice versa. More precisely, with reference to FIG. 1, if the data (D) A supplied by Port A is detected incorrectly and the data (D) B supplied by Port B is detected correctly, then a write is sent via Port A at the address Ad1, with the data (D) B which is also in the example the data Dout, which can be written CorrA (Dout, Ad1). If the data (D) B provided by Port B is detected incorrectly and the data (D) A provided by Port A is detected correctly, then a write is sent via Port B to address Ad2, with the Given (D) To which is also in the example the data Dout, which can be written CorrB (Dout, Ad2). In practice, the correction method may force a write on the port concerned Port A, respectively Port B, by a specific signal CorrA CorrB, respectively, presenting the data Dout as input data Din = Dout. This can in practice be done in different ways, typically by the memory controller which arbitrates and serves the various requests, by any techniques known to those skilled in the art. Notably: ~ o-using dedicated memory cycles and systematically reserved in the sequencing of memory access. When a correction has to be made, the next first dedicated memory cycle is then allocated to this correction. using the first available memory cycle, ie which is not used, for functional reasons, which supposes that the user process or device uses only a part of the memory bandwidth considered. by forcing the availability of the next memory cycle by a known so-called cycle flight technique. In this case the activity of the process or user device of the data will be delayed by the duration of the stolen cycle. This can also be done by a masked cycle, using the double port access feature of the memory, to perform the correction directly by forcing a write on the port corresponding to the "erroneous" data, from the correct data provided. output by the other port. It is this implementation which is more particularly illustrated in FIG. 1: an activation signal Corr generated from correction signals CorrA and CorrB makes it possible to select the datum Dout as data Din to write: Din = Dout; and Writing 100.12 is forced by activating the LoadA or LoadB write signals on the corresponding Port A or PortB port by activating the correction signal CorrA or CorrB. A more detailed example of implementation will be explained in connection with FIG.

This correction mode by using the dual port feature allows read access during this correction cycle, on the port that provided the correct data: this port then becomes the default read port, but without the possibility of redundancy while the correction cycle is in progress. This nevertheless makes it possible to respond to requests for reading, and therefore not to slow down the processes too much. In this case, a buffer register will be provided for each port, to allow storage of the read address for which an error has been detected, so as to allow execution of the write correction at this stored address at the next cycle. , on the associated port, while a new address can be loaded in the buffer register associated with the other port, for a reading. A logic circuit will then be provided to adequately control the validation of the registers. In practice, it will be noted that the correction may not be decided: In the example more particularly illustrated in FIG. 1, the signal Corr will not be activated. Or the correction can be interrupted, to answer a priority write request. This corresponds to standard memory management aspects. The security process 100.0 according to the invention that has just been described is in practice managed by the memory controller of the programmable circuit. It allows read / write access management to a memory component, by which: - to each data item D written to a memory address Ad, a parity bit is calculated, and the useful bits and the parity bit are simultaneously stored at two separate memory addresses of the component, by write access to a port with a first address Ad1, and write access to the other port to a second address Ad2. - At each read request to a memory address Ad, the data contained at the two corresponding main and backup addresses are read, their parity is controlled, and the data output is a function of the result of this parity check. When data used in an external process or device is wider than the word structure in RAM, the data will be processed in word slices. Typically each slice will be stored in a different memory component, at the same logical address Ad on each component. The process will thus apply to each word of the data as illustrated in the block diagram of FIG. 2, which illustrates two memory components DPM1 and DPM2 forming a random access memory space used by two devices CP1 and CP2 of a programmable circuit . DATA data used by an external device CP1 is divided into two slices Din1, Din2 of n useful bits. Each slice is conventionally stored in a respective memory component DPM1, DPM2 (all the slices could be stored on the same component, but at different logical addresses, which is less easy to manage). According to the invention, each slice is stored with a parity bit P in the memory component concerned to a main memory address A and a spare memory address B. During read access, the parity check is performed on each pair of corresponding words: (Dini + P) A, (Din1 + P) B for the component DPM1, (Din2 + P) A, (Din2 + P) B for the component DPM2, and a corresponding output data Douti , Doubt is provided, depending on the parity check on each component. Thus, a method for securing data according to the invention facilitates the management of partial modifications of data larger than the memory structure of the programmable circuit: security, parity and redundancy is performed on each slice by the method of the invention.

FIG. 3 illustrates an exemplary memory architecture for a DPM random access memory component, making it possible to secure the data it contains according to the method of the invention, with a possible correction of a defective detected data item, by the redundant data considered correct, performed using the dual-port access capabilities of the memory, by controlling a correction write on the port concerned by internal means, while allowing external read access to the other port. In this example, the memory component has a data structure corresponding to a useful bit byte (D = 8 bits) and a parity bit (ie D + P = 9 bits). The sequencing of the component is controlled by a clock signal Ck. The notations of the processes and associated control signals used in FIG. 1 have been identically taken over, if necessary, to designate the means carrying out the corresponding process. The memory component comprises two ports Port A and Port B which according to the invention address two distinct spaces of the memory, a main space and a spare space. For each port, we have the corresponding address, data and control signals. Thus for 10 Port A: AdA the address signals, INA and OUTA respectively the data inputs and outputs, and RNVA the write / read signal. Similarly, for Port B: AdB the address signals are INB, OUTB and R / VVB. A separate address register is associated with each port, RA for Port A and RB for Port B. If there is to be a correction write on one of the two spaces following a read access, this register will allow keep the address of this reading on the port concerned by the correction, while the other register will be available to receive addresses for read access to the other port requested by an external user process of the memory. By convention, one notes: -Load: activation of a memory write, corresponding to a write access by an external user process of the memory. LoadN means that there is no write access by an external process. This signal can be used as priority information to invalidate the possible correction conditions when a write is required by the user process or device. -CorrA (respectively CorrB): activation of a memory write on Port A (respectively Port B) only, to make a correction; CorrNA (respectively CorrNB) meaning that there is no correction on Port A (respectively Port B). The architecture comprises different registers and logic circuits around the memory component DPM, to implement the security method.

An input buffer register Rin makes it possible to store a data item D written in input by an external process. A Rout output buffer register stores the data output Dout in response to a read access.

Means for providing the two separate paired addresses Ad1 and Ad2 corresponding to an Ad memory address accessed in read or write are provided. In the example, it consists for Ad1 in a simple addition of a "0", and for Ad2, in a simple addition of a "1" to the address Ad. Other simple conventions make it possible to define the two paired addresses corresponding to a memory address, for example by inverting one or more address bits. The multiplexer Mxin receives the output of these two registers and outputs the data Din to be written. It is followed by a circuit 100.10 of parity calculation P. The data Din + P is thus presented at the data input of each port, INA and INB. The multiplexer Mxout receives the data (D) A and (D) B delivered by each of the ports Port A, Port B, and outputs the data Dout to be presented on the bus (not shown) in response to an access request. in reading, based on parity checks on this data. This multiplexer is followed by the output buffer register. A combinatorial logic of the two parity check signals ErrA and ErrB is thus provided to select (Sel) appropriately according to a chosen convention, the data to be output, (D) A or (D) B, as a function of the parity check, and if necessary activate the XC invalidity exception signal. This logic is represented by the circuit 100.23a in FIG. 3. A combinational logic is also provided to activate a correction if necessary on one of the ports, with the output data provided by the other port: CorrA is activated if ErrA is negative and ErrB positive, and CorrB is activated in the opposite situation. This logic is represented by the circuit 100.3a in FIG. 3. As illustrated, the signals CorrA and CorrB can also be applied in the logic 100.23a for generating the signal XC, as explained hereinafter, to allow a reading on a port while the other port is in correction.

Each port has its own address register, RA for Port A and RB for Port B, which allows for the retention of the previous read address on the port concerned by the correction, while the other register is available. for read access. Typically, the register can load a new address Ad presented by an external user process of the memory, only if a write access is performed, represented by Load, or that there is no correction on the corresponding port, represented by CorrNA for RA and by CorrNB for RB. The desired operation is simplified as follows. The data Dout output by the multiplexer Mxout in response to a read cycle has been stored in the output buffer register Rout. If as a result of this reading, a correction is made, because of the parity check, the memory component will normally be unavailable for any "normal" write cycle: Load will not be in the active state, and LoadN will then allow correction CorrA or CorrB: the memorized data Dout is loaded by Mxin at the input of the memory component. If correction is to be performed on Port A (CorrA enabled), CorrNA is not enabled: the contents of the Port A RA address register remain unchanged, allowing correction to the previous read address, on write enable of the R1WA read / write control signal on Port A by the signal CorrA, with the data Din + P = Dout + P loaded into data inputs INA, INB, via Mxin (except for priority loading requested by the process or user device, LoadN then going to the active state for loaded data Din). If the correction is done on Port B, CorrNA is enabled, allowing a new Ad address to be sampled for a read operation only on Port A, on an active edge of the clock signal. In this case, the signals Load and CorrA are both inactive, which is equivalent to a read activation of the RNVA read / write control signal: the data read at the address presented at the AdA address input is outputted Dout of the multiplexer, this output Dout multiplexer Mxout then being forced by the signal salt to present the contents of the channel A and the error signal XC then being equal to ErrA, by a suitable combinational logic (100.23a). A correction write cycle on Port B or a read cycle on Port B during a correction on Port A is similarly obtained using the signals LoadN, CorrB, CorrNB, ErrB. Just swap the letters A and B in the previous paragraph. The set of logic activation signals is in practice generated by simple combinational logic circuits, based on the usual read-write signals in memory and the correction signals generated from the parity checks according to the invention. These are common aspects of control signal management, which do not present particular difficulties for those skilled in the art. The invention that has just been described makes it possible to improve the reliability of the RAM data by securing the data with respect to logical hazards, in particular, security obtained by implementing a redundancy scheme for writing and reading combined with a control. of parity. Advantageously, the correction of a piece of data detected incorrectly by the redundant data detected correctly makes it possible to reinforce this security. It is implemented in practice by simple means comprising buffer registers and logic circuits associated with each memory component forming the random access memory space of an electronic circuit. The practical implementation of which an example has been given uses well-known mechanisms and the usual possibilities of controlling dual port access memories and parity bit (s).

Claims (13)

1. Method for securing the data of a random access memory formed by at least one memory component, characterized in that each memory component is of the configurable type in dual port access on a first port (Port A) and a second port (Port B). ), and such that each memory address makes it possible to store n useful bits of data and at least one additional bit, characterized in that it comprises dividing the memory space of each memory component into a main space (A) and a backup space (B), assigning a different read and write access port to each space, in that each access to write data (D) to a memory address (Ad), it instantiates two simultaneous memory accesses to two distinct addresses (Ad1, Ad2), an access on each port, to write said datum (D) with a corresponding parity bit (P), and that at each read access to a memory address (Ad), it instantiates two memory access s impersonated at two corresponding separate addresses (Ad1, Ad2), an access on each port, to read a corresponding data item on each port, and provides at the output of reading (Dout) one or the other data read according to the result ( ErrA, ErrB) of a parity check on each of said read data. 2. Securing method according to claim 1, characterized in that it consists for each write operation of a datum (D) of n bits to a given memory address (Ad), i) to calculate the parity bit of said datum, to form a write data (Din + P) comprising the useful bits and the calculated parity bit and ii) to instantiate two simultaneous writes of said write data (Din + P) one on each port, at two distinct addresses (Ad1, Ad2) associated with said memory address (Ad). 30 3. security method according to claim 1 or 2, characterized in that it consists for each read operation of the data stored at a given memory address (Ad), i) to instantiate two simultaneous readings on each port, two separate addresses (Ad1, Ad2) associated with said memory address (Ad), ii) performing a check of the parity bit (100.22, 100.22 ') on the first datum ((D) A) read at the first address (Ad1) and on the second data item ((D) B) read at the second address (Ad2), for outputting (Dout) said first or second data as a function of the corresponding parity checks. 4. Securing method according to claim 3, characterized in that if the parity checks of said first data and said second data are incorrect, an exception signal (XC) is activated at the output. A security method according to claim 3 or 4, characterized in that if the parity checks of said first data and said second data are correct and incorrect, the correct detected data is used to correct the incorrectly detected data in a correction write cycle. 25 6. Method according to claim 5, characterized in that said correction write cycle is instantiated by cycle flight. The method of claim 5, characterized in that said correction write cycle is instantiated on the first available write cycle. The method of claim 5, characterized in that said correction write cycle is a masked cycle, activated on the port having provided the incorrect read data detected, read operations being allowed on the other port during said correction cycle. 10 9. The method of claim 8, characterized in that it uses storage means (RA, RB) of the memory address (Ad) read access or write associated with each of the ports of the memory. 10. Method according to any one of the preceding claims, characterized in that the memory component or components are 9-bit type, allowing the storage at each address of a byte of useful bits and an additional bit. 10 11. Method according to any one of the preceding claims, characterized in that a datum (Di ,,) to be stored in said random access memory space whose number of useful bits is greater than the number of bits that can be stored in memory. each address is stored in useful bit slices (Dini, Din2) with one parity bit per slice. 12.Architecture using a secure RAM formed by one or more memory components, characterized in that it comprises associated means (CM) for implementing a method according to any one of the preceding claims for each memory component. 13. Programmable circuit comprising RAM used in architecture according to claim 12.5