FR2993378A1 - Data processing system, has cache memory connected to programmable processor through communication bus, and coprocessor directly connected to cache memory such that programmable processor and coprocessor exchange data through cache memory - Google Patents

Abstract

The present invention relates to a data processing system comprising a programmable processor (P), a cache memory (C) associated with the programmable processor and a coprocessor (CP). According to the invention, the coprocessor is connected directly to the cache memory so that the processor and the coprocessor can exchange data via said cache memory.

Description

TECHNICAL FIELD The present invention relates to a data processing system with processor (s) and coprocessor (s).

STATE OF THE ART Integrated circuit chip data processing systems are an important part of the current market for electronic components and are expected to become their main component in the future.

A simplified generic scheme of such systems is illustrated in Figure 1. The architecture consists of one or more programmable processor (s), Po ... Pi, also called (s) CPU (s) for Central Processing Unit in the English terminology, one or more coprocessor (s) CP0 ... CPJ, also called hardware accelerators, specialized to perform one or more specific functions, one or more memory (s) MO .. Mk, typically RAM memories for Random Access Memory in the English literature, in which data are stored, these electronic components being connected to each other via a communication bus B or a network-on-a-chip. Such architectures are of a high level of design complexity and use if one wishes to obtain reliable and efficient products. When you want to create an application, different solutions are available to the designer: 1) an architecture called "any software": in this case, the architecture contains only processors P0 ... Pi and memories Mo .. Mk and the application is implemented in software and compiled on the system; the main advantage of this architecture is its flexibility because any modification of the system requires only a code modification and a recompilation thereof; its main disadvantage is that it has highly degraded performance (high computing time, high power consumption, ...); 2) an "all hardware" architecture: in this case, the architecture contains only CP0 ... CP coprocessors; and memories Mo ... Mk; compared to an all-software architecture, this architecture has excellent performance in terms of calculation time, occupied area and power consumption; on the other hand, this architecture is not flexible and is more complex than that called "any software" in terms of design; 3) a "software / hardware" architecture: in this case, the architecture contains processors, coprocessors and memories; this type of mixed architecture offers a good compromise between performance and flexibility; parts of the application that require flexibility but few performance are performed in software and are executed by the processors and parts of the application that require good time performance are performed by coprocessors; as can be seen in Figures 2 to 5, different configurations are possible; the coprocessor CP can be connected to the communication bus B (FIG. 2), or directly connected to the processor P (FIG. 3), or connected to the processor P via an auxiliary memory S of the ScratchPad type (FIG. this one (Fig.5); when the coprocessor is connected to the communication bus, which is, for example, the case of the BIC solution proposed by INTEL, the disadvantages are as follows: the coprocessor connected to the bus has a high access time which is a function of the controller of bus; - The communication bus is monopolized by the coprocessor when the latter accesses its data in the memory via the bus; the data used and provided by the coprocessor passes through the communication bus and thereby reduces the bandwidth; the rest of the system wanting to access the bus is then blocked; these disadvantages are however eliminated when the coprocessor is connected to the processor without passing through the communication bus (Figs 3 to 5); however, this solution often requires that the processor be shut down when the coprocessor is used; - the integration of the coprocessor via a ScratchPad memory assumes that the designer is able to permanently fix the maximum size required for this buffer memory but also and above all that the addresses associated with the data contained in this memory are defined at the design of the system and are permanently fixed; - finally, the addition of a ScratchPad memory implies a potentially significant additional cost in the final architecture. Description of the invention The object of the invention is to overcome all or some of the aforementioned drawbacks.

The object of the invention is in particular to propose a data processing system comprising in particular one or more associations of a coprocessor with a processor cache memory. According to the invention, the coprocessor or coprocessors of each association is (are) directly connected (s) to the cache (level 1 for example) of the association. Thus, the processor and the one or more coprocessors can communicate via said cache memory by dedicated links without using a shared communication bus if it is the level 1 cache. Also, the subject of the invention is a processing system. data system comprising at least one programmable processor, at least one coprocessor capable of exchanging data with the programmable processor (s) and a cache memory; the cache memory being connected directly to the at least one programmable processor (in the case of a level 1 cache) or connected via a communication bus to the at least one programmable processor in the case of a higher level cache (for example 2) for temporarily storing copies of data from the system, characterized in that said at least one coprocessor is directly connected to said cache memory so that said at least one processor and said at least one coprocessor can exchange data via said memory hidden.

Thus, the data exchanged between the coprocessor and the cache area with which it is associated does not pass through the communication bus of the system. The communication bus is no longer monopolized by the coprocessor when it works. Programmable processor means any type of processor whose whole or part of the application is defined by a program or software that can be modified and by coprocessor any type of wired processor whose application is not modifiable. In this context, a processor can read data in the cache area associated with it, which data will have been pretreated transparently by a coprocessor. According to another mode of operation, a processor can write data in the cache area associated with it, which data will be post processed transparently by a coprocessor. Typical application examples would be the use of a data encryption / decryption coprocessor or video format conversion (RGB to YUV) or data format. According to the invention, the cache memory normally used by the system processor not only serves as interface memory with the coprocessor but also serves as working memory for the coprocessor. In addition, no ScratchPad memory is required for this data exchange. This eliminates the additional cost of adding such a memory in the system. According to one embodiment, said at least one coprocessor is directly connected to a level 1 cache memory of said at least one programmable processor.

According to another embodiment, said at least one coprocessor is directly connected to a cache memory level higher than 1 of said at least one programmable processor. According to one embodiment, the cache memory of the processor comprises a total of N channels of L lines, k lines being allocated to the programmable processor and N * Lk lines being allocated to said at least one coprocessor, with N, L and k positive integers such that k <N * L. The number of lines allocated to the at least one coprocessor is not necessarily an integer multiple of the number of channels (i.e. (N * L-k) / N is not an integer value). Thus, the programmable processor and said at least one coprocessor can work simultaneously on different data without major degradation of the performance of the programmable processor. According to a particular embodiment, the number (N * Lk) / N is equal to a positive integer M. In this embodiment, the cache memory comprises a total of N channels, M channels being allocated to the programmable processor and NM = ( N * Lk) / N channels being allocated to said at least one coprocessor, with M and N positive integers such that M <N. According to one embodiment, the number of lines allocated to the at least one coprocessor is variable and may be a function of the processing executed by the coprocessor. According to one embodiment, the cache memory comprises an access controller (AC) for controlling the addressing of the N channels of the cache memory and activating the coprocessor when the address of the data supplied to the memory by the programmable processor is refers to N-M channels or N * Lk lines allocated to the coprocessor. Other advantages may still appear to those skilled in the art on reading the examples below, illustrated by the appended figures, given for illustrative purposes. BRIEF DESCRIPTION OF THE FIGURES FIG. 1 represents a simplified diagram of a first data processing system of the prior art comprising several programmable processors and several coprocessors; FIG. 2 represents a diagram of a second data processing system of the prior art comprising a programmable processor and a coprocessor; FIG. 3 represents a first variant of the diagram of FIG. 2; FIG. 4 represents a second variant of the diagram of FIG. 2; FIG. 5 represents a third variant of the diagram of FIG. 2; FIG. 6 represents a simplified diagram of a first data processing system according to the invention; FIG. 7 represents a simplified diagram of a second data processing system according to the invention; FIG. 8 represents a simplified diagram of a third data processing system according to the invention; and - Figures 9A and 9C schematically show a hierarchical cache organization. Detailed description of at least one embodiment With reference to FIG. 6, the data processing system according to the invention comprises a programmable processor P, a memory M, a coprocessor CP and a communication bus B. The processor programmable P and the memory M, for example of the RAM type, are connected to the communication bus B. A level C cache memory 1 is furthermore connected to the processor P for temporarily storing copies of data from the system. This cache memory has a read and write access time reduced compared to that of the M memories of the system. The cache memory is for example a SRAM type memory for Static Random Access Memory in English language. According to an important characteristic of the invention, the coprocessor CP is connected directly to the cache memory C of the processor. A first area of the cache memory is associated with the processor and a second area of the cache memory, separate from the first, is associated with the coprocessor. Thus, the coprocessor can access its data in the cache area associated with it without going through the communication bus B. The cache memory serves both interface memory and working memory for the processor P and the coprocessor CP. Thus, according to the invention, we reuse a memory already existing in the system, namely the cache memory of the processor P, instead of adding a specific memory for the coprocessor.

According to the embodiment illustrated in FIG. 6, the cache memory C comprises an access controller CA and N channels (or "ways" in English ") Vo to VN 4. Each channel designates a specific memory space of the cache memory. and includes for example L lines. (N * Lk) / N channels out of the N channels of the cache memory are allocated to the coprocessor and the remaining N - ((N * Lk) / N) channels are allocated to the coprocessor, with N integer positive and M <N. According to one particular embodiment, M is also a positive integer.Figure 7 represents a second embodiment of the system of the invention.In this embodiment, the cache memory comprises a cache memory C1. Level 1 directly connected to the processor P and a cache memory C2 of higher level, for example level 2, directly connected to the coprocessor CP In this embodiment, the processor P and the coprocessor CP can exchange data via C2 cache memory.

The system may also comprise several processors and several coprocessors, for example 2 processors P1, P2 and 3 coprocessors CP1, CP2 and CP3. In this case, the coprocessors CP1 and CP2 are for example respectively directly connected to the cache memories C1 and C2 of level 1 of the processors P1 and P2 and the coprocessor CP3 is connected to the cache C3 of level 2 shared by the processors P1 and P2 as shown in Figure 8. The operation of the system of the invention as shown in Figure 6 is described below. For this, we consider that the memory M contains encrypted data and that it is the coprocessor CP which is responsible for encrypting or decrypting for the processor P.

In the following, it is considered that the cache memory C is a set associative cache which contains 4 sets of each 4 channels as shown in Figures 9A to 9C. A cache line contains 4 memory words and a channel in a set contains exactly one line. Channel 0 is allocated to the coprocessor. Thus, when the data addresses correspond to one of the memory segments associated with the coprocessor, these data are placed in the O-channel. FIG. 9A shows the data in the central memory. In this example, the set 0 of the cache memory comprises the words DO, D1, D2 and D3, the set 1 comprises the words D4, D5, D6 and D7, the set 2 comprises the words D8, D9, D10. and D11 and set 3 comprises the words D12, D13, D14 and D15. Channel 0 of the cache memory includes the words DO to D15. FIG. 9B shows a schematic of the set-up cache, namely set 1, set 2, set 3, and set 4. Finally, FIG. 9C shows a schematic of the organized cache 2 5 by channels, namely channel 0, channel 1, channel 2 and channel 3. It is also considered that the coprocessor CP is a slave: it is therefore the access controller CA which is in charge of its configuration. and the management of his data. In the case of a master / slave coprocessor, the coprocessor CP itself accesses the data but is configured by the access controller (operating mode, address range, number of data to be processed, etc.).

As indicated above, some data contained in the memory M are encrypted. The coprocessor CP has the function of decrypting this data transparently for the processor P when the latter accesses it in reading. The coprocessor CP encrypts this data transparently for the processor P when the latter accesses it in writing. A result datum is stored at the same address as the operand data in the cache memory C. In a first example of operation, only the data item to be processed is necessary to obtain the result ie Dres = COPRO (Dop) where Dres is the result datum , Dop is the operand data and COPRO is the processing applied by the coprocessor CP on the data to be processed. The list of actions below describes a possible execution scenario in which the processor P first accesses read data DO encrypted and placed in memory and then accesses write data D8.

The processor P accesses in a second time in reading data D1 then accesses write data D9. Scenario 1 (the data DO, D1, D8 and D9 are associated with the coprocessor) 1. The processor P accesses the data DO in reading 2. The data DO is not present in the cache memory C. This causes a defect of the cache memory and the processor P is frozen. 3. The line of 4 words containing the data item DO is loaded in the cache memory C. The address controller of the access controller CA chooses the channel 0 to store this line in the cache memory because this data belongs to an associated segment to the CP coprocessor. 4. The access controller AC detects that the data DO is associated with the coprocessor CP. The AC access controller starts the coprocessor CP and provides it with the data DO to be processed according to the decryption mode (either directly or via a relative address i.e. an "offset"). 5. The coprocessor CP processes the data DO, ie decrypts it, and supplies the stored result to the same address as the data DO in the O-channel. 6. The coprocessor's writing of the new value of the data item DO is detected. by the CA access controller. 7. The decrypted data is supplied to the processor P ("cache hit"). 8. The processor P uses the data DO (decrypted) to perform a calculation and supply the data D8 as a result. 9. Data D8 is written to the cache memory. The access controller address decoder selects channel 0 to store this line in the cache memory because, in this case, this data belongs to a segment associated with the coprocessor CP. 10. The access controller AC detects that the data D8 is associated with the coprocessor CP. The access controller starts the coprocessor CP and provides it with the data D8 to be processed in the encryption mode (either directly or via a relative address i.e. an "offset"). 11. The coprocessor CP processes the data D8 ie the encrypt and provides the result which is stored at the same address as the data D8 in the channel O. 12. The coprocessor's writing of the new value of the data item D8 is detected by the access controller. The memory M is updated immediately or deferred according to the management policy write writes ("write through" or "write back"). 13. The processor P accesses the data D1 for reading; 14. The data D1 is present in the cache memory. Steps 4, 5, 6 and 7 apply identically to the data D1. Data D9 is the result data. Scenario 2 (only the data DO is processed by the processor to produce the data D 8. The data DO is associated with the coprocessor and the D8 is not associated with the coprocessor) The steps 9-14 are replaced by the steps 9.bis and 10.bis. 9. bis The data item D8 is written in the cache memory C in a different channel of the channel O. 10.a The writing of the new value of the data item D8 is detected by the access controller CA. The memory M is updated immediately or in a deferred manner according to the management policy of writes in the cache memory ("write trhough" or "write back").

In the case where, to decrypt the data DO, the coprocessor CP needs additional data such as the data D1 to D7 for example, the access controller CA is loaded (the coprocessor is still supposed to be slave here) to go read the data in the memory M and store them in the cache memory C before starting the coprocessor CP. Any other combination can be considered. In a particular operating case, data from the cache memory and decrypted by the coprocessor CP can directly be provided by the latter to the processor P without passing through the cache memory.

In a symmetrical manner, data processed by the processor P can be directly supplied by the latter to the coprocessor CP which will write the encrypted data directly into the cache memory. Thus, the data to be protected is always stored encrypted in the cache memory.

Of course, according to another embodiment, when the system comprises 1 processor and 2 coprocessors, M cache memory channels are allocated to the processor, M1 channels to coprocessor 1 and M2 channels to coprocessor 2, with N = M + M1 + M2. According to another embodiment, it is also possible to provide that M channels are allocated to the processor P, M1 channels are allocated to the coprocessor 1 and then M1 channels to the coprocessor 2 knowing that the coprocessor 1 operates exclusively before the coprocessor 2, which supposes a mechanism of hardware or software synchronization, with N = M + M1. M, M1 and M2 are not necessarily positive integers.

Claims (7)

CLAIMS1) Data processing system comprising at least one programmable processor (P, P1, P2), at least one coprocessor (CP; CP1, CP2, CP3) able to exchange data with said at least one programmable processor and a cache memory (C; C1, C2, C3) associated with said at least one programmable processor, which cache memory is connected directly or via a communication bus (B) to said at least one programmable processor for temporarily storing copies of data of the system, characterized in said at least one coprocessor is connected directly to said cache memory (C; C1, C2, C3) so that said at least one programmable processor and said at least one coprocessor are able to exchange data via said cache memory . 2) System according to claim 1, characterized in that said at least one coprocessor is connected directly to a level 1 cache memory of said at least one programmable processor. 3) System according to claim 1, characterized in that said at least one coprocessor is connected directly to a cache memory level higher than 1 of said at least one programmable processor. 4) System according to claim 1 or 2, characterized in that the cache memory comprises a total of N channels (Vo-VN_i) of L lines, k lines being allocated to the programmable processor and the N * Lk remaining lines being allocated to said at least a coprocessor, with N, L and k positive integers such that k <N * L.30 5) System according to claim 3, characterized in that the number (N * I-k) / N is a positive integer. 6) System according to claim 4 or 5, characterized in that the number of rows is variable and is a function of the processing performed by the coprocessor. 7) System according to any one of claims 4 to 6, characterized in that the cache memory comprises an access controller (CA) for controlling the addressing of the N channels of the cache memory and activate the coprocessor when the address data supplied to the memory by the programmable processor refers to the NL * k lines allocated to the coprocessor.