FR2980915A1 - Method for manufacturing e.g. metal-oxide semiconductor transistors in zones of semiconductor substrate of complementary metal-oxide semiconductor integrated circuit, involves filling openings with conducting material - Google Patents

Abstract

The method involves forming sacrificial grids on a surface of a semiconductor substrate (41), where the grids are surrounded by an encapsulation layer (48). Sacrificial grids from a set of zones are removed to form a set of openings. A first conductive material layer (51) is conformally deposited. Sacrificial grids from another set of zones are removed to form another set of openings. An insulating material layer (52) and a second conducting material layer (53) are successively and conformally deposited. The openings are filled with a conducting material (55) i.e. aluminum.

Description

FIELD OF THE INVENTION The present invention relates to a method for manufacturing capacitors in integrated circuits comprising MOS transistors.

DISCUSSION OF THE PRIOR ART In an integrated circuit, it is desired to produce active components and passive components such as capacitors. For example, capabilities are designated by the acronym MIM (Metal Insulator Metal). MIM capabilities are typically fabricated over MOS transistors in interconnect levels. FIG. 1 is a cross-sectional and perspective view of MIM capacitors formed in interconnect levels above an integrated circuit chip 1. The overall set of a number of interconnection levels These interconnection levels 3 are covered by a particular interconnection level 5, consisting of a metal layer, for example copper. Conventionally, the metal layer 5 is covered with a barrier layer 7, for example silicon nitride, and an insulating layer 9, for example silicon oxide. In the set of layers 7 and 9 are formed apertures in which B11219 - 11-GR3-0552EN01 2 are successively deposited, in a conformal manner, a first conductive layer 11, for example made of titanium nitride (TiN), a layer or a set of insulating layers 13 and a second conductive layer 15, for example also in TiN. It is conventional to fill the openings with a conductive material 17, for example copper. In Figure 1, there is shown the structure after planarization, that is to say that all the portions of the materials 11, 13, 15 and 17 which had been deposited on the upper surface of the layer 9 have been eliminated. Capacitors consisting of a first electrode corresponding to the conductive layer 11, a second electrode corresponding to the conductive layer 15, and a dielectric corresponding to the layer or set of insulating layers 13 have thus been formed.

For each capacitor, for example, a contact is made on the lower part of the conductive layer 11, where it rests on the metal layer 5. The other contact can be taken by a via to the conductive material 17 or by any other way. If the openings are in the form of grooves, as shown, and they meet at a distance, we can take a common contact on a wider pad corresponding to an intersection of all these grooves. Such MIM capabilities have a high density.

Indeed, each capacity is a capacity in three dimensions (3D) comprising on the one hand a horizontal part and on the other hand two vertical parts, with a form factor that can be relatively high. However, of course, the realization of such capabilities requires a number of specific steps compared to the steps commonly used to manufacture the interconnection levels of an integrated circuit. There is therefore a need for a capability manufacturing process compatible with the manufacture of CMOS integrated circuits, and requiring only a reduced number of additional steps compared to the commonly used steps. for the manufacture of an integrated circuit. SUMMARY Thus, it is sought to manufacture an integrated circuit 5 comprising on the one hand MOS transistors and on the other hand capacitances, by a method requiring only a reduced number of additional manufacturing steps compared to the steps commonly used to the manufacture of MOS transistors, and especially, not requiring the provision of additional critical mask. Thus, an embodiment of the present invention provides a method for manufacturing capacitors and MOS transistors in first and second regions of the same semiconductor substrate, comprising the steps of: a) forming sacrificial grids on the surface of the substrate , the sacrificial grids being surrounded by an encapsulation layer; b) removing the sacrificial grids from the first zones so as to form first openings; c) conformingly depositing a layer of a first conductive material and removing it elsewhere than in and around the first openings; d) removing the sacrificial grids from the second zones so as to form second openings; and e) sequentially depositing a layer of at least one insulating material and a layer of at least one second conductive material 25, and filling the first and second openings with a third conductive material. According to one embodiment of the present invention, this method further comprises, in step a), a source and drain regions implantation step. According to one embodiment of the present invention, this method further comprises, in step c), the following steps: conformally depositing a layer of a first insulating material on the layer of the first conductive material (51) ; and removing the layer of the first insulating material elsewhere than in and around the first apertures. According to one embodiment of the present invention, the sacrificial grids are grids insulated by a gate insulator. According to an embodiment of the present invention, in step b), the gate insulator of the sacrificial grids of the first zones is eliminated, and in step d), the gate insulator of the sacrificial grids of the second zones is eliminated. According to an embodiment of the present invention, in step d), the gate insulator of the sacrificial grids of the second zones is preserved. According to one embodiment of the present invention, the sacrificial gates are of polycrystalline silicon and the gate insulator of the sacrificial gates is of silicon oxide. According to one embodiment of the present invention, the layer of the first conductive material deposited in step c) is made of titanium nitride and the layer of the insulating material deposited in step e) comprises a material with a high dielectric permittivity. According to one embodiment of the present invention, the thickness of the layer of the first conductive material deposited in step c) is between 0.5 and 2 nm. According to one embodiment of the present invention, the third conductive material is aluminum. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects, features, and advantages will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying figures, in which: FIG. previously, is a sectional and perspective view illustrating a conventional embodiment of MIM capabilities; FIG. 2 is a sectional view illustrating various types of MOS transistors commonly used in a CMOS integrated circuit; and Figs. 3A-3G are sectional views illustrating successive steps of manufacturing a MOS transistor and capacitance. As is usual in the representation of integrated circuits, the various figures are not drawn to scale.

DETAILED DESCRIPTION FIG. 2 is a sectional view illustrating a set of MOS transistors formed on a semiconductor substrate 21. In the example shown, each of the N-channel MOS transistors is formed in a P-well 23 and each of the channel MOS transistors P is formed in a box N 24. In practice, there may be a single type of box, the other MOS transistors being formed in the substrate. The caissons are generally joined, as has been shown. It will also be possible to provide specific implantations of the channel regions before forming the gates of the transistors. A first CMOS assembly comprises MOS transistors 26 and 27, respectively N-channel and P-channel, and a second CMOS assembly comprises MOS transistors 28 and 29, respectively N-channel and P-channel. The transistors are separated from each other. others by isolated regions penetrating the surface of the semiconductor. Each of the transistors comprises a gate insulator 32 and a gate conductor 34. Transistors 26 and 27 have been designated with a gate insulator 32 consisting of a stack of two insulating regions 31 and 33, and for the transistors 28 and 29 a gate insulator 32 consisting of a single insulating region. This makes it possible to differentiate CMOS assemblies that can withstand higher or lower supply voltages. In the case where the gate insulator consists of a stack of two insulating regions, it is conventional that one of the insulating regions is a material with a high dielectric permittivity. Furthermore, each of the grids is surrounded by spacers 36. In addition, there are shown source regions 5 and drain 37 formed in the boxes after making grids and spacers. This is only an example of realization. Source and drain regions of somewhat more complex structure are generally provided, with a first portion of the source and drain regions being formed prior to forming the spacers and a second portion after formation of the spacers. FIGS. 3A to 3G show successive stages of simultaneous formation of a MOS transistor and of a capacitance. In the left-hand part of each of the figures are illustrated successive steps of forming a MOS transistor and in the right-hand part successive steps of forming a capacitance. The MOS transistor described in connection with these figures corresponds to a transistor selected from the transistors illustrated in FIG. 2, it being understood that the other transistors 20 may be formed parallel in a conventional manner. FIG. 3A is a sectional view illustrating a semiconductor substrate 41, for example a silicon substrate, in the upper surface of which identical or different boxes 42 have been formed. A sacrificial gate structure was formed above each of the caissons. The areas of the substrate in which the sacrificial grids are formed are separated from each other by isolated regions 43. Each sacrificial gate structure comprises a gate insulator 44, for example silicon oxide, and a gate conductor 45, for example polycrystalline silicon. Each grid structure is surrounded by two spacers 46. Source and drain regions 47 are formed in the caissons 42 after making the sacrificial grids and the spacers. An encapsulation layer 48 surrounds the sacrificial grids and the spacers.

For example, the encapsulation layer 48 has been formed by depositing a layer of an insulating material, for example silicon oxide, having a thickness at least equal to that of the electrodes. sacrificial grids, then planarization of this layer at the top of the gate conductors 45. In the step illustrated in Figure 3B, the sacrificial gate has been eliminated in the right part of the figure. For this, we used a mask, not shown, whose positioning is not critical. Indeed, the mask must only overflow with respect to the sacrificial gate that it is desired to eliminate and stop at any point at the level of the encapsulation layer 48 separating this gate adjacent grids. In the step illustrated in FIG. 3C, a thin layer of conductive material 51, for example a metal or a conductive compound such as TiN, has been conformally deposited. As will be seen below, this conductive material is intended to form a first electrode of a capacitor. In the step illustrated in FIG. 3D, the layer 51 and the sacrificial gate are eliminated in the left part of the figure, for example using a mask complementary to the mask previously used to eliminate the right sacrificial gate. It will also be possible to use the same mask as the mask previously used to eliminate the sacrificial grid on the right, but then a photosensitive resin of different polarity will be used. In the step illustrated in FIG. 3E, a layer or a set of insulating layers 52 and a layer or a set of conductive layers 53 are successively deposited successively. The insulating layer 52 corresponds to the dielectric of the capacitor formed in FIG. right portion of the figure and the conductive layer 53 to the second electrode of the capacitor. The insulating layer 52 also constitutes the gate insulator of the MOS transistor being formed in the left portion of the figure, and the conductive layer 53 a gate conductor of the MOS transistor. A particular type of MOS transistor will have been chosen from among the different types of MOS transistors available such as those illustrated in FIG. 2, so that the gate insulator of this MOS transistor is satisfactory to form the dielectric of a desired characteristic capacitor. . Thus, this capacitor is formed without involving any additional step with respect to the steps necessary to manufacture the MOS transistor, other than the non-critical masking steps described in connection with FIGS. 3B and 3D. In addition, to obtain a high form factor of the capacitance, it is possible to start from a MOS transistor having the minimum allowed gate length for the considered technological node. This gives high density capabilities. Figures 3F and 3G illustrate subsequent steps conventionally used in the manufacture of MOS transistors. As illustrated in FIG. 3F, the remaining openings 20 after the step illustrated in FIG. 3E have been filled with a conductive material 55, for example aluminum. The post-planarization structure is also shown, i.e., all portions of the materials 51, 52, 53 and 55 that had deposited on the upper surface of the encapsulation layer 48 have been removed. In FIG. 3G, there are shown vias 56, 57 made to make contact on the two electrodes of the capacitor formed in the right part of the figure. Contact with the first internal electrode is provided by the source or drain region 47 and the well 42, which in this case are of the same conductivity type. The contact towards the second electrode is provided by the conductive material 55. These vias 56 and 57 are made in a not shown interconnection structure, at the same time as access vias to the gate and the drain and / or to B11219 - 11-GR3-0552EN01 9 the source of the MOS transistor formed in the left part of the figure. Of course, as described with reference to FIG. 1, in place of the access niases 56 and 57, contacts may be made to larger pads connecting groove extensions in which the capacitors are formed. The present invention is capable of numerous variants, optimizations and modifications.

First of all, to optimize manufacturing, all the capacitors will preferably be grouped together in the same area of the integrated circuit structure so as to simplify the mask whose use has been described in relation to FIGS. 3B and 3D.

In addition, it may be provided, in the step illustrated in Figure 3C, to deposit a first insulating layer above the conductive layer 51, before the deposition of the insulating layer 52 in the step illustrated in Figure 3E. The material of this first insulating layer and its thickness will be chosen so as to optimize the characteristics of the capacitance. The insulating layer 52 may also be removed on the capacity side by reusing, in the step illustrated in FIG. 3E and before the deposition of the conductive layer 53, the mask used in the step illustrated in FIG. 3B. Thus, it will be possible for the capacitance to have a dielectric of a different type and thickness than that of the gate insulator of the MOS transistor, for example ZrO2 for the capacitance and Hf02 for the MOS transistor. In the case where the insulating layer 52 is kept on the capacitance side, a dielectric consisting of a ZrO 2 region covered with HfO 2 is obtained for the capacitance. At the step illustrated in FIG. 3D, the gate conductor 45 and gate insulator 44 are eliminated on the side where it is desired to form a MOS transistor. An alternative is to remove only the gate conductor 45 and retain the gate insulator 44. The gate insulator 44 will then serve as the first gate insulator region, a second insulator layer 52. As shown in FIG. being then deposited in the step illustrated in FIG. 3E to form a second gate insulator region of the MOS transistor and the dielectric of the capacitance.

An embodiment has been described in which operations are performed in parallel in a region in which a capacitance is to be formed and in a region in which it is desired to form a particular MOS transistor. It will of course be possible to combine, where capacity is achieved, steps for manufacturing various types of MOS transistors, that is to say choosing a layer or set of insulating layers 52 and a layer or set of conductive layers. 53 corresponding to different types of MOS transistors. Finally, there is described an embodiment on solid substrate. The present invention may be adapted to structures made on a thin layer of silicon formed on an insulator. As an example of orders of magnitude, it will be possible to provide: a gate length of 20 nm MOS transistors; a thickness of the sacrificial gate structures of 50 nm; a thickness of the layer 51 of between 0.5 and 2 nm, for example of the order of 1 nm; for transistors 28 and 29, a thickness of the single gate insulator region 32 of the order of 3 nm; and for the transistors 26 and 27, a thickness of the gate insulator region 31 of the order of 3 nm and a thickness of the gate insulator region 33 of the order of 3 nm. The following materials may also be provided by way of example for the various elements of the structure: - for the conductive layer 53, titanium nitride or a set of layers comprising a layer of lantane and a layer of titanium nitride; for the insulating layer 52, a material with a high hafnium dielectric permittivity such as HfO 2 or HfSiO 2; for the single region of gate insulator 32 of transistors 28 and 29, a material with a high dielectric permittivity, generally resting on a very thin layer of silicon oxide serving as an interface layer between the substrate, generally in silicon , and the material with high dielectric permittivity; for gate insulator region 31 of transistors 26 and 27, silicon oxide; and for the gate insulator region 33 of the transistors 26 and 27, a material with a high dielectric permittivity. Various embodiments with various variants have been described above. It will be appreciated that those skilled in the art may combine various elements of these various embodiments and variants without demonstrating inventive step.

Claims (10)

REVENDICATIONS1. A method of manufacturing capacitors and MOS transistors in first and second regions of the same semiconductor substrate (41), comprising the steps of: a) forming sacrificial grids (45) at the surface 5 of the substrate, the sacrificial grids being surrounded by an encapsulation layer (48); b) removing the sacrificial grids from the first zones so as to form first openings; c) conformingly depositing a layer of a first conductive material (51) and removing it elsewhere than in and around the first openings; d) removing the sacrificial grids from the second zones so as to form second openings; and e) successively and conformally depositing a layer of at least one insulating material (52) and a layer of at least one second conductive material (53), and filling the first and second openings with a third material driver (55). The method of claim 1, further comprising, in step a), a step of implanting source and drain regions (47). The method of claim 1 or 2, further comprising, in step c), the steps of: conformingly depositing a layer of a first insulating material on the layer of the first conductive material (51); and removing the layer of the first insulating material elsewhere than in and around the first openings. 30 The method of any one of claims 1 to 3, wherein the sacrificial grids (45) are grids insulated by a gate insulator (44). The method according to claim 4, wherein in step b) the gate insulator (44) of the sacrificial grids (45) of the first zones is eliminated, and wherein, at step d), the gate insulator (44) of the sacrificial grids (45) of the second zones is eliminated. The method of claim 4, wherein in step d), the gate insulator (44) of the sacrificial grids (45) of the second zones is retained. A method according to any one of claims 4 to 6, wherein the sacrificial grids (45) are of polycrystalline silicon, and wherein the gate insulator (44) of the sacrificial grids (45) is of silicon oxide . 8. A method according to any one of claims 1 to 7, wherein the layer of the first conductive material (51) deposited in step c) is made of titanium nitride, and wherein the layer of insulating material (52) deposited in step e) comprises a material with a high dielectric permittivity. 9. A method according to any one of claims 1 to 8, wherein the thickness of the layer of the first conductive material (51) deposited in step c) is between 0.5 and 2 nm. 20 The method of any one of claims 1 to 9, wherein the third conductive material (55) is aluminum.