FR2702862A1 - An apparatus and method for processing image data capable of processing high speed image data. - Google Patents

Abstract

Techniques for compressing decompressing image data are disclosed. An image compression / decompression apparatus according to an international standard comprises a control unit (2), a pixel processing unit (3) for discrete cosine transformation and quantization, an interval buffer memory. image (51), a motion prediction unit (41), a pixel data bus (PB) and a code bus (CB). An assembly control processor which is incorporated in the control unit performs pipeline control for image compression / decompression, thereby achieving high operation. Application to the transmission of television images.

Description

APPARATUS AND METHOD FOR PROCESSING DATA

  IMAGE CAPABLE OF PROCESSING IMAGE DATA

HIGH SPEED

  The present invention generally relates to an image data processing apparatus and an image processing method. More particularly, it relates to an image data processing apparatus and method by means of which compression and / or decompression of image data

with a high speed.

  International standards for the compression and decompression of image data have been prepared by the International Organization for Standardization, hereinafter referred to as "ISO";

  International Telegraph and Telephone Consultative Committee

  "CCITT", still known today as I Tu-T, and International Electrical Committee, hereinafter referred to as "IEC". Among the international standards, the JPEG standard was prepared by the Joint Photographic Expert Group of ISO and CCITT, and

  it defines compression and decompression algorithms

  On the other hand, an MPEG standard is being prepared by the Moving Picture Expert Group of ISO and IEC, and it defines compression and decompression algorithms for animated color images. an H 261 standard is currently being prepared by the CCITT, and it defines a compression and decompression algorithm suitable for videoconferencing and video telephony. Figure 69 is a block diagram showing main processes in an image compression algorithm which is recommended by the international standard Referring to Fig. 69, it is noted that an image compression process basically comprises a predictive coding, a

  orthogonal transformation and variable length coding

  As can be seen in FIG. 69, each of the JPEG, MPEG and H 261 standards includes, in image compression processing, a discrete cosine transform (also called "DCT"), a quantization and a quantization.

Huffman coding.

  The JPEG specification for processing a color still image includes, as a base system, adaptive discrete cosine transformation, quantization, pulse-code modulation (PCM) and Huffman coding. for example, the JPEG specification includes, as a developed system, an adaptive discrete cosine transform, a hierarchical coding, a coding

  arithmetic and adaptive Huffman coding.

  The MPEG specification for mobile image accumulation includes inter-frame motion / prediction compensation, discus cosine transformation, Huffman La quantization and coding.

  H 261 specification for videophone and videoconfu-

  includes inter-frame motion / prediction compensation, discrete cosine transformation,

  Quantization and Huffman coding.

  A complex integrated circuit for image compression in accordance with the aforementioned international standard has

  been developed and it is for example briefly described

  in an article entitled "LSI for Image Processing", in Journal of the Institute of Television Engineers of Japan, Vol 46, No. 3, pages 253-260, 1992 It is noted that the present invention is generally applicable to a compression apparatus image data, an image data decompression apparatus and an image data processor for compression and / or image decompression according to the international standards described above. Figure 70 is a block diagram of a

  conventional image compression / decompression apparatus.

  Referring to FIG. 70, it will be noted that the image compression / decompression device comprises a digital signal processor (DSP) 900 for image data processing, a memory image data 907, a code data memory 908, a display memory 909 and a working memory 910 The digital signal processor 900 is connected to the memories 907 to 910 by

  via an internal bus 940.

  Figure 71 is a block diagram of the process

  Digital signal processor 900 shown in FIG. 70. Referring to FIG. 71, digital signal processor 900 includes instruction memory 901, program control unit 902, data memory 903, and digital signal processor 900. , a data processing unit 904 and an external interface 905 A bus of

  system 941 connects the parpro-

  902, the data memory 903, the processing unit of

  data 904 and the external interface 905 During the

  tion, a registered instruction code (or program

  m) in the instruction memory 901 is read and is applied to the program control unit 902 The program control unit 902 decodes the instruction code applied and produces various control signals Under the effect control signals from the program control unit 902, the processing unit of

  data 904 receives external data through

  The result of the operation is stored in the data memory 903 or it is transmitted via the external interface 905 of the external interface 905 and the data memory 903. this way, a process is performed in the digital signal processor 900 according to the instruction code which is stored in the memory

901.

  An image data compression operation will be described with reference to Figs. 70 and it is assumed here that the image data to be compressed is stored in an image data memory 907.

  first, the image data that has been recorded

  stored in the image data memory 907 are trans-

  to the data memory 903 in the digital signal processor 900 The format of the image data stored in the data memory 903 is converted

  by the data processing unit 904 In the conversion

  sion, subsampled data of difference signal

  color, or data in RGB format, for example

  The converted data is temporarily stored in the data memory 903. The digital signal processor 900 transfers to the image data memory 907 the converted data that is present in the memory of the data memory.

903 data.

  Then, the digital signal processor 900 determines an image compression mode using the data recorded in the image data memory 907. With regard to the image compression modes, there is known a mode of compression of the image. frame, an intra-frame compression mode, etc. In the inter-frame compression mode, a processing such as a prediction (or a

  detection) sometimes becomes necessary.

  Evaluation data for determining the compression mode and evaluation data for the motion detection are obtained by performing for example summation of absolute values of image data differences. When such an operation is performed, the processor digital signal 900 transfers the data recorded in the image data memory 907 to the data memory 903, in a manner similar to that of the format conversion, and the data processing unit 904 processes the recorded data. in the

data memory 903.

  Based on the evaluation data that is

  obtained by the operation mentioned above, the process

  digital signal 900 determines the compression mode.

  by referring to table data for the purpose of determining

  mode that are stored in the memory of

  910 and / or by performing a comparison operation

because of the evaluation data.

  After determining the compression mode, the digital signal processor 900 performs a coding

  by transforming the image data that is recorded

  The transformation coding is represented for example by the discrete cosine transformation. The digital signal processor 900 transfers to the internal memory 903 the data which is stored in the image data memory 907. , and then the data processing unit 904 performs the discrete cosine transformation. The processed data is stored in the

data memory 903.

  In addition, the 900 digital signal processor

  performs variable length coding (or coding

  pique) Variable length coding is known as code conversion using eg Huffman code 900 digital signal processor fulfills

  a variable length coding of the data that is recorded

  stored in the data memory 903, with reference to a code conversion table which is stored in the working memory 910 After code conversion, the processed data is transferred from the data memory 903 to the code data memory 908 and they are

recorded in the latter.

  Image data processing for the com-

  image pressure is accomplished as described above.

  above, and the image data processing for the decom-

  image pressure is also performed in a similar manner More specifically, the data to be decompressed is first applied to the data memory 903

  in the digital signal processor 900, and processors

  image decompression is performed by the unit

  data processing 904 on the recorded data.

  As described above, in the apparatus of

  compression / decompression of a conventional image, a compres-

  image data are decompressed and decompressed.

  killed by a 900 digital signal processor having a

  only data processing unit 904, and consequently

  Data processing takes a lot of time.

  Further, because the digital signal processor 900 has only one input / output port (i.e. the external interface 905) for the data, the data transfer can not be performed efficiently in the image compression / decompression device

  a large amount of image data.

  An object of the present invention is to provide an apparatus and method for processing image data

  suitable for fast treatment.

  Another object of the present invention is to provide an apparatus and method for image data processing by which

  image data compression with high speed.

  A further object of the present invention is to provide an apparatus and method for image data processing by which

  decompression of image data with high speed.

  Another additional object of the present invention is to provide a treatment apparatus for

  image data that can perform predefined processing

  terminated for image data compression and / or image data decompression and image transfer.

  image data in parallel, with a high speed.

  Another additional object of the present invention is to provide an image data processing apparatus capable of separately controlling access to

several memory units.

  Another additional object of the present invention is to provide an image data processing apparatus which can simplify the determination concerning the selection of a variable length code or

a fixed length code.

  Another additional object of the present invention is to provide an image data processing apparatus which can simplify the determination in the selection of range and data data.

level, or decoded data.

  Another additional object of the present invention is to provide an image data processing apparatus which can access, in a short time,

  pixel data of a desired area on the screen.

  Another additional object of the present invention is to provide an image data processing method in which the number of images can be reduced.

pixel data transfers.

  In accordance with one aspect of the present invention,

  the image data processing apparatus comprises a control processor for controlling pipeline processing of a set of processes for image data compression and / or image data decompression, and a processor image to complete a process

  predetermined among the set of processes, under the

  of a control signal which is applied by the

control processor.

  With the structure described above, the process

  The controller controls pipeline processing of a set of predetermined processes for image data compression and / or image data decompression so that image data can be processed.

with a high speed.

  An image data processing apparatus according to another aspect of the present invention

  includes a control processor which is intended to com-

  order parallel execution of predetermined processes

  for image data compression and / or decompression

  image data and data transfer

  image, and a set of control circuits for executing

  each of them individually controlling the execution of the predetermined processes and the transfer of image data, under the control of a control signal which

  is applied by the command processor.

  With the structure described above, the process

  The controller controls the execution in parallel of a set of predetermined processes for image data compression and / or image data decompression and image data transfer under the effect of a signal. from the control processor, a set of execution control circuits individually control the execution of these operations, so that image data can be processed with a

high speed.

  The image data processing apparatus according to yet another aspect of the present invention is capable of accessing a first memory unit in which table data for the conversion is stored at a second memory unit in a second memory unit. which are recorded data to be processed, a third memory unit in which image data is recorded for display and a fourth memory unit in which converted image data is recorded, and includes a first circuit access for accessing the first memory unit, a second access circuit for accessing the second memory unit, a third access circuit for accessing the third memory unit, a fourth access circuit for accessing the second memory unit, a second access circuit for accessing the second memory unit, a third access circuit for accessing the third memory unit, a fourth access circuit for accessing to the fourth memory unit, and an access control circuit for individually controlling the start of access to the first to

fourth access circuits.

  In the structure described above, the access control circuit individually controls the start of access to the first to fourth access circuits. Therefore, it is possible to access individually the

  first to fourth memory units, the data used

  Data processing can be transferred with high speed and therefore image data can be processed at a high speed. The image data processing apparatus according to yet another aspect of the present invention

  includes a memory unit which is intended to record

  a variable length code corresponding to the combination

  range data and level data,

  corresponding code length data and an indica-

  fixed-length code processor; a read circuit for reading the variable length code, its code length data and the fixed length code processing indicator corresponding to applied range data and applied level data; a fixed length coding circuit for encoding according to a predetermined rule on the applied range data and the applied level data, and producing a corresponding fixed length code; a selection circuit operating under the control of the fixed-length code processing indicator which is output from the read circuit, so as to select the variable length code or the fixed length code; and one

  code coupling circuit for coupling succes-

  the codes issued by the selection circuit.

  In the structure described above, the selection circuit selects either the variable length code or the fixed length code, in dependence on the fixed length code processing indicator which is

  provided by the reading circuit, so that a determination

  nation in accordance with the program can be significantly simplified, and that image data can be

  processed with a high speed.

  The image data processing apparatus according to another further aspect of the present invention comprises a memory unit which is intended to record range data and level data.

  corresponding to the variable length code, and a

  code driver with fixed length; an extraction circuit for

  extract a variable length code from a long code stream

  eur comprenant gu comprenant comprenant--comprenant--comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant comprenant

  coupled; a reading circuit for reading, corresponding to

  dance with the variable length code that is retrieved by the extraction circuit, the range data and the corresponding level data, and the fixed-length code processing indicator, in the memory unit; a fixed-length decoding circuit for decoding the fixed-length code which is extracted by the

  extraction circuit, in accordance with a pre-determined rule

  mined, to provide corresponding decoded data; and a selection circuit for selecting, in response to the fixed length indicator which is output from the read circuit, the range data and the

  level data, or code data.

  In the structure described above, the selection circuit selects either the range data and the level data, or the decoded data, depending on the fixed-length processing indicator that is provided by the read circuit, so that the

  determination in accordance with the program may be

  simplified, and that image data can be

  be treated with a high speed.

  The image data processing apparatus according to another further aspect of the present invention comprises N (n> 2) memory cell arrays for storing image data to define pixels on the screen, the N memory cell arrays providing N pixel data, with each data recorded in a corresponding one of the N memory cell arrays, under the effect of the application of a line address signal and a signal column address, the N pixel data defining a set of pixels arranged in the vertical direction on the screen, and the apparatus further comprising an address signal generating circuit for serially transmitting signals of column address to define pixel data

  concerning the pixels arranged in the horizontal direction

  screen, under the effect of a serial clock signal.

  In the structure described above, N pixel data read in N memory cell arrays under the control of a line address signal and a column address signal define a set of pixels. arranged in the vertical direction on the screen Since the address signal generation circuit sends column address signals in series under the effect of a serial clock signal, it can be accessed in a short time. duration to pixel data of a desired area on the screen so we can process data

image with high speed.

  The image data processing apparatus according to another further aspect of the present invention comprises N (nt 2) memory cell arrays for storing pixel data for defining pixels on the screen, the N gratings. memory cells providing N pixel data, with each data recorded in a corresponding one of the N memory cell arrays, under the effect of the application of a line address signal and a signal of column address, the N pixel data defining a set of pixels arranged in the horizontal direction on the screen, and the apparatus further comprises an address signal generating circuit for serially transmitting column for defining pixel data relating to pixels that are arranged in the vertical direction on the screen, dependent on a

serial clock signal.

  In the structure described above, N pixel data read in N memory cell arrays in response to a line address signal

  and a column address signal, define a set of

  The fact that the address signal generation circuit sends column address signals in series under the effect of a serial clock signal can be accessed by the plurality of pixels arranged in the horizontal direction on the screen. in a short time to pixel data of a desired area on the screen so we can process data

image with high speed.

  The image data processing apparatus according to another further aspect of the invention comprises a first pixel data memory unit which is for recording pixel data to be compressed; a first pixel data bus for transferring pixel data recorded in the first pixel data memory unit; a pixel processor that receives pixel data transferred by the first pixel data bus and extracts data

  reference for motion prediction, by using

  sation of the transferred pixel data, and having first and second data ports for providing the reference data for the motion prediction; a second pixel data bus for transferring the motion prediction reference data output from the second pixel processor data port; a second pixel data memory unit for storing motion prediction reference data that is transferred by the second data bus; a motion prediction unit for performing a motion prediction using the reference data for the prediction which is recorded in the second pixel data memory unit and which is transferred by the second pixel data bus, to generate a motion vector; and a pipeline control processor for controlling the pipeline processing of the first and second data buses

  the pixel processor, the pixel processor and the prediction unit.

movement.

  In the structure described above, the process

  pixel generator provides the reference data for motion prediction via the first and second data ports, these data are respectively recorded in the first and second pixel data memory units, the reference data for the prediction of movement that are recorded in the

  second pixel data memory unit are trans-

  referenced to the motion prediction unit by the second pixel data bus, and the motion prediction unit performs a motion prediction and

generates a motion vector.

  As a result, data can be effectively transferred with the amount of data effectively divided, the amount of data transferred by a path can be reduced so that the practical speed of data transfer can be improved, and image data can be improved. can be treated with a

high speed.

  The image data processing method according to another further aspect of the present invention encodes a set of macroblock data defining pixels which form an image plane, by pipeline processing, and this method comprises the steps which comprises performing a discrete cosine transform and quantizing the macroblock data to generate a pixel code, performing variable length coding on the pixel code that is generated in

  the aforementioned step, to generate a variable length code.

  ble, and to couple the variable length code generated in the previous step, to produce a variable length code stream. With the above method, all of the processing of the macroblock data set can be performed in accordance with the present invention. a pipeline mode, so compression of the image data can be performed

with a high speed.

  The image data processing method according to another further aspect of the present invention decodes a variable length code train, comprising a set of variable length codes defining pixels forming an image plane, by pipeline processing and said method comprises the steps of extracting the variable length code from the variable length code stream, performing variable length decoding on the variable length code that is retrieved by the preceding step, to generate a code of pixel, and performing inverse quantization and inverse discrete cosine transform of the pixel code that is generated in the preceding step, to generate macroblock data defining pixels that

form the image plane.

  With the above method, a variable length code train comprising a set of variable length codes can be decoded by pipeline processing, and hence image data can be

  be decompressed with a high speed. The method of processing image data according to another mode of

  Yet another embodiment of the present invention is for projecting first pixel data into a memory unit that records a set of these first pixel data, defining pixels of the screen, and this method comprises a first step of determining a set of second data mutually adjacent pixels, bidimensionally, and included in a rectangular area, among the first pixel data, a second step of applying an address of the memory unit to the second pixel data, considering the second pixel data as a single data element, and a third step of transferring the second data from or to the memory unit using the address of the second pixel data. the image data processing method mentioned above, a set of second pixel data two-dimensionally adjacent, and included in a rectangular area, are considered as a single data item and are transferred by applying a single address, thereby reducing the number of transfers to transfer the first pixel data to the area It is therefore possible to process the image data with a

high speed.

  The image data processing method according to another further embodiment of the invention is for projecting the first and second color difference pixel data into a memory unit which records these first and second data of the color difference pixel. color difference pixel, mutually linked, for defining pixels on a screen, and this method comprises a first step of alternately projecting in the memory unit transfer units of the first and second color difference pixel data; and a second step of transferring the first and second color difference pixel data to or from the memory unit while working on the transfer unit. Therefore, in the image data processing method described above, first and second correlated color difference pixel data are alternately projected while working on the transfer unit, and first and second difference data. In this way, by generating a single address, it is possible to transfer first and second color difference pixel data of a given area. As a result, it is possible to process

  image data with high speed.

  The image data processing method according to another further aspect of the present invention is for projecting first and second color difference pixel data into a memory unit which records these first and second pixel data of the present invention. color difference related to each other, for defining pixels on a screen, and this method comprises a first step of projecting into the memory unit third color difference pixel data containing the same number of first and second second color difference pixel data, as a single block of data, and a second step of transferring the third color difference pixel data, as a single data block, to from the memory unit

or towards it.

  Therefore, in the image data processing method described above, the third color difference pixel data, including the same

  number of the first and second pixel data of different

  The color difference pixel is projected into the memory unit as a single block of data, and the third color difference pixel data is transferred as a single data block. by generating a single address, the first and second color difference pixel data of a given area can be transferred. Thus, image data can be processed with a high speed. These and other objects, features, aspects and advantages of the present invention will become apparent

  further from the description of embodiments

  presented below The rest of the description refers to

in the accompanying drawings in which:

  Figure 1 is a block diagram of a

  compression / decompression image showing a

  first embodiment of the present invention.

  Figure 2 is a block diagram showing

  treatments for image compression in the

  compression / decompression image which is

shown in Figure 1.

  Fig. 3 is a block diagram showing treatments for image decompression by the appa-

  compression / decompression image which is

shown in Figure 1.

  FIG. 4 is a block diagram of a device

  compression / decompression image, showing a

  second embodiment of the present invention.

  Figure 5 is a block diagram of a

  compression / decompression image showing a

  third embodiment of the present invention.

  Figure 6 is a block diagram of a

  compression / decompression image showing a

  fourth embodiment of the present invention.

  Figure 7 is a block diagram of a

  compression / decompression image showing a

  fifth embodiment of the present invention.

  FIG. 8 is a block diagram of an apparatus

  compression / decompression image showing a

  sixth embodiment of the present invention.

  Figure 9 is a block diagram showing a

example of a control unit.

  Figure 10 is a block diagram showing

  another example of the control unit.

  Fig. 11 is a time chart showing a pipeline processing which is performed under the control of an ensemble control processor which is shown

in Figure 9.

  Figure 12 shows parallel operations in a single period T 1 O which is represented on the

figure 11.

  Fig. 13 is a block diagram of an overall control processor which is shown in FIG.

Figure 9.

  Fig. 14 is a block diagram of a motion prediction control unit which is

shown in Figure 9.

  Fig. 15 is a block diagram of an image format conversion unit which is shown

in Figure 9.

  Fig. 16 is a block diagram of an image data transfer control unit which is

shown in Figure 9.

  Fig. 17 is a block diagram of an instruction transfer unit which is represented on

Figure 9.

  Figure 18 is a block diagram showing

  an example of a pixel processing unit.

  Fig. 19 is a detailed block diagram of the pixel processing unit which is represented on

Figure 18.

  Figure 20 is a block diagram showing

  another example of the pixel processing unit.

Fig. 21 is a detailed block diagram of the pixel processing unit which is shown on

Figure 20.

  Fig. 22 is a flowchart showing a coding operation (intra-interval picture prediction) in the pixel processing unit which is shown

in figure-19.

  Fig. 23 is a flow chart showing a decoding operation (intra-interval image prediction) in the pixel processing unit which is shown

in Figure 19.

  Figure 24 is a flowchart of an operation

  coding scheme (bidirectional prediction) in the pixel processing unit shown in FIG.

19.

  Fig. 25 is a flowchart of a decoding operation (bidirectional prediction) in the unit of

  pixel processing which is shown in Figure 19.

  Fig. 26 is a time chart showing pipeline processing for coding in the unit of

  pixel processing which is shown in Figure 19.

  Fig. 27 is a time chart showing pipeline processing in intra-slot image prediction in the pixel processing unit which is

shown in Figure 19.

  Fig. 28 is a time chart showing a pipeline processing in the unidirectional processing in the pixel processing unit which is shown

in Figure 19.

  Fig. 29 is a time chart showing a pipeline processing in the bidirectional prediction in the pixel processing unit which is shown

in Figure 19.

  Fig. 30 is a block diagram showing a first system structure for a processing

variable length.

  Fig. 31 is a flowchart of the variable length coding in the first system structure

  which is shown in FIG.

  Fig. 32 is a flowchart of variable length decoding in the first system structure

  which is shown in FIG.

  Fig. 33 shows a data memory structure of a table memory for length coding

  variable which is shown in Figure 30.

  Fig. 34 shows a data memory structure of a table memory for decoding at length

  variable which is shown in Figure 30.

  Fig. 35 is a flowchart showing a process for generating a code train to

variable length.

  Figure 36 is a block diagram showing

  a first example of a variable length processor.

  Fig. 37 is a block diagram showing a second example of the variable length processor. Figure 38 is a block diagram showing

  a third example of the variable length processor.

  Fig. 39 is a block diagram showing a second system structure for processing at

variable length.

  Figure 40 is a block diagram of the process

  variable length which is shown in Figure 39.

  Figure 41 is a synoptic diagram of the general

  addressed in FIG. 40.

  Fig. 42 is a flowchart of the variable length coding in the address generator which is

shown in Figure 41.

  Fig. 43 is a flowchart of variable length decoding in the address generator which is

shown in Figure 41.

  Fig. 44 is a block diagram of the code train generation / separation circuit at length

  variable which is shown in Figure 40.

  Fig. 45 is a flowchart of the variable length coding in the variable length code train generation / separation circuit which is shown

in figure 44.

  Fig. 46 is a variable length decoding flowchart in the variable length code train generation / separation circuit which is shown

in figure 44.

  Figure 47 is a block diagram of a

  external interface circuit of FIG. 40.

  Fig. 48 is a flowchart of the variable length coding in the external interface circuit which

is shown in Figure 47.

  Fig. 49 is a flowchart of variable length decoding in the external interface circuit which is shown in Fig. 47. Fig. 50 is a group variable length code table which is used in the processor to

  variable length which is shown in Figure 39.

  Figure 51 shows the format of the data recorded

  stored in the table memory for coding at

  variable length which is shown in Figure 39.

  Figure 52 shows the data format to code

  in variable length coding.

  Fig. 53 shows the basic structure of the memory cell array in a frame buffer. Figure 54 is a block diagram of a

frame buffer.

  Fig. 55 shows a frame structure of the frame buffer employing dynamic random access memories. Figure 56 shows a pixel layout

  showing the relationship between recorded data

  in the frame buffer which is shown

  in Figure 55 and the pixels on the screen.

  Fig. 57 shows a pixel arrangement showing the relationship between data stored in the frame buffer which is

  shown in Figure 60 and the pixels on the screen.

  Fig. 58 shows a pixel arrangement that illustrates addressing by a dynamic random access memory controller which is shown in Fig. 55. Fig. 59 is a time chart showing a read operation of a frame buffer under control of the RAM control unit

  dynamic which is shown in Figure 55.

  Fig. 60 shows a system structure of a frame buffer employing synchronous dynamic random access memories. Fig. 61 is a timing diagram showing a read operation of the synchronous dynamic random access memory. Fig. 62 shows an exemplary operation of the address generator which is shown in Fig. 60. Fig. 64 is a timing diagram showing another example of operation of the address generator.

  which is shown in Figure 60.

  Figure 65 is a timing diagram showing yet another example of generator operation

  address that is shown in Figure 60.

  Figure 66 is a block diagram of the general

  addressed in Figure 60.

  Figure 67 shows the correspondence address-

  page and brings up the relationship between pages and row and column addresses that are provided by the

  address generator shown in Figure 66.

  Figure 68 shows the page-pixel mapping and shows the relationship between pages that are

  shown in Fig. 67 and the pixels on the screen.

  Fig. 69 is a block diagram showing main processing according to an image compression algorithm which is recommended by a standard

International.

  Figure 70 is a block diagram of a

  image compression / decompression image classic.

  Figure 71 is a block diagram of the process

  digital signal which is shown in the figure

70.

  Fig. 72 is an illustration of a first method of projecting into a frame buffer of

pixel data on the screen.

  Fig. 73 is a first illustration of the transfer of a data area comprising 8 pixels in the horizontal direction and 8 pixels in the vertical direction. Fig. 74 is a second illustration showing the transfer of a data area comprising 8 pixels in the horizontal direction and 8 pixels in the

vertical direction.

  Fig. 75 is a third illustration showing the transfer of a data area comprising 8 pixels in the horizontal direction and 8 pixels in the

vertical direction.

  Fig. 76 is a fourth illustration of the transfer of a data area comprising 8 pixels in the horizontal direction and 8 pixels in the vertical direction. Fig. 77 is an illustration of a second method of projecting into the frame buffer of

pixel data on the screen.

  Figure 78 shows a first method of projecting into a raw frame buffer

  and second color difference pixel data.

  Figure 79 shows a second method of projection.

  in a frame buffer of raw and

  second color difference pixel data.

  Fig. 80 shows a third method of projecting into a raw frame buffer

  and second color difference pixel data.

  Figure 81 shows a fourth method of projecting into a raw frame buffer

  and second color difference pixel data.

  Figure 82 shows how the process works.

  set command, at the time of coding with

bidirectional prediction.

  Fig. 83 is a block diagram of an image compression / decompression apparatus showing a seventh embodiment of the present invention. Fig. 84 is a block diagram of an image compression / decompression apparatus showing a

  eighth embodiment of the present invention.

  Fig. 85 is a block diagram of an image compression / decompression apparatus showing a

  ninth embodiment of the present invention.

  Fig. 86 is a block diagram of an image compression / decompression apparatus showing a

  tenth embodiment of the present invention.

  Fig. 87 is a block diagram of an image compression / decompression apparatus showing a

  eleventh embodiment of the present invention.

  Fig. 88 is a block diagram of an image compression / decompression apparatus showing a

  twelfth embodiment of the present invention.

  Fig. 89 is a block diagram of an image compression / decompression apparatus showing a

  thirteenth embodiment of the present invention.

  Fig. 90 is a block diagram of an image compression / decompression apparatus showing a

  fourteenth embodiment of the present invention.

  Fig. 91 is a block diagram of an image compression / decompression apparatus showing a

  fifteenth embodiment of the present invention.

  Figure 92 is a block diagram showing

  an additional example of the control unit.

  Fig. 93 is a block diagram showing a further example of the pixel processing unit. Fig. 94 is a first detailed block diagram of the pixel processing unit which is

shown in Figure 93.

  Fig. 95 is a second detailed block diagram of the pixel processing unit shown in Fig. 18. Described below are image compression / decompression devices (or a compression / decompression system of image) showing first to

  fifteenth embodiments of the present invention.

  We will first describe the general or system structure of these embodiments and describe

  then the internal structures of the system.

  1 General structure (1) First embodiment

  Figure 1 is a block diagram of a

  FIG. 1 shows that the image compression / decompression apparatus 101 comprises an interface circuit (I / I). F) host 1 for the exchange of information with a host computer 93; a control unit 2 comprising two processors (not shown); a pixel processing unit 3 for discrete cosine transformation and quantization; a Lon preict unit

  (or detection) of movement 41, a buffer memory of

  picture frame 51 for recording image data to be processed; a buffer memory 6 for storing code data; a working memory 7 for storing table data needed for various conversions; and

  an input / output memory 81 for recording data.

  image from a television camera 91 and / or

  to provide recorded image data to a device

  viewing eye (cathode ray tube) 92.

  An HB host bus has a bus width of 24 bits (which is designated in the figure as "24 b") and is intended for data transfer between each of the elements comprising the host interface circuit 1 , the control unit 2, the pixel processing unit 3, the buffer memory 6 and the working memory 7 The pixel data bus PB has a 32-bit bus width (32 b) and is embedded therein for the transfer of data between each of the elements comprising the control unit 2, the pixel processing unit 3, the motion prediction unit 41 and the image slot buffer 571 Unbus of code data CB has a 16-bit bus width (16b) and is embedded for the transfer of code data between the control unit 2, the pixel processing unit 3 and the buffer memory 6 An input bus / IOB output has a bus width of 24 bits (24 b) and is embedded for data transfer between control unit 2 and the

input / output memory 81.

  The host interface circuit 1 comprises a logic circuit which is constituted by a programmable logic device such as a high-level logic circuit.

  general level of (discrete) integration, a

  PLD-type or FPGA-type programmable gate array The image buffer Jle d 1 image 51 is incorporated

  essentially to temporarily save data

  images to be compressed and image data to

  With regard to the image memory buffer 51, a memory having a large capacity such as

  Static RAM (or SRAM), a dynamic random access memory

  (or DRAM), a synchronous dynamic random access memory and a

  dynamic random access memory provided for the function of

memory.

  The buffer memory 6 is incorporated for recording

  temporarily store range / level data and bit stream data that are obtained by the image coding Buffer 6 is constituted by a first-in, first-out (FIFO) memory. RAM

  dynamic or a static RAM.

  The working memory 7 is incorporated to record discrete cosine transform table / discrete cosine transformation data.

  inverse, quantization / quantization table data

  reverse cation, Huffman table data for a

  variable-length treatment, a program (micropro-

  gram) for the processing in the control unit 2 and the pixel processing unit 3, data for

  initialization, etc. The working memory 7 is constituted

  killed by static memories.

  The input / output memory 81 is incorporated to record image data for the television camera 91 and / or the display apparatus 92 The input / output memory 81 is constituted by memories

vivid video.

  The control unit 2 comprises a microprocessor

  seur (not shown) for the overall control and a processor (not shown) for processing at length

  variable The processor for the overall set command

  mandates pipeline processing of the cosine transformation dicrete, quantization and length coding

  variable for image compression, as well as

  variable-length decoding pipeline, the quan-

  inverse fication and discrete cosine transformation

  reverse for image decompression.

  The pixel processing unit 13 performs pixel processing such as discrete cosine transformation and image compression quantization, and

  it performs pixel processing such as the quantization

  reverse cation and discrete cosine transformation

reverse in image decompression.

  The motion prediction unit 41 performs motion detection processing such as unidirectional image inter-interval predictions.

and bidirectional.

  Figure 2 is a diagram showing

  image compression apparatus in the image compression / decompression apparatus 101 shown in Fig. 1 Fig. 2 shows by way of example a

  encoding method that is specified in the MPEG standard.

  Referring to Fig. 2, it is noted that ID image data to be compressed is applied via a subtracter 921 and a switch 922 to a discrete cosine transform processor 923 After the cosine transformation discreet, a

  quantization is performed by a quantizer 924.

  The quantized data is applied to a variable length encoder 925 and is variable length coded, and the encoded data is provided as compressed VD image data via a 926 D 'buffer. on the other hand, the quantized data is also applied to an inverse quantizer and an inverse discrete cosine transform processor, and inverse quantization and

  inverse discrete cosine transform for prediction

  The output data of the discrete cosine transform processor are

  inverse are applied to an adder 929.

  The ID image data is also applied to a motion predictor 930, and the predicted data is applied to the adder 929.

  the output of the adder 929 are applied to the subtraction

  921 and the motion predictor 930 through

  931 Through the switching action of a

  In the case of switches 922 and 931, image compression is performed taking motion prediction into consideration. Fig. 3 is a diagram showing an image decompression processing which is performed by the image compression / decompression apparatus 101 shown in Fig. 1 Referring to Fig. 3, it is noted that Variable length VD are applied to a variable length decoder 912 via a buffer 911 After variable length decoding, the code data is applied to a reverse quantizer 913 and they are subjected to inverse quantization After inverse quantization, a transformation

  in discrete inverse cosine is performed by a process

  In this embodiment, the adder 915 performs an addition of the output data, including the data that has been subjected to the motion prediction, and provides data.

uncompressed image ID.

  The treatments that are shown in Figures 2 and 3 are specified in the main

  MPEG standard These compression and decompression

  image pressure are actually accomplished under a

  pipeline processing control, which will be described later

  later, in the compression / decompression device

  101 which is shown in Figure 1.

(2) Second embodiment

  FIG. 4 is a block diagram of a device

  Image compression / decompression element 102 showing a second embodiment of the present invention In comparison with the image compression / decompression apparatus 101 shown in FIG. 1, the motion prediction unit 41 is removed in the image compression / decompression apparatus 102 which is shown

  in Figure 4 More precisely, in the embodiment of

  tion shown in Figure 4, it is possible to

  kill motion picture decoding as well as still picture encoding and decoding Motion picture decoding is an inverse process of coding It does not, however, include motion prediction and, instead, motion decoding is added and this decoding generates a predicted image, under the effect of receiving a motion vector. (3) Third embodiment

  Figure 5 is a block diagram of a

  FIG. 5 illustrates a third embodiment of the present invention. Referring to FIG. 5, it is noted that in comparison with the image compression / decompression apparatus 101 which is shown in FIG. FIG. 1, the image compression / decompression device 103 comprises an input memory /

  output 82 which is connected to the pixel data bus PB.

  More specifically, the input / output memory 82 is connected to the control unit 2 via the pixel data bus PB Therefore, in the control unit 2, the input / output memory 82 and the picture slot buffer 51 use a common address space, and therefore the number of input / output interface circuits can be reduced (input port /

output) of the control unit 2.

  (4) Fourth embodiment

  Figure 6 is a block diagram of a

  FIG. 6 shows a fourth embodiment of the present invention. Referring to FIG. 6, in comparison with the first image compression / decompression apparatus 101, the compression apparatus / image decompression 104

  includes a bidirectional motion prediction unit

  42 which can perform in parallel (or simultaneously

  In particular, the directional motion prediction unit 42 comprises a motion prediction unit 43 for the forward motion prediction, and a motion prediction unit 44. for motion prediction in the backward direction Motion prediction units

  43 and 44 are connected to the pixel data bus PB.

  Because the prediction of movement in

  forward and reverse directions can be performed in parallel

  or simultaneously, using two prediction units

  43 and 44, the bidirectional motion prediction can be effectively accomplished in one

short duration.

  (5) Fifth embodiment

  Figure 7 is a block diagram of a

  compression / decompression image 105 showing a

  fifth embodiment of the present invention.

  In comparison with the image compression / decompression apparatus 101 shown in FIG. 1, the image compression / decompression apparatus 105 includes a motion prediction unit 45 capable of simultaneously performing a motion prediction. bidirectional, and two image interval buffers 52 and 53, each of which is connected to the pixel data bus PB The motion prediction unit can make a prediction in both directions

  simultaneously, and therefore a bidirectional prediction

  can be accomplished over a period of time

  for prediction in the forward direction or in direc-

  rearward motion The motion prediction unit 45

  has two input / output ports, one of which is connected

  to the PB pixel data bus and the other is connected to

  the image gap buffer 53 through the

  1 of the LB local bus 1 One of the two image slot buffers 52 and 53 is used as a memory

  of image intervajle for the moving prediction in direc-

  forward, while the other image slot buffer is used as image slot memory for forward motion prediction. Reference image data is transferred.

  to the PD pixel data bus and the LB local bus 1.

  Model image data and motion vector data are transferred from the prediction unit of

  movement 45 to the control unit 2 through

* Diary of a second local bus LB 2.

(6) Sixth embodiment

  FIG. 8 is a block diagram of an apparatus

  In comparison with the image compression / decompression apparatus 101 shown in FIG. 1, the compression / decompression apparatus 106 exhibits a sixth embodiment of the present invention. Fig. 106 includes a motion prediction unit 46 having two input / output ports. The first input / output port of the motion prediction unit 46 is connected to the pixel data bus PB and its second port of input / output is connected to the control unit 2 via a local bus LB 3 The motion prediction unit 46 directly applies to the control unit 2, via the local bus LB 3, the data Motion vector data obtained by motion prediction Because the motion vector data is 8-bit signals, the LB 3 local bus has an 8-bit bus width. of movement are dir applied to the control unit 2 by

  the local bus LB 3, it is possible to

  to improve parallel processing in the compres-

  image decompression / decompression 106, and as a result image compression / decompression can be performed more than

  effectively at a higher speed.

  The image compression / decompression apparatuses 102 to 106 which are shown in FIGS. 4 to 8 basically accomplish the same operation as the image compression / decompression apparatus 101 which is shown in FIG. from second to sixth embodiments, the image compression / decompression shown in Figs. 2 and 3 is accomplished under pipeline processing control. Therefore, it is noted that image compression / decompression can be accomplished.

  effectively with a high speed will be described later

  in detail the pipeline treatment, referring to

Figures 11 and 12.

  Specifically, hereinafter, the image data transfer in the image coding will be described with respect to the data transfer by the data bus.

  PB pixel data in the compression / decompression apparatus

  image pressure 106 of the sixth embodiment, and the image data transfer volume for processing

  of image data of a macro-block.

  It is assumed that the image data to be encoded has already been recorded in the image interval buffer 51 The data transfer volume is calculated with the assumption that the image format is 4: 2: 0 , the motion detection range is +16 pixels, and the structure is an image gap structure. Each unit performs image data input and output operations in connection with the bus of

  PB pixel data under control of the communication unit

  command 2 The control unit 2 defines the conditions

  time of operation of each unit.

  First, original image data is transferred from the control unit 2 to the image interval buffer 51 via the pixel data bus PB. data

  image to transfer is 384 pixels.

  Next, the reference image luminance component (reproduced image), in the search scope

  of movement, is transferred from the buffer memory

  image value 51 to the motion prediction unit 46 via the pixel data bus PB for the motion prediction At this time, the image data volume to be transferred is 768 pixels for an interval of reference image Therefore, in the

  bidirectional prediction, it is necessary to trans-

  to make 1536 pixels, that is to say two shots of images.

  Then, the luminance component of the image to be encoded is transferred from the image interval buffer 51 to the control unit 2 via

  of the PB pixel data bus for the motion prediction

  Then, the luminance component is transferred from the control unit 2 to the motion prediction unit 46 by the local bus LB 3.

  of image data that is transferred is 256 pixels.

  The motion prediction is accomplished and the inter-frame prediction must be performed in accordance with the determined encoding mode using the results, and the data of the predicted image (reproduced image) is transferred from the image intervae buffer. 51 to the pixel processing unit 3 via the pixel data bus PB for encoding At this time, the image data volume to be transferred is 451 pixels for a predicted image plane Therefore , for the bidirectional prediction, we must transfer 902 pixels

for two shots of images.

  Then, the image data to be encoded is trans-

  from the image interval buffer 51 to the pixel processing unit 3, via the pixel data bus PB.

  image data that is transferred is 384 pixels.

  After the end of the coding, the data of the image to be reproduced, with respect to the Xifza coding interval and the unidirectional prediction image, are transferred from the pixel processing unit 3 to the image interval buffer 51 via the pixel data bus PB At this time, the image data volume that is transferred is 384 pixels.

  The volume of data transfer described above

  it becomes maximal at the time of bidirectional prediction

  in which all data transfers are performed, with the exception of the transfer of data

  image to reproduce, and this volume is 3462 pixels.

  Under these conditions, if the motion search range is enlarged in order to improve the quality of the image, the image data transfer volume of the luminance component of the reference image in for example, if the motion search range is enlarged to + 32 pixels, it becomes necessary to transfer 1280 pixels at the time of the unidirectional prediction and 2560 pixels at the time of

bidirectional prediction.

  With regard to digital image data,

  There are different data formats depending on the amount of color difference component data of the image data. Thus, there are 4: 4: 4 formats in which the amount of data from the original image is preserved, a 4: 2: 2 format in which the color difference component is reduced to half, and a 4: 2: 0 format in which the component of

  difference in color is reduced to one quarter

  when changing the image format to be manipulated, there is an increase in the image data transfer volume, with the exception of the image data transfer volume related to the motion prediction For example , if the 4: 4: 4 format is used, the volume of data that is manipulated in the original image data transfer, the image data transfer to be encoded to the pixel processing unit, and the transfer of image data to be reproduced, will be 768 pixels, while for the transfer of prediction image data, it will transfer almost twice as many pixels, that is to say that 867 pixels must be transferred for each

  image plane of the predicted reference image.

  As described above, if the number of pixels of the image to be processed is increased, as in the case of a high definition image, the time required for the processing of a macroblock increases. system is fixed, the volume of data transfer that can be processed in one cycle of the system clock is limited by the hardware performance, when the data transfer volume for the processing of a macro-block increases Therefore, to transfer the data described above, the number of cycles of

the system clock increases.

  As described above, if the volume of trans-

  data is very high and increases further when

  Because more pixels are needed and image quality is better, the data transfer process limits the processing speed of the entire device if pipeline processing is performed.

  using as unit the coding corresponding to a macro-

  block, since the number of cycles required for the

  data transfer to perform the coding is superior

  the number of cycles required for the coding operation itself A description will be given in the following

  compression / decompression of images which improves the

  cacity of the data transfer and in which the overall processing speed is not limited by the speed of

data transfer.

  (7) Seventh Embodiment Fig. 83 is a block diagram of an image compression / decompression apparatus 107 in accordance with Figs.

  to a seventh embodiment of the present invention

  In Fig. 83, parts corresponding to those of the sixth embodiment shown in Fig. 8 are designated by the same reference characters.

  and their description is not repeated.

  Referring to Fig. 83, it is noted that the pixel data bus PB has a data width of 32 bits and is incorporated for data transfer between the control unit 23, the

  pixels 33 and the frame interval buffer 51.

  The local data bus LDB has a data width of 32 bits and is embedded for data transfer between the pixel processing unit 33, the motion prediction unit 47 and the local memory 56.

  Local memory 56 is incorporated to record

  temporarily store a luminance component of the reproduced image data which is used for the motion prediction and is transferred from the pixel processing unit 33 A memory having a larger capacity such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (RAM) and dynamic random access memory (RAM)

cache function.

  A microprocessor (not shown) for the overall control, which is incorporated in the control unit 23, controls the transfer of image data

  between the control unit 23, the buffer memory of

  the image processing unit 51 and the pixel processing unit 33, and controls the image data transfer between the pixel processing unit 23, the image processing unit 23,

  movement 47 and local memory 56.

  The pixel processing unit 33 has a new data output port P 2 for the image data, in addition to the data input / output port P1 which is connected to the pixel data bus PB The unit motion prediction 47 and the newly incorporated local memory 56 are connected to the data output port P 2 via the local data bus

  LDB The data output port P 2 of the processing unit

  pixel 33, the motion prediction unit 47 and

  local memory 56 are controlled by the communication unit

  mande 23, and they complete the data transfer

  image via the local data bus 61.

  The control unit 23 also controls the conditions

of each transfer.

  The image data that is manipulated by the local data bus LDB is the reference data for motion prediction that is extracted from image data transferred by the pixel processing unit 33 from the buffer memory. picture interval 51, via the pixel data bus

  PB (data comprising at least one information representative

  of luminance data among the image data, hereinafter luminance component). The reference data is transferred from the data input / output port P1 to the image interval buffer 51 through the pixel data bus

  PB and they are saved in this memory.

  A dedicated local bus LB 4 having a width of 8

  bits, is incorporated between the motion prediction unit

  47 and the control unit 23 The image data that is the subject of the motion detection is transferred from the control unit 23 to the motion prediction unit 47 The motion vector data which indicates the result of the motion detection is transferred from the motion prediction unit 47 to the control unit 23 The control unit 23, the image interval buffer 51 and the pixel processing unit 33, which are connected to the pixel data bus PB, generate a predicted image and encode the predicted image, based on the motion vector data. The pixel processing unit 33 provides image data.

coded to the CB code bus.

  With reference to FIG. 83, the image data transfer in the image coding and the image data transfer volume in the processing of a macro-block of image data will be described. the image data to be encoded have already been recorded in the

  image interval buffer 51, and the component

  the luminance of the reference image (image reproduced

  duite), necessary for motion detection, has already been saved in local memory 56 The transfer volume is calculated assuming that the image format is 4: 2: 0, that the image detection range is of +16 pixels and the structure is an image interval structure. First, original image data is transferred from the control unit 23 to

  the image slot buffer 51 through the

  of the PB pixel data bus At this time, the amount of image data that is transferred is 384

pixels.

  Then, for the motion prediction, the luminance component of the image to which the motion prediction relates is transferred from the image interval buffer 51 to the control unit 23 via the image bus. PB pixel data The luminance component is also transferred to the motion detection unit 47 via the local bus LB 4 At this time, the data volume

  image that are transferred is 256 pixels.

  When motion prediction is accomplished

  and 2 has prediction it Ei-ntea of image must be accomplished conf or-

  according to the particular coding method, on the basis of the results

  states of the motion prediction, the predicted image (at

  reproduce) is transferred from the inter-

  image range 51 to the pixel processing unit 33 via the pixel data bus PB, for coding At this time, the volume of image data that is transferred is 451 pixels for one plane of the predicted image So we transfer 902 pixels for the prediction

bidirectional.

  Next, image data to be encoded is transmitted

  from the image interval buffer 51 to the pixel processing unit 33 via the pixel data bus PB At this time, the volume of

  Image data that is transferred is 384 pixels.

  In parallel with the four image data transfers mentioned above, the

  luminance of the image in the motion search range.

  The motion prediction unit 47 is transferred from the local memory 56 to the motion detection unit 47 via the local data bus LDB. At this time, the volume of image data transferred is 768 pixels per second. reference image plane Therefore, for bidirectional prediction, it is necessary to transfer 1536 pixels corresponding to two planes. After the end of the coding, with regard to an image for intra-interrupter image coding and an image for the

  unidirectional prediction, reproduction image data

  are transferred from the pixel processing unit 33 to the image interval buffer 51 by

  via the PB Simultaneous pixel data bus

  the luminance component of the image to be reproduced

  is transferred to local memory 56 via

  LDB local data bus.

  At this time, the control unit 23 produces an output control signal to control the port P1 connected to the pixel data bus PB, in synchronism with the transmission of the image data to be reproduced by the processing unit. of pixels 33, from the internal reproduction image output memory (for example the image memory 335 shown in Fig. 19, which will be described later) simultaneously, while luminance data is output by the reproduction image output memory, the control unit 23 produces an output control signal for controlling the port P 2 which

  is connected to the local LDB data bus.

  In the pixel processing unit 33, image data is output from the reproduction image output memory according to an instruction from the control unit 23, or according to a sequence program which is recorded. in an internal memory (for example an internal memory in a unit of

  319 shown in FIG. 19, which is described in FIG.

  ra later) At that moment, under the effect of a signal

  output control that is produced by the communication unit

  Mande 23, the port Pl connected to the pixel data bus

  PB provides image data of a Simultaneous macro-block

  the port P 2 connected to the local data bus LDB only provides the luminance component of the data

  image of a macro-block, under the effect of the signal of com-

  output control which is provided by the control unit 23.

  In the image transfer to be reproduced, which is described above, the volume of image data that is transferred on the pixel data bus PB is 384 pixels, while on the local data bus LDB the

volume is 256 pixels.

  As described above, the treatment unit of

  pixels 33 which is intended to generate a reproduction image

  duire, is designed to have an emission function

  data to two data buses, and the reproduction image

  it is transmitted to the local data bus LDB in synchronism with the transmission of the image to be reproduced to the pixel data bus PB Therefore, the reproduction image output memory (not shown) in the unit The pixel processing unit 33 may be commonly controlled, and data may be transferred to each of the ports connected to the output of the internal memory by means of a single bit of the output control signal. data transfer, view of the control unit 23, is facilitated, and except for the transfer of the reproduction image, the buses are divided by the control unit 23, thus allowing

  a parallel data transfer.

  The volume of data transfer at this time

  becomes maximal in the case of bidirectional prediction-

  and 1926 pixels on the PB pixel data bus and 1536 pixels on the LDB local data bus. Therefore, by using two divided data buses, the volume of data that is transferred by a bus can be reduced in comparison with the sixth embodiment, the practical data transfer rate is improved, and the processing speed in the image compression / decompression apparatus can be increased. (8) Eighth Embodiment FIG. 84 is a block diagram of an image compression / decompression apparatus 108 showing

  an eighth embodiment of the present invention.

  In Fig. 84, the parts corresponding to those of the image compression / decompression apparatus shown in Fig. 83 are designated by the same

  reference characters and their description is not

repeated.

  The pixel processing unit 34 comprises two newly incorporated image data output ports P 4 and P 5. Three data buses, i.e. the pixel data bus PB and two data buses. local LDB 1 and LDB 2, are incorporated as image data bus. The output control operation of the respective ports P 3 to P 5 is effected by an output control signal which

  is provided by a system controller (e.g.

  a system control unit 114 shown in Fig. 13, which will be described later) which is included in a pipeline processing control processor (e.g., the overall control processor).

  It is represented in FIG. 9, which will be described later.

  in the control unit 24.

  When the camera function is enlarged and the motion detection range is enlarged to +64 pixels, image data up to 2304 pixels must be transferred even when

  unidirectional prediction We will present the description

  which follows assuming that the range of the motion detection is enlarged to +64 pixels and unidirectional prediction is performed. In the sixth embodiment which is shown in FIG. 8, the data transfer volume of FIG. picture is

  increased to 4230 pixels when the detection range

  The process in the eighth embodiment is as follows.

  eighth embodiment, for predicting movement

  The luminance component of the image in the motion search range is divided into two, and is transferred by the use of two data buses. More precisely, 1280 pixels are transferred from the local memory 56 a to the prediction unit 47a by the local data bus LDB 1, while 1280 pixels are transferred from the local memory 56b to the motion prediction unit 47b by the local data bus LDB 2 At that moment, data in the data join part must be transferred to both data buses LDB 1 and LDB 2 Therefore, although the volume of data that is transferred by a data bus

  data of 2384 pixels, the volume of trans-

  two data buses will be 2560 pixels in total. In other words, the data volume is increased by the pixel data of a macro-block (256 pixels). This is intended to allow recognition of the junction between respective elements of the data of

divided reference.

  In this case, when the image to be reproduced is transferred, the reproduction image data is transferred from the pixel processing unit 34 to the image interval buffer 51 via the data bus. PB pixel, and simultaneously the reproduction image is transferred to the local memories 56a and 56b via the LDB local data buses 1

and LDB 2.

  The data transfer volume at this time is 1926 pixels on the pixel data bus PB and 1280 pixels on each of the local data buses LDB 1 and LDB 2 More precisely, the volume of data that is transferred on a bus can be reduced because the bus

  image data is divided into three, the

  that data transfer is increased to more than double that of the sixth embodiment, and it is possible to improve the seventh embodiment of

  the image compression / decompression device.

  (9) Ninth Embodiment Fig. 85 is a block diagram of an image compression / decompression apparatus according to

  a ninth embodiment of the present invention.

  In Fig. 85, the parts corresponding to those of the image compression / decompression apparatus shown in Fig. 84 are designated by the same

  reference characters and their description is not

  repeated. Referring to FIG. 85, it will be noted that the ninth embodiment uses a common address bus AB for the local memories 56c and 56d. The address bus AB is connected to the control unit 25 and

  address signals are emitted by the control unit 25.

  When the motion search range is set to + 32 pixels in motion prediction

  bidirectional, as the function of the appa-

  compression / decompression image, it becomes necessary to transfer 1280 pixels for 1 plane of the predicted image In what follows, we describe the transfer

  image data assuming that the search for the motion

  is performed over the range of + 32 pixels and that

  bidirectional prediction is performed.

  Data transfer will first be described in the case of images for intra-interval coding. For example, when image data to be reproduced that is stored in local memory 56d are newer ( appeared later), in comparison with the image data for reproduction that is recorded in the

  local memory 56c, or when the initial image data

  they must be coded (the data are not recorded

  in one of the local memories 56c and 56d), the data transfer is performed in a manner similar to that of the seventh embodiment, using the control unit 25, the buffer memory image interval 51, the pixel processing unit 34, the motion prediction unit 47a, the local memory 56c, the pixel data bus PB and the local data bus LDB 1 The signal the luminance of the image to be reproduced is stored in the local memory 56c to be used as reference data for

  motion prediction At this point, the unity of com-

  Mande 25 controls the writing of data by selecting the local memory 56c by means of a chip selection signal, and it applies an output control signal to the output port P 4 on the side of the local data bus LDB 1 of

  the pixel processing unit 34.

  The image data transfer for unidirectional prediction will now be described. If the reproduction image data which is recorded in local memory 56c is newer (later appeared) than the reproduction image data which are stored in the local memory 56 d, for example, the reproduction image data which is stored in the local memory 56c is used as the reference image data for the direction prediction.

  before, and the image data in the scope of the search

  movement prediction are transferred using

  the motion prediction unit 47a, the local memory 56c and the local data bus LDB 1 At this time, only when the luminance signal of the image to be reproduced in the range of the prediction search of movement must be transferred, the control unit 25 controls the transmission of the data by the selection of the local memory 56c by means of the chip selection signal, and it applies an input control signal to the input port on the side of the local data bus LDB 1 of

  the motion prediction unit 47 a.

  With regard to an image transfer other than that envisaged above (for example an original image transfer, an image transfer to be encoded for the motion prediction, an image transfer for forward prediction, an image transfer to code and a

  transfer of image to be reproduced), data is transmitted

  in a manner similar to that of the seventh embodiment, using the control unit 25, the

  image interval buffer 51, the processing unit

  pixels 34, the local memory 56 d, the data bus

  PB and the LDB local data bus 2.

  At this time, the data transfer volume on the PD pixel data bus will have the maximum value

  of 1926 pixels at the time of bidirectional prediction.

  and the data transfer volume on the local data buses LDB 1 and LDB 2 will have the maximum value of 1280 pixels for each bus The luminance signal of the image to be reproduced is recorded here in the local memory 56 d, as reference image data for

  motion prediction At this point, the unity of com-

  Mande 25 controls the writing of data by selecting the local memory 56 d on the basis of the chip selection signal, only when the luminance signal of the image to be reproduced is transferred, and it applies an output signal to the port of exit P 5 on the bus side of

  local data LDB 2 of the pixel processing unit 34.

  The addressing of the local memory 56 d is performed here in a manner similar to the addressing of the local memory 56 c. The transfer of image data for bidirectional prediction will now be described When the data of the image to be reproduced which are recorded in the local memory 56d are newer (appeared later) than the data of the image to be reproduced. reproduce that are saved in local memory 56c, for example,

  the image data for reproduction which is recorded

  in the local memory 56 are used as reference image data for the forward prediction, and the image transfer in the motion prediction search range is performed by the motion prediction unit 47a, the local memory 56c and the local data bus LDB 1 Simultaneously, the image to be reproduced which is stored in the local memory 56b

  is used as a reference image for the prediction

  backward motion, and the image transfer in the range of the motion prediction search is performed using the motion prediction unit 47b, the local memory 56d, and the local data bus LDB 2A. moment, the control unit 25 selects the local memories 56c and 56d by means of the chip selection signal, only when the luminance signal of the image to be reproduced in the range of the motion prediction search must be transferred, so that the common data output control is performed by applying the same address signal, using a common address bus AB The control unit 25 also applies an input control signal to the port entrance on the side of

  local data bus LDB 1 and LDB 2 of the prediction units

  movement respectively 47a and 47b.

  With regard to image transfers other than those envisaged above (for example the transfer of the original image, the transfer of the image to be coded for the motion prediction, the image transfer for the

  forward prediction, image transfer for the prediction

  back and image transfer to be encoded), the image data is transferred in a manner similar to that of the seventh embodiment, using the control unit 25, the interval buffer of image 51, the pixel processing unit 34 and the bus

PB pixel data.

  Thus, the extent of the forward motion search and the extent of the backward motion search, relative to a macroblock, which is the object on which the motion prediction relates, correspond to the same extent. on the real screen Therefore, by common addressing local memories 56c and 56d, it becomes possible to transfer the data in the range of motion prediction search, in

  both directions, using a common address.

  Specifically, with the exception of the chip selection signal of the local memories 56c and 56d, the hardware related to the memory control and the address generation can be used in common by the local memories 56c and 56 d Therefore, in comparison with an example in which address generators are incorporated for respective memories, it is possible to reduce the volume of

  hardware without increasing the volume of data transfer.

  (10) Tenth Embodiment Fig. 86 is a block diagram of an image compression / decompression apparatus showing a tenth embodiment of the present invention. In Fig. 86, the parts corresponding to those of the apparatus of Figs. image compression / decompression shown in Fig. 85 are designated by the same

  reference characters and their description is not

  repeated. Referring to Fig. 86, it will be noted that in the tenth embodiment, the pixel processing unit 34 shown in Fig. 85 is divided into two parts.

  pixel processing units 34a and 34b.

  When motion search is to be performed in the range of + 32 pixels for bidirectional motion prediction, as an expanded function of the image compression / decompression device, it is necessary to transfer 1280 pixels for a plane. predicted image In the following, we describe the image data transfer assuming that motion search is performed in the range of + 32 pixels and that

  bidirectional prediction is performed.

  First of all, the image data transfer will be described for the Image Intra-Interval Imaging When the images to be reproduced which are recorded in the local memory 56b are newer (appeared later)

  that the image data to be reproduced that is recorded

  in the local memory 56c, for example, or when the initial image data is to be encoded (the data is not recorded in either of the local memories 56c or 56d), the transfer of data is accomplished in a manner similar to that of the seventh embodiment, using the control unit 26, the

  image interval buffer 51, the processing unit

  pixels 34, the motion prediction unit 47a, the local memory 56c, the pixel data bus PB and the local data bus LDB 1. The luminance signal of the image to be reproduced is recorded in FIG. local memory

  56 c to be used as reference image data

  For the moment, the control unit 26 controls the writing of the data by selecting the local memory 56 c by a signal of

  chip selection, only when the light signal

  The control unit 36 applies an output signal to the output port P 2a on the side of the local data bus L D1 B 1 of the control unit.

pixel processing 34 a.

  The transfer of image data for unidirectional prediction will now be described When the data of the image to be reproduced which are recorded in local memory 56 c are newer (later appeared) than the data of the image to be reproduced which are stored in local memory 56b, for example, the reproduction image data which is stored in local memory 56c is used as the reference image data for forward prediction, and the transfer in the range of the motion prediction search is performed using the prediction unit 47a, the local memory 56c and the local data bus LDB 1 At this time, the control unit 26 controls the transmission of the data by selecting the local memory 56c, based on the chip selection signal, only when the luminance signal of the image to be reproduced in the scope of the prediction search d This motion is transferred. The control unit 26 applies an input control signal to the input port on the side of the local data bus LDB 1 of the prediction unit.

movement 47 a.

  For image transfer other than those envisaged

  above (transfer of the original image, transfer of the image to be encoded for the motion prediction,

  transfer of the image for forward prediction, trans-

  of the image to be encoded and transfer of the image to

  the data are transferred in a similar way.

  to that of the seventh embodiment, using

  the control unit 26, the buffer memory of

  image value 51, the pixel processing unit 34b, the local memory 56d, the pixel data bus PB and the local data bus LDB 2 The luminance signal of the image to be reproduced is recorded in local memory 56 d to be used as a reference image for motion prediction At this time, control unit 26 controls the writing of data by selecting local memory 56c based on the selection signal chip, only when the luminance signal of the image

to reproduce is transferred.

  The control unit 26 applies an output signal to the output port P 2b on the data bus side

local LDB 2 of the pixel processing unit 34 b.

  The addressing of the local memory 56b is performed here in a manner similar to the addressing of the local memory 56c. The transfer of image data for bidirectional prediction will now be described When the image data to be reproduced that is recorded in local memory 56b are newer (later appeared) than the data of the image to be reproduced. reproducing which are stored in local memory 56c, for example, the image data to be reproduced which is stored in local memory 56c is used as reference image data for forward prediction, and image in the scope of the search for prediction of

  movement is transferred using the prediction unit

  47a, the local memory 56c and the local data bus LDB 1 At this time, the data of the image to be reproduced which is recorded in the local memory 56d are used as image data. reference for the backward prediction, and the image in the range of the motion prediction search is transferred using the motion prediction unit 47b, the local memory 56b and the local data bus LDB 2A at this time, the control unit 26 selects the local memory 56c or 56d with the chip selection signal, only when the luminance signal of the image to be reproduced in the range of the motion prediction search is transferred, so that the transmission of the data is jointly controlled by the application of the same address, using a common address bus AB En

  in addition, the control unit 26 applies a signal of com-

  input side of the input side of the local data bus LDB 1 and LDB 2 of the prediction units of

movement 47 a and 47 b.

  With regard to an image transfer other than that described above (original image transfer),

  transfer of the image to be coded for the motion prediction

  Image transfer for forward prediction,

  image transfer for backward and forward prediction

  image to be encoded), the image data is transferred

  as shown in FIG. 7, using the control unit 26, the image interval buffer 51, the pixel processing unit 34a or 34b, and the data bus of FIG. At this moment, the image is transferred macro-block by macroblock, alternatively using two pixel processing units 34a and 34b, and in the processing unit 34a or

  34 b the coding of two macroblocks is accomplished using

  the time corresponding to the treatment of two macro-

  blocks. when the predictive coding inter-initervae image must be performed, the processing volume in the case of bidirectional prediction is generally very high In the present embodiment, at the time of the bidirectional prediction, the image data are transferred alternately to two pixel processing units 34a and 34b, macroblock by macroblock, so that a pixel processing unit 34a or 34b can have substantially two macro processing time. Therefore, in comparison with the ninth embodiment, the practical operating time of the processing unit can be increased.

  pixels 34a and 34b for bidirectional prediction.

  (11) Eleventh Embodiment Fig. 87 is a block diagram of an image compression / decompression apparatus 111, showing an eleventh embodiment of the present invention in the image compression / decompression apparatus which is represented in FIG. 87, the motion prediction unit 47b which is connected to the bus of

  local data LDB 2 of the eighth embodiment,

  84, is eliminated.

  In this example, a data transfer other than the transfer of the original image from the control unit 27 to the image interval buffer 51 is performed with the original image data divided into luminance component and difference component

  of colors, as follows.

  With regard to the luminance component, for the image intended for intra-interval image coding, the image to be encoded is transferred from the image interval buffer 51 to the pixel processing unit 35. The image to be reproduced is transferred from the buffer

  interval of image 51 to local memory 56 a.

  For the image intended for unidirectional predictive coding, on the motion prediction side, the image data in the motion search range is transferred from the local memory 56a to the motion prediction unit 47, and the image data to be encoded is transferred from the image interval buffer 51 to the control unit 27.

  coding side, the predicted image data is transferred

  from the buffer 51 to the pixel processing unit 35, and the image data to be encoded is transferred from the image interval buffer 51 to the unit

  Pixel processing 35 The reproduction image data is

  are transferred to the interval buffer

  image 51 and local memory 56 a.

  In the image for bidirectional predictive coding, on the motion prediction side,

  image data in the scope of motion research

  two image intervals are transferred from the local memory 56a to the motion prediction unit 47, and the image data to be encoded is transferred from the image interval buffer 51 to the unit. prediction 47 through the control unit 27 On the coding side, two predicted image data intervals are transferred from the image interval buffer 51 to the pixel processing unit 35, and the image to be encoded is transferred from the image interval buffer 51 to the image processing unit 51.

pixels 35.

  With regard to the color difference component, for the image that is mapped to the intra-image coding Uie, the image data to be encoded is transferred from the image interval buffer 51 to the unit. The image data to be reproduced is trans-

  to local memory 56 e.

  With respect to the image for unidirectional predictive coding, the image data to be encoded is transferred from the image interval buffer 51 to the pixel processing unit 35, and the predicted image data are transferred from the local memory 56 e to the pixel processing unit 35 The image data to be reproduced are transferred to the memory

local 56 e.

  In the case of bidirectional predictive coding, the color difference signal of the image to be encoded is transferred from the image interval buffer 51 to the pixel processing unit 35, and two data intervals of predicted images are transferred from 56 th local memory to the unit of

  pixel processing 35 Lesestizmations of the volume of trans-

  respective data bus image in bidirectional prediction, in which the data transfer volume becomes the maximum, are as follows for the 4: 4: 4 format image having a difference component

concordant color.

  In the image compression / decompression apparatus of the sixth embodiment, shown in FIG.

  figure 8, the volume of data transfer that is trans-

  checked on the PD pixel data bus for the format

  mentioned above is a total of 4806 pixels.

  However, in the image compression / decompression apparatus of the eleventh embodiment shown in Fig. 87, for the 4: 4: 4 format mentioned above, 768 pixels of original image data, 578 pixels of the luminance component of two predicted image data intervals and 768 pixels for the image data to be encoded are transferred onto the PD pixel data bus, and therefore the total data transfer volume is reduced. at 2114 pixels only. On the LDB local data bus 1, when the motion search range is +16 pixels, the volume will be 768 pixels for a predicted image data plane, and therefore the data transfer volume will be 1536 pixels for both data plans

predicted images.

  On the local bus LB 5, only 578 pixels of luminance component of the predicted image data of

  two plans are transferred for the components of

  respectively Cb and Cr, and therefore the data transfer volume is a total of 1156 pixels. By separately encoding respective components of the image data and providing an additional bus LB for the color difference components, the data transfer volume on the pixel data bus PB can be reduced. it is an average of the volume of data transfer for respective data buses that intervenes, the volume of data

  transfer of a data bus is reduced.

  compared to the sixth embodiment shown in FIG. 8, the data transfer rate is improved in a ratio which is substantially

  2.2 times, and as a result it is possible to increase

  the processing speed in the compres-

image decompression / decompression.

  (12) Twelfth Embodiment Fig. 88 is a block diagram of an image compression / decompression apparatus 112 showing

  a twelfth embodiment of the present invention.

  The twelfth embodiment shown in Fig. 88 is obtained by dividing the pixel processing unit 35 of the eleventh embodiment shown in Fig. 87 into two pixel processing units 35a.

  b, to which the

  of the luminance component and the processing of the

  color difference component.

  Therefore, in the twelfth mode of

  In this case, processing is performed for respective components by the pixel processing units a and b, the processing volume in a pixel processing unit can be reduced, and the result is that the processing speed can be improved. in the apparatus of

compression / decompression of image.

  (13) Thirteenth Embodiment Fig. 89 is a block diagram of an image compression / decompression apparatus 113, showing a thirteenth embodiment of the present invention. In addition to the structures of the eleventh and twelfth embodiments, the thirteenth embodiment includes a structure that can accept the development

  of the extent of movement search More precise-

  the minimum required luminance component is extracted separately by a set of pixel processing units 36a and 36b from the image data which is transferred from the image interval buffer 51 to reference data for the

  motion prediction The extracted data are recorded

  registered in local memories 56a and 56b through

  local data bus LDB 1 and LDB 2.

  On the other hand, the pixel processing unit 35b extracts a color difference component, which is not used for motion prediction, from the image data that is transferred from the memory

  image interval buffer 51 The difference component

  The color difference that is extracted is recorded in the

  Local memory 56 th via the local bus LB 5.

  In the structure described above, the volume of trans-

  Data inference on the PB pixel data bus would be 768 pixels of original image data, 578 pixels of luminance component of the two planes of image data

  predicted and 768 pixels of image data to be encoded, that is,

ie a total of 2114 pixels.

  If the extent of the motion search is + 32 pixels, data corresponding to 1280 pixels are transferred to each of the local data buses LDB 1 and

LDB 2.

  In addition, 578 pixels of luminance component

  both planes of the predicted image data are trans-

  for the respective color difference components Cb and Cr, on the local data bus LB 5, and therefore data representing a total of 1156

pixels are transferred.

  With the structure described above, when the range of motion search is increased and the 4: 4: 4 format is selected for the image format to

  manipulate, it is possible to reduce the volume of trans-

  data on the PB pixel data bus, and the volume of data transfer can actually be

divided by the respective buses.

  (14) Fourteenth Embodiment Fig. 90 is a block diagram of an image compression / decompression apparatus 114 showing

  a fourteenth embodiment of the present invention;

  In the fourteenth embodiment, an amplification

  800-bit, 32-bit, two-way, three-state divider-divider is added to connect the pixel data bus PB and the local data bus LDB. The pixel processing unit 37 which does not include the second port can be used. data output connected to the bus of

  local data LDB, as shown in FIG.

  The control unit 29 also controls the operations of bidirectional tri-state amplifier 80, motion prediction unit 47 and local memory 56.

  motion prediction are transferred through the

  the local LDB data bus.

  At this point, the transfer units 21 are also controlled by the control unit 21. The bidirectional tri-state amplifier 80 is capable of performing

  simultaneously reading data and issuing data.

  which have been recorded, in synchronism with a

  clock signal from the control unit 29.

  Referring to Fig. 90, the image data transfer in image coding and image data transfer volume in the processing of a macro image data block will be described. the image data to be encoded have already been recorded in the

  image interval buffer 51, and the component

  the luminance of the reference image (image

  reproduce) which is necessary for the detection of movement

  has already been stored in memory

  Local 56 The transfer volume is calculated based on

  that the aspect ratio is 4: 2: 0, that the range of

  motion detection is +16 pixels and that the structure

  ture is the image interval structure.

  First, the original image data is transferred from the control unit 21 to the image interval buffer 51 via the pixel data bus PB. data

  image that are transferred is 384 pixels.

  Then, the luminance component of the image for the motion prediction is transferred from the image interval buffer 51 to the control unit 29 via the pixel data bus PB and then to the control unit. motion prediction unit 47 via a dedicated local bus LB 4, for the

  prediction of motion At this time, the volume of

  The number of images that are transferred is 256 pixels. When the motion prediction is completed and the prediction-inbrva Ule of image has to be performed on the basis of the determined encoding mode using the result, the predicted image (image to be reproduced) is transferred from the buffer memory. Fig. 51 to the pixel processing unit 37 via the pixel data bus PB for coding At this time, the volume of the image data that is transferred is 451 pixels for one plane of the predicted image Therefore, one has to

  transfer 902 pixels of data at the time of the prediction

bidirectional.

  Then, the image to be encoded is transferred from the image interval buffer 51 to the pixel processing unit 37 via the pixel data bus PB. At this time, the data volume

  image that are transferred is 384 pixels.

  In parallel with the four aforementioned image data transfer processes, the component of

  luminance of the image in the motion search range.

  It is transferred from the local memory 56 to the motion prediction unit 47 via the local data bus LDB for the motion prediction. At this time, the volume of the image data that is transferred

  is 768 pixels for a plane of the reference image.

  Therefore, at the time of bidirectional prediction,

  it is necessary to transfer 1536 pixels of

data for both plans.

  After the end of the coding, with regard to the image for the intraintervalle image coding and the image for the unidirectional prediction, the data of the image to be reproduced is transferred from the pixel processing unit 37 to the image interval buffer 51

  via the PB Simul-

  at the same time, the data of the image to be reproduced are trans-

  In addition, the image to be reproduced is transferred from the tri-state separator amplifier.

  bidirectional 80 to local memory 56 via

  The control unit 29 controls the transfer of data to the local memory 56 through the bidirectional tri-state amplifier 80 only when the local data bus LDB is delayed by one cycle of the system. component of

  luminance of the image to be reproduced is being trans-

  At this time, the volume of image data that is transferred is 384 pixels on the data bus of

  PB pixel and 256 pixels on the LDB local data bus.

  As described above, since the control unit 29 comprises a system control unit (not shown) which controls the transfer of data to the

  local memory 56 via the amplifier-

  bidirectional three-state separator 80, only when the luminance component of the image to be reproduced is being transferred, it becomes unnecessary for the pixel processing unit 37 to include a second data output port which is directly connected to the LDB local data bus, and the buses can be divided in a manner similar to that of the seventh embodiment shown in Figure 83, which allows the processing

  in parallel with the data transfer.

  At this moment, the volume of data transfer

  equivalent to that of the seventh embodiment

  83, and it becomes the maximum at the time of the bidirectional prediction. More precisely, 1926 pixels of data are transferred on the pixel data bus PB and 1536 pixels of data are transferred on the local data bus LDB. , by dividing the

  bus, we can reduce the volume of data that is trans-

  on a single bus, the speed of data transfer can be significantly improved, and the processing speed in the compression apparatus can be improved /

image decompression.

  (15) Fifteenth Embodiment Fig. 91 is a block diagram of an image compression / decompression apparatus 115, showing a fifteenth embodiment of the present invention.

  The fifteenth embodiment has a structure

  wherein bitstream data is input / output via a buffer memory 6 and an external communication apparatus 94 The bitstream data which is obtained by encoding image data by means of a variable length processor (not shown) which is included in the unit of

  command 23, and range / level data is temporally

  stored in the buffer memory 6

  it is possible to transfer only bit stream data without passing through the host computer 93, which

  which improves the transfer speed.

  Specifically, the host computer 93 is heavily loaded because many diverse processes such as command control, in addition to the data transfer process, take place in the host computer 93 With the communication apparatus 94 outside the image compression / decompression apparatus 215,

  can transfer data to the communica-

  94 from the buffer 6 without passing through the host computer 63, and therefore data can be transferred at a high speed, independently of the

load of the host computer 93.

  2 Control unit (1) Control unit 21 (first example) Fig. 9 is a block diagram showing an example of a control unit The control unit 21 which is shown in Fig. 9 is applicable to the unit 2 which is shown in the figures

1, 5, 6, 7 and 8.

  Referring to FIG. 9, it is noted that the control unit 21 comprises a processor 11 for the overall control, comprising the control of the pipeline processing, a processor 12 for coding and variable length decoding, a unit order 13 for one unit

  motion prediction (eg the prediction unit

  41 which is shown in FIG. 1), an image format conversion unit 14 for converting the image format, an image data transfer control unit 15, an instruction transfer unit 16 for a pixel processing unit (e.g. unit 3 shown in Fig. 1), a main port 17 connected to a host bus (bus HB shown in Fig. 1), a video RAM port (VRAM) 19 connected to an input / output bus (IOB bus shown in FIG. 1), and a code data port 20 connected to a code data bus (code bus CB shown in FIG.

1).

  In Fig. 9, generally, the reference symbol "DT" designates a data signal, "ADR" designates an address signal, and "Sc" designates a control signal. The respective units 12 to 16 are connected

  to the overall control processor Il through

  bus and receive instructions from the overall control processor.

  units 12 to 16 perform a treatment in a mutually

  independently, in accordance with the instruction applied.

  The control unit 13, the format conversion unit 14 and the image data transfer control unit 15 are connected to buses for pixel data, and the pixel data transfer is performed under the control of the transfer control unit of

image data 15.

  The main port 17 is connected to the set control processor 11 and the variable length processor 12 When data is transferred between the

  processor 11, the variable length processor

  12, the buffer memory 6 and the working memory 7 shown in FIG. 1, the data are transferred

  through the main port 17.

  The image data port 18 is connected to the image data transfer control unit 15.

  transfer of data between the transmission control unit

  data feed 15 and the image slot buffer 51 shown in Fig. 1 is performed through the image data port

  18 When the destination of the inter-

  image level 15 is the motion prediction unit 41 or the pixel processing unit 3, the image data port 18 provides a control signal which indicates whether

the data is valid or not.

  The VRAM port 19 is connected to the picture format conversion unit 14 The data transfer between the picture format conversion unit 14 and the input / output memory 81 which are represented on the picture.

  Figure 1 is accomplished through the port VRAM 19.

  The image compression process will be described with reference to FIGS. 1 and 9. It is assumed that image data to be compressed has been recorded in the image interval buffer 51 which is shown

  in Figure 1 In the first place, the communication processor

  Set-up 11 transfers image data from the image slot buffer 51 to the image format conversion unit 14, applying an image data transfer instruction to the unit. The overall control processor 11 is informed of the end of the data transfer by the transfer control unit of the data transfer control unit.

image data 15.

  Then, the set control processor 11 applies an image format conversion instruction to the image format conversion unit 14 The image format conversion unit 14 performs operations to convert the format More precisely, a subsampling of color difference signals and a conversion from RGB to YUV format are performed in the image format conversion unit 14 The end of the data transfer is signaled the

  overall control processor 11 by the communication unit

  image data transfer command 15.

  In order to perform processing for motion prediction and coding mode determination, the set control processor 11 transfers image data for the motion interval buffer frame motion prediction. 51 to the prediction control unit 13 This data transfer is accomplished by applying an image data transfer instruction to the image data transfer control unit 15, from the control processor of the 11 The set control processor 11 is informed of the end of the data transfer by the control unit.

  image data transfer control 15.

  The set control processor 11 applies a data downsampling instruction to the motion prediction control unit 13 when necessary, whereby the motion prediction control unit 13 performs a sub-sampling operation. sampling the image data that is the subject of the motion prediction The overall control processor 11 is informed of the end of the subsampling of the data by

the control unit 13.

  Then, the set control processor 11 applies a mode evaluation operation instruction for the image intoe-interva Ie coding to the control unit of the controller.

  prediction of movement 13 The control unit 13 performs

  kills an operation for values evaluated in the image intra-interval coding mode on the data that fetched the object of

  motion prediction (data that has been sub-

  sampled according to need) The overall ordering process 11 is informed of the end of this

  operation by the control unit 13.

  Further, the set control processor 11 applies a data transfer instruction to the image data transfer control unit 15, and the image data transfer control unit 15 transfers to the image data transfer control unit 15, and the image data transfer control unit 15 transfers to the image data transfer control unit 15. motion prediction unit 41 of the image data in the motion search area, from the image interval buffer 51 The overall control processor 11 is informed of the end

  data transfer by the transmission control unit.

image data 15.

  Then, the set control processor 11 applies a data transfer instruction for the motion prediction to the control unit 13 of the motion prediction unit, and the control unit

  13 transfers the data to be detected (under-

  as required) to the motion prediction unit 41 The overall control processor is informed of the end of the data transfer by the image data transfer control unit 15. After the image for the search and the image data for the motion prediction has been transferred, the motion prediction unit 41 starts the motion prediction, and after a while it generates the result of the prediction movement, that is, the data evaluated for the mode

inter-interval coding.

  After the lapse of a certain duration, the set control processor 11 applies to the motion prediction control unit 13 an instruction to receive the result of the motion prediction, and the control unit 13 receives from the motion prediction unit 14 data that indicate the result of the motion prediction The

  general order 11 is informed of the end of the

  data transmission by the control unit 13.

  Then, the set control processor determines the encoding mode on the basis of the value data of the intra-interval image coding mode, which are

  obtained by the operation carried out in the com-

  13, and on the basis of the evaluated value data for the interlayer mode, which is obtained by the operation which is carried out

  in the motion prediction unit 41 The determination

  encoding mode is performed by reference to encoding mode determination table data which is stored in the buffer memory 6, or

comparing the evaluated data.

  After determining the coding mode, a source coding, i.e. discrete cosine transformation and quantization, is performed. First, the set control processor 11 applies a data transfer instruction of image to the image data transfer control unit 15, and the image data transfer control unit 15 transfers to the pixel processing unit 3

  data to be encoded from the interworking buffer

  image valle 51 The overall control processor It is informed of the end of the data transfer by the unit

  for controlling image data transfer 15.

  Next, the set control processor 11 applies a source encoding instruction to the pixel processing unit 3 via an instruction transfer unit 16 for the pixel processing unit L. pixel processing unit 3 performs the source coding, i.e. discrete cosine transformation and quantization, under the control of the source coding instruction.

  overall order 11 is informed of the end of the

  by the pixel processing unit 3, through the

  of the Instruction Transfer Unit 16.

  After source coding, ie discrete cosine transformation and quantization,

  Variable length coding is performed

  The set control processor 11 applies to the pixel processing unit 3 via the instruction transfer unit 16 an instruction which requests the transfer of the processed data. this instruction, the pixel processing unit 3 transfers the processed data to the variable length processor 12 The overall control processor It is informed of the end of the data transfer by the pixel processing unit 3, by intermediary

  the instruction transfer unit 16.

  To perform variable length coding,

  that is to say the entropy coding, the comm processor

  The variable-length processor 12 performs the entropy coding in the entropy coding.

  code, using the Huffman code or whatever, is performed.

  Specifically, the variable length processor 12 performs the code conversion of the data obtained by the source coding, with reference to code conversion table data that is stored in the working memory 7. The control processor 11 is informed of the end of the entropy coding by the processor to

variable length 12.

  After the end of the entropy coding, the set control processor 11 applies to the processor at

  variable length 12 an instruction that requires the trans-

  processing of the processed data The variable length processor

  ble 12 transfers the processed data to buffer 6 The set command processor It is

  informed of the end of the data transfer by the

variable length 12.

  As can be seen from the description

  above, the compression of the image data can be performed independently in various processing units 13, 14, 15 and 16 in the control unit 21, as well as in the variable length processor 12, under the control of whole of the control processor 11 More precisely, the conversion of image format by the unit

  image format conversion, motion prediction,

  and the operation for encoding the evaluated value for the mode, by the motion prediction unit 41 and the motion prediction unit control unit 13, the image data transfer by the image data transfer control unit 15, the source coding by the pixel processing unit 13 and the entropy coding by the variable length processor 12, can be performed in parallel and independently of each other.

  Therefore, the overall control processor

  It performs the processes described above for each macro-block of image data, under the control of the pipeline processing. The pipeline processing of the processes described above will be described in detail with reference to

  subsequent to Figures 11 and 12.

* line enables very efficient image compression. Image decompression is also performed in a manner similar to image compression, and

  various processes in the control unit 21 are accom-

  folds independently of each other, under the overall control of the set control processor 11 In the image decompression, code data stored in the buffer memory 6 are reverse converted, and finally the decompressed image data

  are transferred via the conver-

  image format 14 to the input / output memory

  81 which is shown in Figure 1.

  (2) Control unit 22 (second example) Figure 10 is a block diagram showing

  another example of the control unit

  22 which is shown in FIG.

  cable to the control unit 22 which is shown in FIG. 4 In comparison with the control unit 21 which is shown in FIG. 9, the motion prediction unit control unit 13 is eliminated from the More specifically, the image compression / decompression apparatus 102 shown in FIG. 4 does not require a motion prediction and, correspondingly, the prediction unit control unit. movement is eliminated from the unit of

order 22.

  It is noted that with the exception of motion prediction, the control unit 22 shown in Fig. 10 functions similarly to the control unit 21 shown in Fig. 9. obtain similar advantages to those of the control unit 21 which is shown in FIG. 9, that is to say that various internal units of the control unit 22 can operate independently of each other and in parallel with the compared to each other, and compression of the image data can be effected efficiently under the control of pipeline processing. (3) Pipeline Processing The set control processor 11 shown in FIGS. 9 and 10 accomplishes the pipeline processing in the apparatus of FIG.

compression / decompression of image.

  Fig. 11 is a time chart showing the pipeline processing that is performed under the control of the set control processor 11 shown in Fig. 9 On Fig. 11, the abscissa represents time and the ordinate represents process steps for In image compression, a data frame to be processed is divided into a number of macroblocks MB, and processes for image compression are performed on each macroblock of data. example which is represented in FIG. 11, data of ten macroblocks MB 1 to

MB 10.

  Referring to FIG. 11, the processing of an MBI macroblock will be described by way of example. Firstly, during the period T1, the RGB data of the macroblock of data MB 1 are transferred from the data memory. input / output 81 shown in FIG. 1 to the control unit 2 (step S1) During the period T 2, the RGB data is converted into YUV data by

  the image format conversion unit 14 which is

  shown in Figure 9 (step 52).

  During the period T 3, the YUV data is transferred to the memory and image slot buffer 51, and the image data that is being searched

  are transferred to the control unit 2 Simultan-

  The image data being searched is transferred to the motion prediction unit 41 via the pixel data bus PB (step 53).

  During the period T 4, the prediction of movement

  This is done by the motion prediction unit 41 (step 54). During the period T 5, the coding mode

  is determined by the control unit 2 (step 55).

  During the period T 6, the image data to be encoded is transferred from the image interval buffer 51 to the pixel processing unit 3, while the reference image data is transferred to the image processing buffer 51. pixel processing unit 3 through the

  PB pixel data bus (step 56).

  During the period T 7, the image processing for the coding, ie the discrete cosine transformation and the quantization, is performed by the pixel processing unit 3 (step 57). During the period T 8, the processed data, i.e. the range / level data are transferred to the buffer memory 6 by

  via the CB code bus (step 58).

  During the period T 9, the length coding

  variable is performed by the variable length processor.

  12 which is shown in FIG. 9 (step 59).

  During the period T 10, the processed data, i.e. the variable length code data, is transferred via the code bus CB to the memory

buffer 6 (step 510).

  As described above, in the image compression / decompression apparatus 101, pipeline processing is accomplished under the control of the ensemble control processor 11 Therefore, as shown in Fig. 11, corresponding processes are successively during periods T 2 to T 10 on other macro-blocks of data MB 2 to MB 10, of the same

  only on the macro-block of data MB 1.

  Figure 12 shows the operation in parallel

  Figure 11 shows the operating state in the period T 10 of various internal units in the control unit 21 and the compression / decompression apparatus of the control unit 21, which is shown in FIG. 11. Fig. 101 which is shown in Figs. 1 and 9 Referring to Fig. 12, it is noted that during the period T 10, the input / output bus IOB transfers RGB data of the tenth macroblock MB 10 (step 10). SI shown in Fig. 11) The data bus

  Pixel PB transfers data from the eighth and fifth

  MB 8 and MB 5 macro-blocks (steps 53 and 56) The CB code bus transfers data of the third and first

  macroblocks MB 3 and MB 1 (steps 58 and 510).

  The set control processor 11 controls the RGB data transfer of the tenth macroblock MB (step 53), and in parallel thereto, it determines the coding mode of the sixth macroblock MB 6 (step 55). Moreover, the set control processor 11 performs a

  macroblock sequence control MB 1 to MB 10, i.e.

  say a command for pipeline processing.

  The variable length processor 12 performs variable length coding on the second macroblock MB 2 (step 59). The instruction transfer unit 16 performs an image processing control of the fourth macroblock.

MB 4 (step 57).

  The motion prediction unit control unit 13 performs a motion prediction for the seventh macro block MB 7 (step 54). The image data transfer control unit 15 controls the data transfer of the eighth and fifth macroblocks MB 8 and MB 5

(step 58).

  The image format conversion unit 14 performs a format conversion (from RGB to YUV) on the ninth macroblock MB 9 (step 52). The processing unit

  pixels 3 performs image processing on the fourth

  MB 4 macro-block (step 57) The motion prediction unit 4 makes a prediction for the seventh

macro-block MB 7 (step 54).

  (4) Structure of respective internal units (i) Ensemble control processor II (FIG. 13)

  Figure 13 is a block diagram of the process

  The overall control driver 11 shown in FIG. 9 Referring to FIG. 13, the overall control processor 11 includes an instruction memory 111, a program control Sequence control unit / address processing unit 113, a system control unit 114, a group of operation registers 115 and a data processing unit 116 In this figure, the reference symbol "DT" designates "ADR" means an address signal, "ID" means instructional data, "S Sc" means a status control signal and "Sc" means

a control signal.

  (ii) motion prediction control unit

  13 (Figure 14) Figure 14 is a block diagram of the unit

  motion prediction control 13 which is

  FIG. 9 Referring to FIG. 14, it will be noted that the motion prediction control unit 13

  includes a mode / time control unit

  131 for the motion prediction unit, an ensemble control unit 132, a vector data processor 133, a processor 134 for the image data, for the motion detection, and a unit of

  evaluation processing 135 for the intra-coding mode.

picture interval.

  The mode control unit / time conditions

  Roles 131 produces a control signal Smc for the motion prediction unit 41 The vector data processor 133 also produces a control signal Smc for the motion prediction unit 41 The vector data processor 133 receives from of the motion prediction unit 41 of the Dmr data indicating the results of the motion detection The processor 134

  for image data relating to motion detection.

  produces a control signal Smc for image data Dmi which is the object of the motion detection,

  and for the motion prediction unit 41 The process

  134 for the image data for motion detection applies PD pixel data to the

  evaluation processing 135, for the intra-coding mode

  frame. (iii) Image Format Conversion Unit 14 (Fig. 15) Fig. 15 is a block diagram of the image format conversion unit 14 shown in Fig. 9 Referring to Fig. 15, it is noted that the image format conversion unit 14 comprises an assembly control unit 14, a video random access control unit (VRAM) 142, a color converter

  143, a UV filter 144 and an image memory 145.

  The set control unit 141 receives DT data and an address signal ADR via a main data bus MB The VRAM control unit 142 is connected to the VRAM port 19 The image memory 145 receives PD pixel data via the IPB internal pixel data bus and provides

recorded data.

  (iv) Image Data Transfer Control Unit 15 (Fig. 16) Fig. 16 is a block diagram of the image transfer control unit 15 shown in Fig. 9 Referring to Fig. 16, it is noted that the image data transfer control unit 15 comprises an assembly control unit 151, an image data memory control unit 152, a data transfer control unit 153 and a pixel data bus transfer control unit 154. In Fig. 16, the reference symbol "Simc" designates an image data memory control signal, "Sptc" designates a signal of image data transfer control for the pixel processing unit 3, and "Smtc" means an image data transfer control signal for the motion prediction unit

41.

  (v) Instruction transfer unit 16 (Fig. 17) Fig. 17 is a block diagram of the instruction transfer unit 16 which is shown in Fig. 9 Referring to Fig. 17, it is noted that instruction transfer unit 16 for the pixel processing unit 3 comprises a control unit

  set 161, an instruction transfer control unit

  truction 162 and a state monitoring unit 163.

  The instruction transfer control unit 162 produces a control signal Spc for the pixel processing unit 3 The status monitoring unit 163 receives the status signal Sps that originates from the processing unit 3 The set control unit 161 receives the data DT and the address signal ADR via

of a main data bus MB.

  In this way, the internal units 13, 14, 15

  and 16 which are shown in Figures 14 to 17 received

  respectively, signals requesting the start of respective processes, from the set control processor 11 shown in Fig. 13, and send back to the set control processor 11 control signals indicating the end of the process

  respective processes, when the respective processes are terminated

  Thus, it is noted that the internal units 13, 14, 15 and 16 perform respective processes independently of each other in dependence on process start signals from the control processor.

  11 Therefore, under the control of the

  set command 11, data processing for image compression and image decompression

  can be effectively accomplished in a pipeline manner.

  (5) Control Unit 200 (Third Example) Figure 92 is a block diagram showing

  yet another example of the control unit.

  The control unit 200 which is shown in the figure

  92 is applicable to the control unit which is

  shown in Figures 1, 5 to 8 and 84 to 91.

  Referring to Figure 92, it is noted that the controller 200 includes a host interface portion 201 connected to a host bus HB; an assembly control part 202 for performing various commands including a pipeline processing command; a video input / output portion 203 connected to an input / output bus IOB; a main processor 204 which executes programs written in the form of macro-codes; an image gap memory control portion 205; a motion prediction unit control portion 206 for controlling an image gap memory for motion prediction; a code data control portion 207 that manipulates code data that is exchanged with the pixel processing unit; a parameter processing part 208; and a variable length processor 209 for length coding / decoding

variable.

  Further, the control unit 200 includes, as internal buses, a first internal bus 210 connected between the video input / output portion 203 and the dimming interval memory control portion 205; a 2 U 1 internal bus secoid connected between each of the elements including the interva memory control portion Jle 205, the motion prediction unit control portion 206 and the parameter processing portion 208; a third internal bus 212 connected between the motion prediction unit control portion 212 and the image slot memory control portion 205; a fourth internal bus connected between the code data control portion 207 and the variable length processor 209; and a main bus

214 connected to all the blocks.

  We will now describe the structure and the

functioning of various blocks.

  The host interface portion 201 is a control portion that controls the transfer of data between an external host computer and the control unit 200. The data that is received / transmitted via the interface portion of the host 201 are transferred by the main bus 214 which is connected to each block in the unit

200.

  The overall control part 202 is a block

  which essentially controls various temporary conditions

  In the encoding of an image, the set control portion 202 generates an internal sync pulse at each pixel or macroblock, at the time of image encoding. the base of a basic clock and a synchronization signal, it controls the main parameters in the coding, it transfers data, etc. The video input / output portion 203 has an interface with the input / output memory 81 which is shown in Fig. 83, for example, and in the control unit 200 it is connected to the memory control portion. image interval 205 by the first bus

internal 210.

  The main processor 204 is a block which is essentially responsible for the adaptive processing in the

  coding, the details of which will be described later.

  If there is a conflict with the host interface part 201,

  the main processor 204 will be the master of the main bus

  pal 214, and performs the transfer of data from registers

be / memory in each block.

  The image interposer memory control portion 205 includes, as an external interface, a 32-bit interface, which operates in the manner of a master of a 32-bit pixel data bus (e.g. the pixel data bus PB of Fig. 83) between the image gap buffer (for example, the image slot buffer 51 shown in Fig. 83) and the processing unit of pixels (e.g., the pixel processing unit 33 shown in Fig. 83) The image gap memory command part 205 is connected in the control unit 200 to the part of video input / output 203 through the

  first internal bus 210, to the control part of para-

  meters 208 and to the prediction unit control part

  movement 206 through the second internal bus 211, and further to another interface of the motion prediction unit control portion 206

  via the third internal bus 212.

  The motion prediction unit control portion 206 includes, as external interfaces, an interface that applies a control signal to the motion prediction unit (e.g., the motion prediction unit 47 shown in FIG. Fig. 83), and an interface that applies a control signal, including an address, to the local memory (e.g. local memory 56 shown in Fig. 83). The motion prediction unit control portion 206 further comprises an interface with the local bus (for example the local bus LB 4 which is shown in Fig. 83), for transferring parameters such as a motion vector and model data (image data) to

  the motion prediction unit and from that

  In addition, the motion prediction unit control portion 206 is connected in the control unit to the image gap memory control portion 205 and the parameter control portion 208. through the second internal bus 211, and the image gap memory control portion 205 through

  via the third internal bus 212.

  The code data control part 207 has an interface which is connected to a code bus (for example the code bus CB shown in FIG.

  83) which is intended to be connected to the treatment unit.

  pixels (e.g., the pixel processing unit 33 shown in Fig. 83) and the buffer memory (e.g., the buffer memory 6 shown in Fig. 83).

  code data 207 is connected in the communication unit

  200, to the variable length processor 209 by

  via the fourth internal bus 213.

  The parameter processing portion 208 is connected to the image interval memory control portion 205

  and the motion prediction unit control part

  206 through the second internal bus 211.

  Model data is transmitted from the image interval memory control portion 205 to the parameter processing portion 208 through the second internal bus 211, and the parameter processing portion 208 extracts related parameters. to the model

  parameter processing part 208 includes a regis-

  which retains the result of the operation which is

  The result of the operation stored in the register can be transferred (read) via the main bus 214 (slave operation). The variable length processor 209 is connected to the code data control portion 207 via the fourth internal bus 213 The variable length coding of the range / level type data or a quantization index from the part code data control 207 is performed in the variable length processor 209 The bit stream data that is produced in the variable length processor 209 is transferred to the image slot buffer (e.g. image slot buffer 51 which is shown in Fig. 83). Detailed will be described, with reference to Figs. 83 and 92, the contents of processes that are performed in respective blocks of the control unit 200 during the

image coding.

  The control unit 23 has the function of com-

  to cause the pixel processing unit 33 and the motion prediction unit 47 to perform the coding. Therefore, the four types of data control

  following are essentially accomplished.

  (1) Reading of original data and recording

  data in the interval buffer

picture 51.

  (2) Reading of model data for prediction

  movement and activation of the prediction unit

of movement 47.

  (3) Reading and determining the results of the motion prediction, and activating the unit of

pixel processing 33.

  (4) Reading and variable length processing of code data (quantization index, range / level),

  and write to the buffer 6.

  The four types of data control will be described with reference to the respective block operations. (i) Read original data and write data to the image interval buffer 51 (projection). The original data that is stored in an external input / output memory (the original image data to be encoded) is segmented on the basis of what is called a macro-block and is transferred to

  the video input / output part 203.

  The video input / output portion 203 contains a conversion circuit from RGB format to YUV format and a

  filter circuit, and the format conversion is accom-

  fold here (eg RGB - * YUV, 4: 2: 2 -> 4: 2: 0, etc.).

  The processed data is transferred by the first bus

  internal 210 to the memory control portion of

  The image interval memory control portion 205 projects (writes) the transferred data, with a format suitable for subsequent encoding, into the image interval buffer 51 which is controlled by the picture interval memory control portion 205 will be described later in

  detail the projection process that is used here.

  The generation of an address for the frame interval buffer 51 is accomplished by the party

  image interval memory control device 205

  of the image slot buffer 51 and the time conditions of the data transfer from the video input / output portion 203 are governed by the

set control part 202.

  (ii) Reading of model data for the

  motion prediction and command of the prediction unit

  Motion To perform the motion prediction of a macroblock to be encoded, the memory control portion

  interval 205 reads the image data corresponding to

  spanning at the macro-block in the interval buffer

  This data is called model data.

  The image gap memory control portion 205 transfers the model data to the motion prediction unit control portion 206 and the portion of

parameter processing 208.

  The motion prediction unit control part 206 transfers the model data to the motion prediction unit 47 via the local bus LB 4 and, simultaneously, it transfers search window data corresponding to the model data, to the local memory 56 via the local data bus LDB Further, the motion prediction unit control part 206 activates the operation of

  prediction of movement of the model data into application

  the motion prediction unit 47, as input information, a control signal such as a

activation command.

  In addition, the frame memory control portion 205 transfers the pattern data to the motion prediction unit control portion 206 by

  via the second internal bus 111 and simultaneously

  it transfers them to the parameter processing part 208 The parameter processing part 208

  extracted from the model data characteristics in accordance with

  to a predetermined operation, and these characteristics

  are used later to determine the coding or other parameters that are calculated here

  include the variance (only of the light signal

  each block (in a frame / inter-

  frame size) of the model for the activity calculation, the average value and the variance value of the luminance signal of the model macro-block, etc., which

  require operations on pixels.

  (iii) Reading the result of the motion prediction and activation of the pixel processing unit After several macro-block cycles from the activation of the motion prediction unit, the result of the motion prediction , i.e., various motion prediction modes, motion vectors backward in the horizontal and vertical directions, and evaluated functions thereof are taken from the prediction unit control portion

  movement 206 via the local bus LB 4.

  The motion prediction unit control portion 206 determines the prediction mode and the motion vector by use of the aforesaid evaluation function. The determined motion vector is transferred to the interval memory control portion. image 205 through the internal bus 212 The image gap memory control portion 205 calculates an address of the predicted image on the

  base of the input motion vector The game part

  Image interval memory command 205 controls the image interval buffer 51 and the pixel processing unit 33 based on the calculated address, and transfers to the pixel processing unit. The predicted image data corresponding to the motion vector. Further, the image gap memory control portion 205 transmits the pattern data to the pixel processing unit 33 in a manner similar to that described above (because the pipeline is

  different from the model data mentioned above.

  above, it is necessary to carry out the trans-

  fer), and by activating the pixel processing unit 33, it causes the pixel processing unit 33 to perform the discrete cosine transform and the

  following processes The order for activation and para-

  meters required for coding in the treatment unit.

  pixels (e.g. half by filter instruction) are placed here in a determined register in the pixel processing unit 33, via the code data control part 205 or the

  host interface part 201, using the same pipe-

  line The pixel processing unit 303 is designed so that it can be packaged from the two aforementioned ports. (iv) Reading and variable length processing of the code data, and writing to the buffer data processed in the processing unit

  pixels 33 (ie the data that was submitted to

  filtering, discrete cosine transformation, quantization, or the like) are written temporarily to the buffer memory 6 via the code bus CB, or they are transferred directly to the data control portion of code 207 of the control unit 23, by the command that is exerted by the set control part 202 The data format at this time corresponds either to the quantization index (data after quantization) or to the range data / level (the aforementioned quantization index converted to a range / level). The code data control part 207

  receives the data at an arbitrary time and trans-

  to the variable-length processor 209 via the fourth internal bus 213 The variable-length processor 209 performs so-called Huffman coding on the data, in accordance with a micro-program, and writes the result in an external buffer 6 At the time of the code conversion, corresponding for example to the Huffman coding, it is possible to access table data which are

  saved in working memory 7.

  In what follows, the manner in which the main processor 204 participates in coding will be described below.

  in the treatment described above.

  Where a determination other than the determination

  If the user wishes to use his own determination method, the process proceeds in the following manner. The main processor 204 accesses a control unit that is performed in the motion prediction unit control part 206. register in which vectors and evaluated values are stored for various prediction modes in the motion prediction unit control part 206, via the main bus 214 The vectors and evaluated values are processed only in the form of macro-codes and they are returned to the original register in a predetermined time.

  adaptive as a determination becomes possible.

  The main processor 204 essentially deals with

  In other words, the main processor 204 is responsible for processes that are performed at the GOP / image / level. For example, the main processor 204 sets encoding parameters of the next image based on the amount of codes used in the encoding of the previous image. The main processor 204 also supports exceptional modes such as the command. of cadence, synchronous refresh, forced internal control, etc. The main processes in the macro-block layer include adaptive quantization that is performed on the basis of activity

calculated.

  As described above, the main processor 204 is able to access a register or memory in each unit of the control unit 23, so that it can refer to the registers or the memory, accomplish some process such as an operation and

  rewrite the contents of the register or memory, provided that

  that these operations are completed during a predetermined acceptable process step.

  a higher degree of freedom in the coding.

  As can be seen from the description of

  In the above coding operation, the coding is performed independently in each of the processing units by pipeline control which is exerted by the set control part 202 in the control unit 23. In other words, the four data control operations mentioned above are performed independently of one another and in parallel with each other. The decoding of images can be accomplished in a manner similar to the coding, by parallel operation of respective blocks in the unit

  command 23, under the effect of a command in pipe-mode

  line which is exerted by the set control portion 202. 3 Pixel processing unit (1) Pixel processing unit 31 (Figs. 18 and 19) Fig. 18 is a block diagram showing an example of the unit of The pixel processing unit 31 shown in FIG. 18 is used, for example, for the image processing unit.

  pixels 3 shown in FIG.

  Referring to Fig. 18, it is noted that the pixel processing unit 31 comprises a host interface circuit (I / F) 311, a local memory group 312, a cosine transformation processing unit Discrete / inverse discrete cosine transformation (or DCT / IDCT) 313, a quantizer 314, a

  filter 315, a selector bus 316, an inter-

  code data bus face 317, a pixel bus interface circuit 318 and a control unit 319. The host interface circuit 311 is embedded

  to exchange data with the host processor, that is,

  between the control unit 2 and the treatment unit

  pixel number 311 The pixel bus interface circuit

  318 is incorporated for the input / output of image data.

  The code data bus interface circuit 317 is

  embedded for the input / output of code data.

  The DCT / IDCT processing unit 313 performs a discrete cosine transform (DCT) operation and an inverse discrete cosine transform operation. The quantizer 314 is incorporated for the first time.

  quantification The filter 315 is incorporated for the gen-

  reference image data ration for motion prediction The selector bus 316 is incorporated to transfer internal data of the pixel processing unit 31 The control unit 319 is incorporated for the overall control of the pixel processing unit 31. Fig. 19 is a more detailed block diagram of the pixel processing unit 31 shown in Fig. 18. The local memory group 312 shown in Fig. 18 includes memory memories. 331 to 335 shown in Fig. 19, data memories 341 and 342, a code data memory 343 and a parameter memory 344 The selector bus 316 shown in Fig. 18

  comprises selector bus SB 1 to SB 5 which are

shown in Figure 19.

  The image memory 331 is incorporated to record

  store image data to be compressed The image memories 332 and 333 record reference image data from previous and next image intervals. The image memory 334 stores the processed reference image data, which The image memory 335 records image data to be decoded. The code data memory 343 records quantized code data. The parameter memory 344 stores table data for an operation, such as a matrix.

of quantification.

  The SB 1 selector bus has a 12-bit bus width and it transfers filtered reference picture data. The SB 2 selector bus has a 12-bit bus width and it transfers difference data after difference calculation. and after inverse discrete cosine transformation The selector bus SB 3 has a bus width of 12 bits and is incorporated to transfer a

  direct cosine transformation factor after trans-

  Direct cosine formation and after inverse quantization The selector bus SB 4 has a bus width of 12 bits and is incorporated to transfer code data after inverse quantization and after development of the zeros. The selector bus SB 5 has a width of 16-bit bus and it is embedded to transfer parameter data. (2) Pixel processing unit 32 (Figs. 20 and 21) Fig. 20 is a block diagram showing

  another example of the pixel processing unit.

  The pixel processing unit 32 shown in FIG. 20 can also be used, for example, for the pixel processing unit 3 which is shown in FIG.

Figure 1.

  Referring to Fig. 20, it will be noted that in comparison with the pixel processing unit 31 shown in Fig. 19, the pixel processing unit 32 further comprises a programmable processing unit 320 L '. programmable processing unit 320 is connected to selector bus 326 and is capable of performing various other operations in accordance with programs that are registered in this unit. For example, the programmable processing unit 320 performs frequently used operations such as addition, subtraction, summation of difference absolute values, accumulation of difference absolute values, summation of difference squares, accumulation of difference squares, multiplication,

  etc., according to recorded programs.

  Fig. 21 is a more detailed block diagram of the pixel processing unit 32 shown in Fig. 20. As shown in Fig. 21, the added programmable processing unit 320 is connected to the selector bus SB 1 to SB In addition, the programmable processing unit 320 is connected to the

* parameter memory 344.

  (3) Operation of the Pixel Processing Units 31 and 32 The operation of the pixel processing unit 31 will be described with reference to Fig. 19. An example of a motion picture coding operation of the type will be described by way of example. with accumulation, according to the MPEG standard. The pixel bus interface circuit 318 receives image data to be encoded from the frame interval memory 51 shown in FIG.

  apply the data to image memory 331 through

  mediator of the IPB internal pixel bus 2 If a prediction

  movement is required, reference image data

  are applied to the image memory 332 in the case

  prediction on the other hand, in the prediction

  bidirectional data, the reference image data of the previous image interval and the next image interval are transferred to the image memories 332 and 333. In the forward prediction, the data that is recorded in the image memory 332 are applied to the filter 315 The filter 315 performs a filtering and the processed reference data is written into the

image memory 334.

  In the case of bidirectional prediction,

  forward reference image data which is recorded

  stored in the image memory 332 are applied to the filter 315, while backward reference image data which is stored in the image memory 333 is also applied to the filter 315. In the filter 315, a filter and a interpolation are performed on

  the reference image data applied, and the data

  generated reference image are written in the

image memory 334.

  A difference generator 310 transfers to the selector bus SB 2 image data to be encoded which

  are stored in the image memory 331 The general

  Difference converter 310 applies to the selector bus SB 2, as needed, difference data between the image data to be encoded and the reference image data which is stored in the image memory 334. The DCT / IDCT processing unit 313 performs a discrete cosine transform operation on the image data or difference data that is applied via the selector bus SB 2 in the encoding, and it transfers over the bus selector SB 3 the inverse cosine transform factor that is generated When a loopback operation for coding and decoding is performed, the DCT / IDCT processing unit 313 performs a reverse discrete cosine transform operation on the discrete cosine transformation which is applied via the selector bus SB 3, and generates image data or difference data. have transferred via selector bus SB 2.

  The quantizer 314 performs a quantization

  on the DCT factor which is applied by the selector bus SB 3, with reference to the parameter memory 344 The code data which is obtained under the effect of the quantization are transferred by the selector bus

  SB 4 to the code data memory 343 In the operation

  loopback for coding and decoding, quantum-

  The indicator 314 performs an inverse quantization of the code data that is applied via the selector bus SB 4. The DCT factor that is obtained under the effect of the inverse quantization is transferred by the

selector bus SB 3.

  In the coding, the code data bus interface circuit 317 receives code data from the SB selector bus 5 which is stored in the code data memory 343. The bus interface interface circuit 315 is code data 314 provides, without modification, the received code data to an external code data bus, i.e. the CD code bus shown in Fig. 1 In some cases, the data is converted in code range / level by the code data bus interface circuit 317 and are transmitted to the code bus CB In the decoding, the code data bus interface circuit 317 performs inverse quantization on the code data that is applied via the selector bus SB 4 The discrete cosine transform factor that is obtained under the effect of the inverse quantization is

  transferred via the selector bus SB 3.

  In the reference picture decoding process for encoding and decoding, the picture decoder 310 provides reference picture data which is applied via the selector bus SB 1, and the result data. the addition of decoded difference data, if a motion prediction is required, and the data is stored in the image memory 335 On the other hand, if the motion prediction is not necessary, the data of decoded images are issued without modification and they are

  stored in the image memory 335.

  The host interface circuit 331 receives operation commands for the pixel processing unit 31 and parameters such as a quantization matrix, via the host bus HB shown in FIG. on the other hand, the host interface circuit 311 provides externally data which is stored in the internal memories 331 to 335 and 341 to 344, as well as data which is recorded.

in internal registers.

  (4) Sequence of operations in the pixel processing unit (Figs. 22-25) (i) Sequence for intra-image predicted image coding in accordance with MPEG Fig. 22 is a flowchart coding in the pixel processing unit 31 shown in Fig. 19 Referring to Fig. 22, it is noted that the image data which is stored in the image memory 331 is applied to the difference generator 310 The applied data are not processed in this case at all, and they are applied to the DCT / IDCT processing unit 313 via the selector bus SB 2 After the discrete cosine transform processing in the control unit. treatment 313,

  data indicating the result of the treatment are applied

  quantizer 314 via the bus of

selector SB 3.

  The quantizer 314 performs the quantization

  referring to the parameter memory 344 through

  The data of the quantization result, i.e., code data, are applied to the code data memory 343.

  and they are recorded in the latter.

  The outputs stored in the code data memory 343 are applied to the external code bus CB (FIG. 1) via the selector bus SB 4 and the circuit.

  code data bus interface 317.

  Figure 23 is a flowchart for deco-

  in the pixel processing unit 31 shown in Fig. 19 Referring to FIG.

  23, we note that the data to be decoded, which are recorded

  stored in the code data memory 343, are applied to

  quantizer 314 via the bus of

  selector SB 4 The quantizer 314 performs a quanti-

  reverse, referring to the parameter memory.

  344 via the selector bus SB 5 Data indicating the result of the inverse quantization are applied to the DCT / IDCT processing unit 313 by

  via the selector bus SB 3.

  The processing unit 313 performs a reverse discrete cosine transform operation on the applied data Data indicating the result of

  the operation are applied to the decoder 310 via the

  The decoder 310 performs a limiting operation on the applied data, and the processed data is applied to the image memory.

  335 to be registered in the latter.

  (ii) Sequence for bidirectional prediction coding according to the MPEG standard Referring to Fig. 24, it is noted that in the coding, the forward direction image data which is stored in the image memory 332 and the

  rear direction image data that is recorded

  The filter 315 performs a 1/2 image processing and pixel interpolation on the applied data. The processed data is applied to the memory of the data store. image 334 and they are recorded in the latter The data which is stored in the image memory 334 is applied to the difference generator 310 via the selector bus SB 1 On the other hand, the image data to be encoded which are saved in the image memory 331

  are also applied to the difference generator 310.

  The difference generator 310 performs an operation of

  pixel difference calculation on the applied data.

  The DCT / IDCT processing unit 313 receives the

  difference data from the difference generator

  310 via the selector bus SB 2.

  The processing unit 313 performs a transaction operation.

  discrete cosine formation on the received data, and data representative of the result of the operation are applied to the quantizer 314 via the selector bus SB 3 The quantizer 314 quantizes the applied data with reference to the memory of parameters 344 via the SB selector bus 5 The data representative of the quantization result are applied to the code data memory 343 via the selector bus SB 4,

  and they are recorded in the latter.

  (5) Pipeline Processing (Figs. 26) 29) Fig. 26 is a time chart showing the pipeline processing for coding in the pixel processing unit 31 which is shown in Fig. 19 Referring to Fig. 26, note that in the operating period A, write data for the image memory 331 is transferred by the internal pixel bus IPB 2 In the operating period B, write data for the image memory 332 are transferred by the internal pixel bus IPB 2 In the operating period C, write data for the image memory 333 is transferred by the data bus.

internal pixel IPB 2.

  In the operating period D, the filter 315 is in operation In the operating period E, the discrete cosine transformation and the quantization are performed by the DCT / IDC processing unit 313 and the quantizer 314 In the operating period F , inverse quantization and inverse discrete cosine transformation, as well as decoding, are performed by the processing unit 313, the quantizer

314 and the picture decoder 310.

  In the operating period G, the read operation in the image memory 335 is performed in

  the operating period H, the combined operations

  range / level and output are performed by the

  code data bus interface circuit 317.

  The processes that are represented in the figure

  26 are successively completed macro-block by macro-

  block More precisely, although the image data processing of a single macroblock is shown in FIG. 26, a pipeline processing is performed for a certain number of macroblocks.

  pipeline processing for a set of macroblocks.

  Fig. 27 is a time chart showing the pipeline processing in intra-frame prediction. Referring to Fig. 27, it is noted that the suffix O designates the data processing of the 0-th macro-block, and

  the suffix 1 designates the processing of the first macroblock.

  Figure 28 is a time chart showing

  pipeline processing in the case of the single prediction

  directional Figure 29 is a temporal diagram

  showing pipeline processing in the case of prediction

  As can be seen in FIGS. 27 to 29, the data processing for a set of macroblocks is performed under the control of the pipeline processing in the pixel processing unit 3, and the data processing can be performed. accomplished effectively in connection with the processing in the pixel processing unit 3 In other words, there is obtained a pixel processing unit which allows discrete cosine transformation

  and efficient and fast quantification.

  (6) Pixel processing unit 33 Fig. 93 is a block diagram showing yet another example of the processing unit of

  pixels The pixel processing unit 33 which is

  93 may be used for the pixel processing unit which is represented for example on

  Figures 83 to 89 and Figure 91.

  Referring to Fig. 93, it is noted that the pixel processing unit 33 differs from the pixel processing unit 31 shown in Fig. 18 in that it comprises two sets of bus interface circuits. 318a and 318b except for this point, it is identical to the pixel processing unit 31 shown in FIG. 18 Therefore, the corresponding parts are designated by the same symbols of

  reference and their description is not repeated.

  Fig. 94 is a more detailed block diagram of the pixel processing unit 33 shown in Fig. 93 Referring to Fig. 94, it is noted that each of the IPB 2a and IPB 2b pixel buses has

  a bus width of 32 bits and is connected respectively

  to dedicated pixel bus interface circuits

  318a and 318b and to image memories 331 to 333 and 335.

  With the exception of these points, it is identical to the pixel processing unit 31 which is shown in FIG. 19. Consequently, the corresponding parts are designated by the same reference symbols and their

description is not repeated.

  The operation of the processing unit 33 will now be described. Referring to FIG. 94, the coding will be described by way of example of operation.

  a moving picture in accordance with the MPEG standard.

  In the MPEG standard, the prediction in

  before, backward prediction and bidirectional prediction

  and the prediction data must be transferred from the outside according to the prediction type. The data transfer for the prediction is performed via the pixel bus interface circuit 318a or 318b. image to be coded are also transferred via the pixel bus interface circuit 318a or 318b Image compression is accomplished in the filter 325, the DCT / IDCT processing unit 313, the quantizer 314 and the difference generator and picture decoder 310, and the data is provided via the code data bus interface circuit 317. On the other hand, the picture which is decoded locally in the picture. pixel processing unit 33 is transferred to external units separated by pixel interface circuits 318a and 318b The first locally decoded data that is transferred is used as data The other locally decoded data that is transferred is used as predicted image data for the motion prediction unit 47 shown in FIG.

  processing of the next image interval.

  As described above, the pixel processing unit 33 shown in Fig. 94 permits the transfer of locally decoded image data to a set of external units simultaneously, and also allows the transfer of decoded picture data locally to a set of external units simultaneously. transferring predicted image data from one port, while reference image data is transferred from the motion prediction unit to the local memory by the other port The image transfer port predicted is not

  limited to one, but the predicted image can be transferred

  Therefore, one can easily change the structure of the system and the method of

data transfer.

  Fig. 95 is a block diagram showing another example of the pixel processing unit 33 shown in Fig. 93. The processing unit of FIG.

  pixels 33 which is shown in Figure 95 may also

  be used for the pixel processing unit

  which is shown in Figures 83 to 89 and 91.

  Referring to Figure 95, it is noted that compared to the pixel processing unit 33 which

  shown in FIG. 94, in the treatment unit

  The pixel bus 33 to the pixel bus IPB 2 is connected to two pixel bus interface circuits 318a and 318b, and an internal bus is used in common for the pixel data transfer. points it is identical to the pixel processing unit 33 which is

  shown in Figure 94 The description is not

not repeated.

  The operation of the pixel processing unit 33 will be described in the following. Referring to Fig. 95, it is noted that the IPB internal pixel bus 2 is used in common.

  decoded locally must be transferred simultaneously

  Natively to two pixel bus interface circuits 318a and 318b, an operation similar to that of the pixel processing unit 33 shown in Fig. 94 is accomplished. In the structure described above, the pixel processing unit 33a can simultaneously transfer data that are locally decoded to a plurality of external units. In addition, while reference image data is transferred from the local memory. to the motion prediction unit, data can be transferred to the pixel processing unit 35 through another port. In addition, since the IPB pixel bus 2 is used in common, it is possible to reduce the number of pixels. circuit area, and this configuration is therefore suitable for obtaining a degree

higher integration.

  4 Variable length processor Two system structures are proposed in the following, and processors will be described to realize

respective system structures.

  (1) First system structure (Figs. 30a) Fig. 30 is a block diagram showing a first system structure for variable length processing The variable length processor having the system structure shown in the figure can be applied for example to the processor to length

  variable 12 which is shown in FIG.

  Referring to FIG. 30, it will be noted that the first system structure comprises a table memory 401 for variable length coding, a table memory 402 for variable length decoding, a code train input memory. variable length 403, a variable length code stream output memory 404, an input memory 405 for data to be encoded, and an output memory 406 for data to be encoded.

  variable length processor 121 is connected to the memory

  res 401 to 406 via a BU bus line.

  Figure 31 is a flowchart of the coding to

  variable length in the first system structure.

  Processes for variable length coding will be described with reference to Fig. 31. In step 431, data to be coded to which the conversion is applied are applied from the input memory 405 for the data to be coded to a memory. internal to the variable length processor 121 The data to be encoded is defined here by the

  combination of "BEACH" and "LEVEL" In the description

  following, the data to be encoded will be represented by (RN, LV) The applied data to be encoded is transmitted to the address generator (not shown) in the variable length processor 121, and a variable length code and its code length are obtained by reference to the

  table memory 411 for variable length coding.

  The variable length code and the code length are stored in the internal memory in the processor.

variable length 121.

  In step 433, it is determined whether or not the variable length code that is obtained is a code change code (ESCAPE) When a code change code is obtained, a fixed length code is generated at the same time. step 434 by coupling the code change code and the data (RN, LV) After the generation of the fixed length code, the sequence proceeds to step 435 On the other hand, if the code change code, c ' that is, the code "000001" is not obtained in step 433, the sequence

go to step 435.

  In step 435, a variable length code stream is generated by coupling variable length code data. After generating the variable length code stream, the variable length code stream

is issued at step 436.

  Fig. 32 is a flowchart of decoding at

  variable length in the first system structure.

  We will describe treatments for decoding at length

  variable with reference to Figure 32.

  First, in step 441, a variable length code train is applied by the variable length code train input memory 403, shown in FIG. 30, to the variable length processor 121. variable length 121 extract code

  at variable length of head at step 442

  based on the code length of the immediately preceding variable length code, the head of the following variable length code is recognized, and 14-bit data, i.e., the maximum code length of the code variable length, are extracted from the head of the

next variable length code.

  Then, in step 443, a variable length code and the code length, i.e. the data (RN, LV), are obtained by reference to the table memory 402, for the decoding More precisely , 14-bit data, i.e. the maximum length of the variable length code, starting from the head of the resulting variable length code, are applied to an address generator, not shown, and a signal d address for reference to table memory 402 for decoding, is generated by the address generator Using the address signal, reference is made to table memory 402 for decoding, whereby we obtain the variable length code and its

code length.

  In step 444, it is determined whether the code change code '0000001' is obtained or not. If the code change code is obtained in step 445, 16 bits of data following the code change code

  "000001" are extracted for the decoded data (RN, LV).

  After the operation of step 445, the sequence proceeds to step 446 If the code change code is not

  obtained in step 444, the sequence proceeds to step 446.

  At step 446, the decoded data (RN, LV)

are issued.

  We will now describe the record structure

  data for data stored in table memory 401 for variable length coding and data stored in table memory 402 for variable length decoding, which are represented on

  Figure 30 Figure 33 shows the record structure

  Data from table memory 401 for variable length coding As can be seen in Fig. 33, table memory 401 for variable length coding provides VC registered variable length coding and CL code length. by reference to the data (RN, LV) The range data RN has a length of 6 bits The LV level data has a length of 10 bits The variable length code has a length of 14 bits The code length data CL have been a length

of 4 bits.

  Figure 34 shows the record structure

  table 402 memory data for the deco-

  As can be seen in Fig. 34, table memory 402 for variable length decoding provides the LV level data, the range data RN, and the code length data CL, with reference to FIG. variable length code VC The data

  CL code lengths are 4 bits in length.

  The VC input data that is used to refer to the table memory 402 for variable length decoding has a length, in bits, that is equal

  at the maximum code length of the variable length code

  Therefore, when there is a code that is shorter than the maximum code length in the bits

  of the VC input data, the result of the deco-

  For example, the same data 416 and 418 would be obtained regardless of the input data 415 and 417 shown in FIG. 34 which are used for the reference. to the

table memory 402.

  A method of generating the variable length code train will now be described.

  is a flow chart that shows the process for gener-

  Variable length code train generation It is assumed that six registers 421 to 426 are prepared to generate a variable length code train. It is also assumed that the variable length processor has a data processing width of N bits. the

  registers 421 to 426 each have a width of N bits.

  Referring to Fig. 35, it is assumed that register 421 contains a variable length code VC 1 and that register 422 contains the code length k of variable length code VC 1. It is assumed that register 523 contains a code to variable length VC 2 and that the register 424 contains the code length j of the variable length code VC 2 It is also assumed that the register 425 contains a variable length code VC 3 and that the register 426 contains the code length m of the code

variable length VC 3.

  First, the variable length code VC 1 that is contained in the register 421 is applied to the

  register 426 Register 426 records bits corresponding to

  In other words, the register 426 contains the variable length code VC 1 of k bits, starting from the highest-order bit (or MSB). bit of highest weight. In step 427, the code length j of the variable length code VC 2 is compared with (nk) If j C (nk), the variable length code VC 2 which is contained in the register 423 is applied to the register 426 The register 426 contains the variable length code VC 2 after the variable length code VC 1. An operation is performed in the register 426 by shifting the variable length code VC 2 from k bits to the least significant bit (LSB) side. , and then by accumulating corresponding bits of the variable length codes VC 1 and VC 2, or by performing an OR operation between these bits. As a result, the register 86 then contains coupled (k + j) bit data, that is to say a string of codes at length

variable (VC 1 + VC 2).

  At this stage, there is still room for (n-k-j) bits in register 426, and hence register 426 is then used to hold the code to

variable length VC 3.

  In step 427, when j> (nk), on the variable length code VC 2 in the register 423, only the data corresponding to (nk) bits are contained in the register 426 More precisely, the variable length code VC 2 is shifted by k bits and an accumulation or OR operation is performed between the variable length codes VC 1 and VC 2. As a result, the register 426 is filled with k bits of the variable length code VC 1 and part of the variable length code VC 2 which includes

(n-k) bits.

  At step 428, the data that was introduced

  in the register 426 are issued After the transmission of the data, the variable length code VC 2 having (j + k-n)

  which remains in register 423 is applied to the regis-

  The register 426 contains the applied data, i.e. the remaining bits of the variable length code VC 2, in order from the most significant bit side. In this way, the register 426 is filled by

  variable length codes that are applied successively

  sily, and N data bits that have been input are successively output as the variable length code train The variable length code train is segmented by repetitively performing a data shift, a logic operation, a the code length of the variable length code and a determination,

  as in the processes described above, for the gen-

  ration of the variable length code train.

  (2) Variable length processor (dedicated circuit: Fig. 36) Fig. 36 is a block diagram showing a first example of the variable length processor Referring to Fig. 36, it is noted that the variable length processor 120 includes a register address 451, a read-only memory 452 and an output processing circuit 453. These internal circuits 451, 452 and 453 are

  constituted by specialized circuits.

  (3) Variable length processor (digital signal processor: Figure 37) Figure 37 is a block diagram showing a second example of the variable length processor The variable length processor 123 is constituted by a digital signal processor Referring to FIG. 37 shows that the variable length processor 123 comprises an external interface circuit 461, an arithmetic and logic unit (UAL) 462, an offset circuit 463, a memory 464, an instruction memory 465 and a

control circuit 466.

  (4) Variable length processor (microprocessors)

  Figure 38 is a block diagram showing a third example of the variable length processor The variable length processor 124 is constituted by a universal microprocessor Referring to Figure 38, it is noted that the variable length processor 124 comprises an execution unit (EU) 471 which comprises a group of registers 473; a bus interface unit 472 which includes a repositioning register group 474;

  an arithmetic and logical unit 475; a register of indi-

  476; a bus interface unit 477; an instruction queue 478; and a control circuit /

synchronization 479.

  The variable length processors 122, 123 and 124 which are respectively shown in Figs. 36, 37 and 38 all have the first system structure shown in Fig. 30, and the processes of the first system structure, described above. above, are accomplished. (5) Second system structure (Fig. 39) Fig. 39 is a block diagram showing a second system structure for processing

  variable length The system structure that is

  shown in FIG. 39 is implemented for example in the image compression / decompression apparatus which

is shown in Figure 1.

  Referring to Fig. 39, it is noted that the working memory 7 comprises a table memory 481 for variable length coding, and a memory of

  table 482 for variable length decoding

  481 and 482 are connected to the processor at

  variable length 125 by buses 491 and 492.

  The buffer memory 6 comprises an input memory 483 for a variable length code train, an output memory 484 for a code train to be used.

  variable length, an input memory 485 for data

  to be encoded, and an output memory 486 for data

  The input memory 483 and the output memory 484 for code streams are connected to the variable length processor 125 via buses 493 and 495. The input memory and the memory

  output for the code trains are connected to the process

  variable length 125 and the interface circuit

of host 1 by a bus 494.

  The input memory 485 for the data to be encoded and the output memory 486 for the data to be encoded are connected to the variable length processor 125 via buses 496 and 498. The input memory 485 and the output memory 486 are connected to the variable length processor 125 and the processing unit of

pixels 3 by bus 497.

  (6) Variable length processor (Figure 40)

  Figure 40 is a block diagram of the process

  variable length 125 which is represented on the

  FIG. 39 The variable length processor 125 represents

  40 is therefore applicable for example to the variable length processor 120 which is shown in FIG.

Figure 9.

  Referring to Fig. 40, it is noted that the variable length processor 125 comprises a control unit 501, an address generator 502, a circuit

  external interface 503, a data processing unit

  504, a variable-length code train generation / separation circuit 505, an external interface circuit 506, external interface circuits 507 and a data memory 508. These internal circuits 501 to 508 are connected by a first one. On the other hand, the external interface circuit 503 and the

  generation / separation of variable length code trains

  505 are connected by a second internal bus 510.

  The external interface circuit 503 is connected to a main port 17 shown in Fig. 9 by buses 491 and 492. The external interface circuit 506 is connected to the code data port 20 shown in FIG.

  FIG. 9 by buses 493, 494 and 495.

  (i) Address Generator (Figure 41)

  Figure 41 is a block diagram of the gen-

  address editor 502 shown in FIG. 40.

  Referring to Fig. 41, it will be noted that the address generator 502 includes a positive limit value register 502, a negative limit register 521, a PE mode register 522, a page register 523, datalogue registers address 524 and 525, a code change decoder 526, a code change encoder 527, a code change register 528, a data register 529, a selector circuit 530, a limiter circuit 531, a priority encoder 532, an offset circuit 533, an external address register 534, pipeline registers 561, 562, 563 and an OR circuit (circuit for generating a logic sum) 564 Registers 520 to 525 are connected to a first internal bus The selector 530 is connected to first and second internal buses 509 and 510. The data register 529 and the external address register 534 are connected to the external interface circuit.

  503 which is shown in Figure 40.

  Fig. 42 is a flowchart of the variable length coding in the address generator 502 shown in Fig. 41.

  detail the treatments that are carried out in the general

  address 502, and it will be described below only

basic operation.

  Referring to FIG. 42, it is noted that in step 601 specific data are placed in the

registers 520 to 523 which are shown in FIG.

  In step 602, data to be encoded (RN, LV) is applied.

  address register 525 The data to be coded (RN,

  LV) have a total of 16 bits, of which 10 bits

  The first step is to define the level data LV and the lower 6 bits define the range data RN. After step 602, the processes of steps 603 to 605 and 606 to

607 are performed in parallel.

  In step 603, the data contained in the address register 525 is applied to the limiting circuit 531. The limiting circuit 531 limits the 10 bits.

  applied data, that is, the data

  LV level, within a range that is specified by the positive limit register 520 and the negative limit register 521 Because of the limitation, data to be coded having a total of 12 bits is obtained. ie 6 bits of LV level data and 6 bits of

RN range data.

  The data to be coded with 12 bits is

  to the OR circuit 564, an OR operation is performed

  between the applied data and the data that

  The data is generated from the page register 523, and 20-bit coupled data is generated (step 604). The generated data is recorded in the external address register 534 (step 605). At step 606, the data to be encoded in the register 525 is applied to the code change encoder 527 and the latter generates a fixed length code. More precisely, a process is executed to generate a code. fixed length when the data to be encoded is encoded as a fixed length code In step 607, the fixed length code that is generated is stored in the change register

of code 528.

  Fig. 43 is a variable length decoding flowchart in the address generator 502 shown in Fig. 41.

  basis for variable length decoding.

  Referring to Fig. 43, it is noted that in step 611 determined data is placed in the registers 520 and 523. At step 512, a variable length code train to be decoded is applied to the address register. Register 524 retains 22 bits of the variable length code stream applied, starting from the first bit, in order from the most significant bit side. After step 512, the processes of steps 613 through 616 and steps 617 and 618 are performed in parallel. In step 613, the data held in the address register 524, i.e. the variable length code stream, is applied to the priority encoder 532. The priority encoder 532 calculates the number SN of O "continuous, from the most significant bit of the data

applied.

  In step 614, the data contained in the address register 524 is applied to the shift circuit 533. Under the effect of the number SN which is calculated in the step 61, the shift circuit 533 extracts 6 bits of data which are below the (SN + 1) -th bit from the most significant bit of the applied data.

  extracted are applied to the OR circuit 564.

  In step 615, the OR circuit 564 provides a logical sum and 20 bits of data are generated. The data that is generated is recorded in the

  external address register 534 (step 616).

  On the other hand, at step 617, the data held by

  in the address register 524 are applied to the

  code change decoder 526 The currency decoder

  coding 526 performs a decoding, concerning the fact that the applied data consists of a code

  fixed length, using the code change code.

  The decoded data is recorded in the register of

  code change 528 (step 618).

  (ii) Variable length code train generation / separation circuit (Fig. 44) Fig. 44 is a block diagram of the variable length code train generation / separation circuit 505 shown in Fig. 40 Referring in figure 44, we note that the circuit of

  generation / separation of variable length code trains

  505 comprises a bus register 536, a circular shift circuit (or BSFT) 537, an adder 538, a code length register 539, a code output register 540, a code input register 541, PEPS circuits 542 and 543 and a control unit 544 The register

  bus 536 is connected to the first internal bus 509.

  The adder 538 is connected to the second internal bus 510.

  PEPS circuits 502 and 503 are connected to an external interface circuit 506 (to be described later) shown in FIG. 47 through lines

signal 42a to 43c.

  Fig. 45 is a flowchart of the variable length coding in the generation / separation circuit

  variable-length code train 505 which is

  Figure 44 The basic operation of variable length coding will be described with reference to FIG.

figure 45.

  In step 621, a variable length code VC is applied to the bus register 536 via the internal bus 509. The code length data CL of the

  variable length code VC are applied to the addition-

  neur 538 via the second internal bus 510.

  At step 622, the circular shift circuit 537 couples an old variable length code VC ', which has already been inputted, with the new variable length code VC being applied at the present time, and it generates a train In step 623, the adder 538 adds the code length CL of the new variable length code to the sum of

  lengths of CLS code which is the accumulated sum.

  In step 624, it is determined whether or not the sum of CLS code lengths exceeds 8 bits if CLS> 8,

the sequence goes to step 625.

  In step 625, 8 data bits from the first bit of the variable length code train VCT are applied to the FIFO circuit 542 and are recorded therein. In step 626, a new code length is

  calculated by subtraction, that is, CLS = CLS 8.

  After step 626, the sequence returns to step 624. In step 624, if CLS <8, this operation of

coding is complete.

  Fig. 46 is a flowchart of variable length decoding in the generation / separation circuit

  variable-length code train 505 which is

  shown in Figure 44 Referring to Figure 46,

  notes that at step 631 a string of codes with varying lengths

  VCT is applied to the first internal bus 509 In step 632, the code length CL of the first variable length code VC which is included in the variable length code string VCT is applied to the adder 538 by the intermediate of the second internal bus 510 In step 633, the adder 538 adds the new length of

  CL code to the sum of the old lengths of CLS code.

  In step 634, it is determined whether or not the sum of CLS code lengths exceeds 8 bits if CLS> 8,

the sequence proceeds to step 635.

  In step 635, a data word is applied from the variable length code stream input memory 483, and this word is coupled to the variable length code train present in step 636, the 8 first bits of data are removed from the variable length code stream which is coupled to step 637, a new sum

  lengths of CLS code is obtained by performing the operation

  ration CLS = CLS 8 After step 637, the process

returns to step 634.

  At step 634, when CLS <8, the process of

decoding is complete.

  (iii) External Interface Circuit 606 (Fig. 47) Fig. 47 is a block diagram of the external interface circuit 506 shown in Fig. With reference to Fig. 47, it is noted that the external interface circuit 506 comprises a control unit 505 having the direct memory access function (DMA), read access counters 546 and 549, write access counters 547 and 548, subtracters 565 and

  566, comparators 550 and 558, gen-

  551 to 554, a write data register 556, a read data register 557, and

a selector 555.

  The control unit 545 is connected to the circuits

  PEPS 542 and 543 shown in FIG. 44 by

  via signal lines 42b, 42c, 43b and 43c.

  The register 556 is connected to the PEPS circuit 542 represented

  44 is connected to the PEPS circuit 543 shown in Fig. 44 by the signal line 43a. The counters 546 and 547 are connected to the code train input memory. variable length 438 and the variable length code train output memory 484, shown

  in Fig. 39, by the signal line 493.

  548 and 549 are connected to the variable length code stream input memory 438, the variable length code stream output memory 484 and the host interface circuit via the The selector 555 is connected to the variable length code train input memory 483 and the variable length code train output memory 484, shown in FIG. 39, by the signal line.

495.

  The counter 546 counts the number of read accesses to the variable length code stream input memory 483 shown in Fig. 39. The counter 547 counts the number of write accesses to the output memory of Variable length code train 484 shown in Fig. 39 Counter 548 counts the number of write accesses to the variable length code train input memory 483 from other circuits Counter 549 counts the number of read accesses to the train output memory of

  variable length codes 484 from other circuits.

  Indicator register 551 produces an indica-

  solid State Indicator that indicates the full state of the variable-length code train input memory 483, and retains the flag. The register 552 generates and maintains an empty status flag which indicates the blank state. Variable length code train input memory 483 Register 553 generates and maintains a solid state flag which indicates the full state of the memory of the memory.

  Variable length code train output 484

  554 produces and maintains an empty status flag which indicates the empty state of the train output memory.

variable length codes 484.

  The comparator 550 produces a full status indicator FF 1 which indicates the full state of the input memory

  variable-length code train 483, or an indica-

  empty state meter EF 1 which indicates the empty state of this memory The comparator 558 produces a solid state flag FF 2 which indicates the full state of the variable length code stream output memory 84, or a indicator

  Empty state counter EF 2 which indicates the empty state of this memory.

  Fig. 48 is a flowchart of the variable length coding in the external interface circuit 506

  which is shown in Figure 47 will describe the function

  basic coding of variable length

referring to Figure 48.

  In step 641, it is detected whether the variable-length code stream output memory 484 is empty or not. In other words, it is detected whether or not it exists.

  an empty status indicator EF 2 which is provided by the comparison

  558 If the empty status indicator EF 2 is not detected, the sequence proceeds to step 642 If the indicator

  blank state EF 2 is detected, the process is complete.

  At step 642, it is detected whether the variable-length code train output memory 484 is

  full or not In other words, it is detected whether the

  controller 558 or not provides a full status flag FF 2.

  If the full status flag FF 2 is not detected, the sequence proceeds to step 643 When the status indicator

  full FF 2 is detected, the process is complete.

  In step 643, a word of the data stored in the variable length code stream output memory 484 is read and stored in the external variable length code stream output memory. At step 644, the contents of the write access counter 547 is incremented After step 644, the sequence returns to

step 641.

  Fig. 49 is a variable length decoding flowchart in the external interface circuit 506 shown in Fig. 47. Referring to Fig. 49, it is noted that in step 5651 it is detected whether the memory of Variable length code train input 483 is full or not In other words, it is detected whether or not the comparator 550 provides a full status flag FF 1 If the full status flag FF 1 is not detected, the sequence goes to step 652 If the status indicator

  full FF 1 is detected, the process is complete.

  At step 652, it is detected whether the input memory

  Variable length code train 483 is empty or not.

  In other words, it is detected whether the comparator 550

  produced or not an empty status indicator EF 1 If the indica-

  Empty state meter EF 1 is not detected, the sequence proceeds to step 653 If the empty state flag EFI is

  detected, the process is complete.

  In step 653, a word of the data recorded in the external variable length code stream input memory is read and stored in the variable length code stream input memory 483. At step 654, the read access counter 446 for external variable length code train input memory is incremented After step 654, the sequence

returns to step 651.

  (iv) Detailed description of the coding / decoding

  variable length Variable length coding / decoding will now be described in more detail in the variable length processor 125 shown in FIG. 39. FIG. 50 is a variable length code table which is used in processes which are performed in the variable length processor 125 which is shown in Fig. 39 Referring to Fig. 50, it is noted that four columns on the left side of the variable length code table correspond to the

  variable length code table in accordance with the

  In particular, the range data (zero span length) RN, the level (factor) data LV, the code length CL, and the variable length code VC that are specified in Recommendation H 261 are indicated in the four columns on the side

  On the other hand, three columns on the right side represent

  sense a variable length code table which is grouped More precisely, in accordance with the number of continuous 'O' from the first bit of the variable length code VC, the variable length code VC and the code length CL are divided into one total of nine groups GRO to GR 8. For example, the group GRO contains a variable length code VC whose first bit is not "O" The group GR 1 contains a variable length code VC in which only the first bit is "O" The group GR 2 contains a variable length code VC in which the first two bits are "'" Similarly, the group GR 8 contains a variable length code VC which comprises 8 "QO from the first bit variable length code VC. The grouped variable length codes VC and the lengths of code CL are used in the operations performed in the variable length processor 125, which is

will describe later.

  To begin, we will describe the variable length coding Basically, the variable length coding is performed in accordance with the flowchart shown in Figure 31, which has already been described First, data to be coded, that is, say data (RN, LV) are

  entered in the data memory 538 in the process

  variable 40 shown in Fig. 40, from input memory 425 for data to be encoded, which is shown in Fig. 39 Input data is applied to address generator 502 which generates a memory address In parallel with the generation of the table address, the code change decoder 526 shown in FIG. 41 generates a code for the variable length coding conversion.

  fixed length using a code change code.

  The fixed length code that is generated is applied to the code change register 528 and is stored therein.

  detailed operation of the address generator 502.

  Using the table address that is generated by the address generator 502, reference is made to the variable length coding table memory 481 and reads the variable length code VC, the code length CL

  and the ESF code change indicator that are registered.

  The variable length code VC and the code length CL are applied to the data register 529 shown in Fig. 41 and are stored in the latter. After the end of the access to the table memory 481 for variable length coding, the data of the code change register 528 or the data register 529 are provided to the generation / separation circuit.

  of variable length codes 505 The selection is made

  killed by the selector circuit 530 More precisely, among the data that are kept in the two registers

  528 and 529, the selector 530 selectively transmits the data

  from one of the registers, depending on the bit of

higher weight (MSB).

  Specifically, as shown in Fig. 51, table memory 481 for variable length coding retains an ESF code change flag which indicates whether the data to be encoded is within the applicable range of the code change code. , with regard to the most significant bit Therefore,

  if the most significant bit of the data that is applied

  data register 529, that is to say, the indica-

  With the ESF, indicating the application of the code change code, the selector 530 selectively transmits the data that has been stored in the data register 529. As a result, referring only to the table memory 481 for coding to variable length, we can determine

  whether or not it is necessary to apply the exchange code

  code to the data to be encoded, and a program-based determination is not necessary for this purpose. In addition, in the address generator 502 shown in Fig. 41, access to the memory of

  table 481 for variable length coding and general

  Fixed-length code using the code change code can be performed in parallel, i.e. simultaneously. Therefore, an increase in the processing time resulting from access to the table memory can be avoided. 481 for coding at

variable length.

  The variable length code VC which is obtained by reference to the table memory 481 for the coding to

  variable length is transferred to the circuit of genera-

  Variable length code train 505 is separated by means of the first internal bus 509 shown in Fig. 41. On the other hand, its code length CL is transferred to the code train generation / separation circuit. variable-length code bus 505 by the second internal bus 510 The variable-length code train generating / separating circuit 505 generates a variable-length code train VCT from the variable length code VC that is applied and its code length. CL The generation operation of the variable length code train will be described later. The variable length code train VCT generated is applied to the variable length code train output memory 484 shown in FIG. intermediate of the external interface circuit 506

  this way, the variable length coding is completed.

  Variable length decoding will now be described. First, a variable length code train is applied to the variable length code train generation / separation circuit 505 from the variable length code train input memory 483. shown in Fig. 39 through the external interface circuit 506 The variable length code train generating / separating circuit 505 performs the segmentation of a variable length code to which the decoding relates, from the variable length code string applied, and shifts the bits of the variable length code to the side of the most significant bit The offset variable length code is transferred to the address generator 502 via the first internal bus 509 We will present later

  detailed description of the generation / separation circuit

  of variable length code train 505.

  Address generator 502 generates a table address for a reference to table memory 482 for variable length decoding, which is shown in Fig. 39, as a result of the variable length code being applied. of table that is generated is applied to the table memory 482 for the decoding to

  variable length, through the circuit of inter-

  As a result, the decoded variable length code, the code length data and the ESF code change indicator are stored in the data register 529 shown in FIG. 41 at this time in parallel. with this process, variable length code is applied to the code change code encoder, and decoding of the fixed length code using the code change code is accomplished Data indicating the result is applied to the code change register 528 and they are kept in the latter. As in the variable length coding, the table memory 482 for the variable decoding contains an ESF code changing flag. Therefore, at the end of the access to the table memory 482, the code change flag ESF is contained in the most significant bit (MSB) of the data register 529 Under the effect of the code change flag ESF, the data that is contained in the code change register 528 or that which is contained in the data register 529 is selectively transmitted via the selector 530 The transmitted data is applied to the data memory 508 shown in FIG.

40.

  On the other hand, the code length data is transferred to the generation / separation circuit

  of variable length code train 505 through

  of the second internal bus 510 The circuit of genera-

  Variable length code train separation / separation 505 performs the segmentation of the next variable length code using the applied code length data. The data indicating the result of the decoding, which is applied to the data memory 508, are transmitted to the output memory 486 for the data to be encoded, via the external interface circuit 506 Variable length decoding is thus completed. The operation of the address generating circuit 502 will now be described in greater detail.

  which is shown in Figure 41.

  Fig. 52 shows a format of the data to be coded in variable length coding. Referring to Fig. 52, it is noted that the data to be encoded comprises 10-bit LV level data and 6-bit NR range data. to encode so have a total length

16 bits.

  Turning now to the four columns on the left side of the variable length code table shown in Figure 50, it is noted that LV level data (which is defined as absolute value data in Recommendation H 261), they have a

  value that is in the range of -15 to +15.

  In accordance with Recommendation H 261, data outside this range is represented in a code change code (ESCAPE) This means that the number of bits required to represent the LV level data is 5 bits , and that a combination of range data and level data can be represented by a total of 11 bits, in association with

RN level data.

  LV level data that is not inferior

  than +15 and not greater than -15 are respectively limited to +16 and -16, and therefore addresses with +16 and -16 level data

  designate code change codes With this

  a total of 11 bits becomes sufficient for the address to access the table memory for the variable length coding, and therefore the table memory for the variable length coding can be realized in

  the range of 2 K words of address space.

  In this manner, the address generator 502 can perform address generation by working with a single channel. Therefore, the limiter 531 shown in FIG. 41 limits in the range of +16 to -16 bits of data. The result is that a positive value + 16 is set in the positive limit value register 520, while a negative value -16 is set in the control register. Negative limit value 521 shown in Fig. 41 Limiter 531 performs the limiting operation mentioned above with reference to the data stored in

registers 520 and 521.

  Due to the limitation of data from

  level, we obtain a total of 11 bits of combined data.

  and using this data an address is generated to refer to the table memory 481 for the

variable length coding.

  The decoding will now be described in the address generation circuit 502 which is shown on

Figure 41.

  As shown in the variable length code table of Fig. 50, variable length codes VC are divided into a total of nine groups GRO to GR 8. In each group, 6 bits are required to define each variable length code. , to make a decoding table for the variable length code, 4 bits to designate a total of 9 groups and 6 bits to designate a code in each group are required Specifically, a total of 10 bits is required as an address The address generation circuit 502 shown in FIG. 41 can generate 10 table address bits by a single channel. More specifically, the variable length code to be decoded is applied to the address generator 524 and is stored therein. The data that is held by the address generator 524 is applied to the priority encoder 532, and the number of "O" continuous from

  first bit of the applied data is counted accordingly.

  determine which of the groups GRO to GR 8 represents

  shown in Figure 50 to which the data belong

  The number of the group is represented by 4 data bits On the other hand, 6 data bits that follow the continuous "O" are segmented.

  4-bit group and the 6-bit segmented data

  kill a table address of a total of 10 bits, and the table address is applied to the address register

  external 534 and it is kept in the latter.

  In this way, using the address generator 502 shown in Fig. 41, the address space for the table memory 481 for variable length coding, and for the table memory 482 can be reduced for variable length decoding, and moreover

  these processes can be carried out through a series of

  rations. The encoding operation will now be described in the variable length code train generation / separation circuit 505 shown in FIG.

  44 The code output register 540 includes registers

  40 to 40 e, each comprising 8 bits In the initial state, the code output register 540, the code length register 539 and the PEPS circuit 542 each contain data "O". 40-bit circular offset 537 (40b) shifts the input data to the right side, according to the code length that is stored in the

code length 539.

  For example, "001010" data is applied to the bus register 536 as the first coded variable length code, while code length "6" is applied to a 5-bit adder 538 at this stage, because the value in the length register

  code 539 is "O", the data contained in the regis-

  Bus 536 traverses the circular shift circuit 537 without change and is applied to the code length register 539. In the adder 538, the input data "6" is added to the "O" data present in the register. code length 539, and the resulting "6" data is described in the

code length 539.

  Then, for a coded variable length code

  following, "00001000" data is applied to the regis-

  536, and a code length "8" is applied to the adder 538 Since the data in the code length register 539 is equal to "6", the data of the bus register 536 is shifted by 6 bits to the right side by the circular shift circuit 537, and the shifted data is applied to the code length register 539 Therefore, the data that is stored in the code length register 539 includes the first variable length code in the first 6 bits, and they include the length code

  following variable at the 7th bit and following bits.

  The adder 38 adds the input data "8" to the data "6" in the code length register 539, and applies the result of the addition, i.e., "14" to the data register. code length 539. At this stage, since the register 40a in the code output register 540 is filled with the variable length code "00101000", the data present in the data register 40a is applied to the circuit PEPS 542 Next, the data present in the register 40 b

  are transferred to register 40. In addition,

  In the register 40c are transferred to the register 40b Similar operations are repeated and the data of the last register 40e are transferred to the register 40d After this transfer process, the code length of the data applied to the FIFO circuit 542, i.e. "8", is subtracted from the data in the code length register 539 More specifically, in this example, because the register 539 contains the data "14", the result of the subtraction will be "6"

(= 14 8).

  As a result, the data in the code length register 539 now indicates the number of

  bits of the variable length code "0011000" which is

  stored in the register 40a, and when the next variable length code is inputted, the input variable length code is shifted to the right side of the number of bits of the variable length code which is registered in the register 40 Thus, following the variable length code which has already been registered, the following variable length code is recorded in the code output register 40. In this way, using the variable length code and its code length, we can

  generate a string of variable length codes without

  kill a determination by means of software.

  The decoding operation in the variable length code train generation / separation circuit will now be described as the code output register.

  540, the code entry register 541 includes registers

  4 In the initial state, the code input register 541 and the code length register 539 both contain data "0". The circular offset circuit 537 has bits , shifts the input data to the left side,

  over a distance corresponding to the value that is

  naked in the code length register 539.

  First, the first variable length code train is successively introduced into the registers 4a through 4c through the FIFO circuit.

  543 Where a variable length code is to be segmented

  In this case, the data contained in the code input register 541 is applied to the bus register 536 via the circular shift circuit 537 at this point because the data in the code length register 539 is " O ", the data present in

  the code entry register 541 pass through without changing-

  The decoding of the data contained in the bus register 536 results in the data "6" for the corresponding code length, and the length data. The adder 538 adds the input data "6" to the "O" data in the code length register 539, and the "6" data indicating the result is applied to the code register. code length

  539 and they are kept in the latter.

  When the next variable length code is to be segmented, the data present in the code input register 541 is applied to the bus register

  536 through the circular shift circuit 537.

  Since the data in the code length register 539 is "6", the data present in the code input register 541 is shifted 6 bits to the left by the circular shift circuit 537, and the shifted data are applied to the bus register 536. More precisely, following the already decoded variable length code, the following variable length code is obtained in a position shifted to the left side Under the effect of the decoding of the data in the register of 536, data "8" is obtained for their code length, and the code length data is applied to

the adder 538.

  The adder 538 adds the input data 8 "to the data" 6 "in the code length register 539, and applies to the code length register 539 the data" 14 "which indicates the result. The contents of register 41 have been fully decoded, and therefore the data present in the

  register 40b are transferred to the register 40a.

  Then, the data present in register 40c are

  transferred to the register 40 b By repeating

  similar information, the data in the register

  e are finally transferred to the register 40 d.

  The following variable length code train is applied to the empty register 40 e from the FIFO circuit 543. Because the 8-bit decoding has been completed, the data in the code length register 539 is "6". therefore, when the next variable length code is segmented, the next variable length code that follows the already decoded variable length code,

  is obtained in a position shifted to the left side.

  In this way, by using the code length of the variable length code that is decoded, the next variable length code to be decoded can be segmented by being shifted to the left side from the variable length code stream without perform a

determination with software.

  Variable length coding will now be described in the external interface circuit 506 which is

shown in Figure 47.

  Referring to Fig. 47, it is noted that the control unit 545, having a direct memory access function (DMA), controls internal circuits in the external interface circuit 506. The counters 548 and 549 receive a activation signal for access operations (read and write) to the variable length code train input memory 483 and the variable length code train output memory 484 from the circuit Host interface 1, through signal line 494 Therefore, counter 548 counts the number of write accesses that the host computer makes in the variable-length code train input memory. On the other hand, the counter 548 counts the read access number to the variable length decode train input memory 483, from the external interface circuit 506. The counter 547 counts the number of access d writing to the outgoing code train output memory r variable 484 from the circuit

external interface 506.

  The output data of counters 546 and 548

  are applied to subtractor 565 in which a subset

  The data which indicates the result of the subtraction thus represent the number of words of the data recorded in the variable-length code stream input memory 483. The data transmitted by the subtractor 565 is applied to the comparator 550. The comparator 550 receives the data of number of words in the full state of the train input memory of

* codes with variable length 483 On the other hand, the comparison

  The comparator 550 compares the output data of the subtractor 565 with the data that originates from the registers 551 and 552, the data of the number of words indicating the empty state of the variable-length code stream input memory 483. and he produces the

FFI and EFI indicators.

  If the output data of the subtractor 565, i.e. the difference data, is equal to the number of words indicating the full state, which is registered in the register 551, the comparator 550 produces a status indicator On the other hand, if the output data of the subtractor 565 is equal to the number of words indicating the empty state, which is kept in the register 552, the comparator 550 produces the empty state flag EFI. similar, in the variable-length code train output memory 484 which is

  shown in FIG. 39, the operation which is effected

  is the same as in the input memory 483, and the comparator 558 transmits the full status flag FF 2 or

the empty status indicator EF 2.

  The control unit 545 controls the data transfer between the PEPS circuits 542 and 543, the variable length code train output memory 484 and the variable length code train input memory 483, based on the an indicator output signal 42b from PEPS circuit 542 shown in FIG. 44, indicator output signal 43b from PEPS circuit 543, and FF 1, EF 1, FF 2 and EF 2 indicators from comparators 550 and 558 The control of the

  data transfer is performed as follows.

  When variable length coding is effected

  killed, data is transferred between the FIFO circuit 542 and the variable-length code train output memory 484 At this time, in the variable-length code train generation / separation circuit 505, the data transfer is commanded so as not to place the FIFO circuit 542 in the data miss state, i.e. so as to prevent a read operation without the data logging In addition, the data is transferred to avoid excess data in the code train output memory at length

  variable 484, that is to say, to prevent an operation

  in the variable-length code train output memory 484 when valid data

  are already stored in this memory.

  In variable length decoding, data

  The data transfer is transferred between the PEPS circuit 543 and the variable-length code train input memory 483. At this time, the data transfer is controlled so as to avoid an excess of data in the FIFO circuit 543 and to avoid a lack of data. of data in the memory of

  Variable length code train output 484.

  Image Interval Buffer (1) System Structure (Figures 53 and 54) Figure 53 shows a basic structure of an array of memory cells in the image gap buffer. picture interval 51 which is shown in FIG.

  example the structure of Figure 53.

  Referring to Fig. 53, it is noted that the image interval buffer 54 (or 55) comprises a total of 32 memory cell network plans 701 to 732 (or 801 to 832) when an address RA line and a CA column address are applied, a data bit is read (or written) in each of the memory cell arrays 70 1 to 732 For example, when a line address R Al and a column address C Al are applied, 32 bits of data in total are read in the networks of

memory cells 701 to 732.

  In general, 8 bits of data are needed

  Thus, the total of 32 data bits makes it possible to represent four pixels PC 1 to PC 4 (see FIG. 53). In other words, by applying a row address RA and a column address CA , we can manipulate data for four

PC pixels 1 to PC 4.

  Fig. 54 is a block diagram of the image gap buffer. Referring to Fig. 54, it is noted that the image gap buffer 54 (or 55) comprises a control circuit 741 and memory cell networks 701 to 732 (or 801 to 832) In the case of synchronous dynamic random access memories, each of the memory cell arrays 701 to 732 is divided into two blocks BK 1 and BK 2. A sense amplifier 742 and a second one. input / output amplifier-splitter 743 are incorporated in correspondence with each of the

  networks of memory cells 701 to 732.

  Therefore, 32 data bits PD 1 to PD 32 are written and read in the memory cell arrays

701 to 732.

  The control circuit 741 receives an address signal ADR and a control signal Sc, and generates a control signal for accessing the cell networks of

memory 701 to 732.

  (2) An example employing dynamic random access memories (first example: FIG. 55) FIG. 55 shows a system structure of an image interval buffer 54 that uses dynamic random access memories (or DRAMs) Referring in FIG. 55, it is noted that the image interval buffer 54 comprises an array of DRAM memory cells 701 to 732, comprising a total of 32 frames. ADR address from the RAM control unit

  dynamic 740 via an AB address bus.

  The image interval buffer 54 is connected to the pixel data bus PD, and data is received /

  transmitted via the PB pixel data bus.

  The dynamic random access control unit

  742 is incorporated in a control unit of the appa-

  compression / decompression image which is

  shown in Figure 1, as an example.

  The dynamic random access control unit 743 is incorporated into the overall control processor.

  11 which is shown in Figure 9.

  Figure 56 shows a pixel pattern indicating the relationship between data recorded in

  the image interval buffer 54 which is

  shown in Fig. 55, and the pixels on the screen as described above, by applying a row address RA and a column address CA to the interval buffer

  54, 32 bits of data can be accessed.

  In the system structure shown in Figure 55, with a row address and a column address, it is possible to define four

  pixels (eg PCO PC 3) in the horizontal direction

  tale on the SCN screen, as shown in Figure 56.

  Figure 58 shows a pixel configuration

  for the description of the addressing signal by the unit of

  dynamic random access control 740 shown in Fig. 55 Referring to Fig. 58, it is noted that the column address of the interval buffer

  image 54 designates pixels in the horizontal direction

  On the other hand, the line address signal designates pixels in the vertical direction of the SCN screen. In Figure 58, the reference symbol O

represents a pixel.

  The set control processor 11 shown in Fig. 55 produces a line address signal RA and a column address signal CA according to

  to a firmware that is registered in this processor.

  The row and column address signals RA and CA are applied as an address signal ADR to the address bus AB The address signal ADR is applied to the frame buffer 54 by intermediate AB address bus Simultaneously, the dynamic random access memory controller 740 produces a control signal

  for controlling the image interval buffer 54.

  In a data write operation, the set control processor 11 applies data to be recorded in the image slot buffer 54 via the pixel data bus PD in a read operation. data, the ensemble control processor 11 receives data which is recorded in the image interval buffer 54, by

  via the PB pixel data bus.

  Figure 59 is a time chart showing

  a read operation in the inter-

  Fig. 54, under the control of the dynamic random access control unit 740 shown in Fig. 55 Referring to Fig. 59, it is noted that after the application of the line address signal RA 1, the signal

  line / RAS activation key goes low.

  After applying the first column address signal CAI, the column address / CAS enable signal goes low In a read operation, a high level write enable signal / WE is applied Therefore, the recorded data P D1 are read from the memory cell (not shown) which is designated by the address signal R A 1 and C Al.

  PD 1 data, the signal / CAS goes high.

  After the application of the next column address signal CA 2, the signal / CAS goes back to the low level. Therefore, the PD 2 data is read in the memory cell which is designated by the signals.

  address R Ai and CA 2 By repeating similar operations

  PD 1, PD 2, which are designated by the column address signals C A1, CA 2, are successively transmitted by a line which is designated by

the line address signal RA 1.

  Referring to FIG. 58, it is noted that a macroblock 750 is constituted by a total of 64 (= 8 × 8), that is 8 in the horizontal direction and 8 in the vertical direction. As a result, the pixel data in the macro block 750 can be designated by line address signals R A 1 to RA 8 and

  CA 4 and CA 5 column address signals.

  Thus, the set control processor 11 shown in Fig. 5 produces line and column address signals in accordance with a

  recorded program, as follows first-

  After the transmission of the line address signal R A 1, the column address signals CA 4 and CA 5 are transmitted. Accordingly, the first line of pixel data can be accessed in the macro block 750. (For example for a read operation) Next, after the application of the line address signal RA 2, the column address signals CA 4 and CA 5 are successively applied.

  so access the second line of data in the macro-

  block 750 A similar operation is repeated until the

eighth line of the macro-block 750.

  Therefore, to access the image interval buffer 54 for all the pixels in the macro block 750, a total of 8 applications is required

  number of line addresses R Ai to RA 8 and a total of 16 applications

CA column address statements.

  In one example, the application of an RA line address requests 90 ns and two applications of the AC column addresses and the data transfer request ns In this case, the designation of a macro-block requires

1680 ns (= (90 + 120) x 8).

  On the other hand, when a motion vector is to be detected in the motion prediction unit, a macroblock 751 such as that shown in Fig. 58 is required. Specifically, the pixel data that is included in the macro block 751 are designated by row addresses RA 11 to RA 18 and column addresses C A1 to CA 3 Pixel data that is recorded in areas 752 and 753 are not required, and are discarded after being obtained, to access pixel data

in the macro block 751.

  Thus, to access pixel data in the macro block 751, a total of 8 RA line address applications and a total of 24 AC column address applications are required. As a result, a total of

  2160 ns is required for access.

  (3) An example using synchronous dynamic random access memories (second, third and fourth

examples)

  In what follows, we will describe three examples (second, third and fourth examples) using

  synchronous dynamic random access memories (also called

  after "SDRAM") for the image interval buffer. Fig. 60 shows a system structure of the image gap buffer 55 employing SDRAM memories. Referring to Fig. 60, it is noted that the image interval buffer 55 is constituted by SDRAM memories. comprising memory cell arrays 801 to 832 which are divided into a total of 32 planes The set control processor 11 comprises an address generator 804 for generating an ADR address signal for access to the buffer memory The address generator 804 applies a line address signal RA and the column address signal CA, as an address signal ADR, to the frame interval buffer Via the address bus AB The data to which the access relates is applied to the image slot buffer via the pixel data bus PB The set control processor applies a system clock signal 4 sc at g nérateur address 840 for

generate the ADR address signal.

  During operation, the set control processor 11 activates the address generator 840 according to a registered program. Under the effect of the system clock signal 4 fsc, the address generator 840 generates a signal of ADR address for accessing the SDRAM in the image slot buffer The address generator 840 generates a row address signal RA and a column address signal CA of the three

  different ways described below (second, third,

me and fourth examples).

  Fig. 61 is a time chart showing a basic operation (in this example a read operation) of the SDRAM memory. Referring to Fig.

  61, it is noted that the DRAM memory functions under the

  4 rd system clock signal which is applied by the set control processor 11 The line address signal R Ai is admitted under the effect of the signal / RAS downlink transition, and then the signal Column address address C Al is admitted under the effect of the downlink transition of the signal / CAS. Under the effect of the system clock signal 4 Wsc, the address generator 840 successively produces column address signals. C Al CA 8, starting from the column address signal C Al These address signals are applied to the image interval buffer 55 via

AD address bus.

  Therefore, in the data read operation, the stored data PD 1 to PD 8 are read from

  the network of memory cells in the SDRAM memory.

  Specifically, in this example shown in Fig. 61, 8 column address signals are generated, starting from the column address signal C A1, so that 8 data elements PD 1 to PD 8 are read in the line that

  is designated by the line address signal RA 1.

  (i) Second Example (Figures 62 and 63) Figure 62 shows a pixel configuration

  for the description of the addressing by the generator

  840, which is shown in Fig. 60 (second example). As shown in Fig. 62, the pixels in the horizontal direction on the SCN screen are designated by the column address signal CA, while the pixels in FIG. the vertical direction are designated by

the line address signal RA.

  Also in this example, with a line address signal RA and a column address signal CA, a total of 32 data bits are read in the frame buffer 55 which is shown in FIG. Four pixels can therefore be represented by 32 bits of data Moreover, in the second example shown in FIG. 62, four pixels in the vertical direction (for example PC O PC 3) can be represented by 32 bits of data, such as represented on

Figure 57.

  By way of example, macroblock 860 contains a

  total of 64 pixels, that is to say 8 pixels in the direction

  horizontally and 8 pixels in the vertical direction.

  By way of example, the addressing of the pixel data of the macroblock 860 in the reading is done in the following manner. After the application of a line address RA 4, a column address C A1 is applied. The address generator 840 shown in FIG. 60 successively generates column addresses C A1 to CA 8, starting from Therefore, from a line designated by the line address RA 4, the first half of the data which is designated

  column addresses C Al to CA 8 is read in succession.

  Then, after the application of the line address RA 5, a column address C A1 is applied. Under the effect of the system clock signal 4 fsc, the address generator 840 successively produces the address signals. of column C Al to CA 8 Therefore, the second half

  pixels in the macroblock 860 can be read.

  Fig. 63 is a timing diagram showing the operation of the address generator 840 shown in Fig. 60. To perform the addressing in the manner shown in Fig. 62, the address generator 840 shown in Fig. 60 operates in the manner shown in Fig. 63. Referring to Fig. 63, it is noted that under the effect of the downlink transition of the signal / RAS, the line address signal RA 4 is admitted, and then under the effect of the downward transition of the signal / CAS, the column address signal C A1 is admitted. The address generator 840 (not shown) successively produces column address signals C Al to CA 8, starting from the column address signal C A1 which has been admitted These address signals RA 4 and C A1 to CA 8 are applied to the image interval buffer 55 via

  AB address bus which is shown in Figure 60.

  As a result, in the read operation, the recorded data PD 1, PD 2, are successively transmitted by

  the image interval buffer 55.

  As described above, since the image interval buffer 55 comprises a total of 32 clips, one data bit is read in each of the plurality of picture frames.

  memory cells 801 to 832 Thus, a data element

  PD 1 represented in FIG. 63 corresponds to 32 bits of data. Therefore, it should be noted that with a data element PD 1, it is possible to represent four pixels in the vertical direction on the screen SCN represented on FIG.

Figure 62.

  Then, under the effect of the

  signal, the line address signal RA 5 is admitted, and under the effect of the downward transition of the

  signal / CAS the CAI column address signal is allowed.

  The address generator 804 successively produces AC address signals A1 to CA8 (not shown), starting from the column address signal C A1. Therefore, the data PD 11 to PD 18 which are intended to represent pixels in the second half of the macro-block 860 are read successively. In this way, only two line address signals (i.e. RA 4 and RA 5) and only two column address signals (twice the C A1 signal) are required for the pixels in a macro-block 860, and the time required for addressing can be reduced in comparison with the example which is shown

in Figure 58.

  For example, if 25 ns are needed for

  application of a line address and 200 ns are required.

  For the application of a CA column address and for data transfer, addressing requires

total of 450 ns.

  Another pixel area 862 shown in Fig. 62 represents the area of pixels that is processed in the motion prediction unit. To read pixel data in area 862, a line address signal RA 1 is applied. , and then a column address signal CA 11 is applied. Therefore, from the line designated by the line address RA 1, the pixel data in the first third of the pixel area 862 is read. successively By successively applying line address signals RA 2 and RA 3, it is possible to read the remaining zones in the zone

862 pixels.

  (ii) Third Example (Fig. 64) Fig. 64 is a timing diagram showing another example of the operation of the address generator 840 shown in Fig. 60 Referring to

  Figure 64, we note that in this example, after the admission

  of the line address signal R Ai and the column address signal C A1 under the effect of the system clock signal 4 sc, the column address signal CA (no

  represented) is generated by the address generator 840.

  Thus, two column address signals CA1 and CA2 must be applied to the image slot buffer 55 Therefore, from the line that is designated by the line address RA 1, 32 bits of PD 1 data designated by the column address C Al and 32 bits PD 2 data designated by the column address CA 2 are read. Since the data PD 1 and PD 2 each comprise 32 data bits, 8 pixels in the direction

  horizontal can be represented on the SCN screen.

  (iii) Fourth Example (Figure 65) Figure 65 shows a pixel configuration

  for the description of yet another example of addressing

  by the address generator 840 shown in Fig. 60 Referring to Fig. 65, it is noted that data for the pixels in the horizontal direction on the screen SCN are designated by the line address signal, while data of pixels in the vertical direction are designated by the column address signal. For example, to designate pixel data of macroblock 863, a line address signal RA 4 is applied, and then a Column address signal C Al is applied. The address generator 840 generates column addresses C A1 to CA 8 starting from the column address signal C A1. As a result, the data of the pixels in the left half of the macro-block 863 are read. Then, after the application of the line address signal RA 5, a column address signal C A1 is applied. The address generator 840 generates the signals.

  column address C Al to CA 8 Therefore, the data

  pixels from the right half of macro block 863 are

read.

  In the processing that is performed in the motion prediction unit, a similar addressing is

  accomplished for the pixels in the pixel area 865.

  In this way, by using the image interval buffer 55 which uses SDRAM memories, as shown in the second, third and fourth examples above, the time needed can be reduced.

for addressing.

  (4) Address Generator (Figure 66)

  Figure 66 is a block diagram of the gen-

  address generator 840 shown in FIG.

  Referring to Fig. 66, it is noted that the address generator 840 includes a vertical initial address register 841, an image interval size register 842, a page size register 843, horizontal initial address 844, a horizontal size register 845, registers 846 and 847, a counter

  horizontal 848, an incrementing circuit 849, a cir-

  cured 850, an output control circuit 451, selectors 852 and 853, an

  adder 854 and a selector 855.

  It is assumed that registers 841 and 845 contain

  The initial address which is contained in the register 841 is transmitted in the form of a line address via the selector 852, the adder 854 and the selector 855. On the other hand, the initial address is applied to the registers 846 and 847 via the selector 852 and the adder 854, and is retained in these

registers.

  The horizontal initial address that is retained in the register 844 is applied to the output control circuit 851 for the width control (number of bits), via the incrementing circuit 849. The output control circuit 851 provides a column address that is issued through the

selector 855.

  The incrementing circuit 859 increments a horizontal address that comes from the horizontal initial address register 844 every 8 cycles of the system clock signal 4 sc. When the horizontal address exceeds the page size, the incrementing circuit 949

increments the line address.

  The data of the register 847 and the data "1" are applied to the adder 854, the result of the addition is provided in the form of a line address

  and the result is also applied to register 847.

  When the right end of the trans-

  is detected by the end detection circuit.

  mite 850, the data that is retained in register 846 and the image slot size data is applied to adder 454 via

  selectors 852 and 853 The data indicating the result of

  addition status are issued as a line address by the selector 855, and they are also

  applied to registers 846 and 847.

  Figure 67 shows the correspondence address-

  page, showing the relationship between the row and column addresses that are provided by the address generator 840 shown in FIG. 6, and the pages.

  On the other hand, Figure 86 shows the correspondence page-

  pixels, showing the relationship between the page that is shown in Fig. 67 and the pixels on the screen The image interval buffer 55 that is shown in Fig. 60 records data from the

  which is shown in Figure 67.

  The address generator 840 allocates the data recorded in the image interval buffer 55 in the manner shown in Fig. 68. The address generator 840 shown in Fig. 66 generates the address signal. line RA and the address signal from

  AC column so that the addressing in the manner

  67 and 68 can be performed.

  (5) Projection Method A method of projecting each pixel data of the screen into the image gap buffer will be described in the following. The methods described below can be applied to the buffer memory. picture interval 51 which is shown in the figure

1.

  We will first describe a projection process

  which reduces the number of data transfers.

  Fig. 52 is a first block diagram which illustrates the method of projecting pixel data of the screen

  in the frame interval buffer Referring to

  FIG. 72 shows that a data area 862 having two pixels in the length and width directions is treated as a unit, and a

  the image slot buffer is assigned to it.

  More specifically, in correspondence with an address specified by the line address signal RA and the column address signal CA, data of four pixels which are included in the data area 861 are recorded in the buffer memory of image interval, or by designating the address, the data is read from the memory

  image slot buffer and the data is transferred

  to each of the blocks and from them via the pixel data bus. For example, referring to Fig. 72, it will be noted that when a data area 862 comprises 8 pixels in the horizontal direction and 8 pixels in the vertical direction, which is used for motion vector detection, is transferred, using the data area 861 as a transfer unit, all the pixel data in the data area 862 can be transferred by (horizontal direction) x 5 (vertical direction) = 25 transfer operations Compared with the example of Fig. 58 in which a data area consisting of four pixels in the horizontal direction is used as a transfer unit , the number of transfers can be reduced by two, and the data area 863 that does not

  need to be transferred can be reduced accordingly.

  using the projection method described above.

  above, it is possible to reduce the number of trans-

  ferts, and to transfer image data with a

high speed.

  We will now describe the transfer of an area

  of data comprising 8 pixels in the horizontal direction

  and 8 pixels in the vertical direction, using the projection method described above.

  at 76 are first to fourth illustrations of the trans-

  of the data area with 8 pixels in

  horizontally and 8 pixels vertically.

  When a data area 864 which comprises 8 pixels in the horizontal direction and 8 pixels in the vertical direction is to be transferred, there are four different ways, shown in Figs.

  function of the position of the data area 864.

  In the example shown in Fig. 73, when each pixel data in the data area 864 is to be transferred using a data area that includes two pixels in the horizontal and vertical directions, as a transfer unit. the number of transfers required is 4 (horizontal direction) x 4 (vertical direction) = 16 In the example of FIGS. 74 and 75, the number of transfers required is 20 In

  In the example of Figure 76, 25 transfers are required.

  Therefore, the average number of transfers required to transfer the data area 864 is 20.25 compared with the transfer by the use of four pixels in the horizontal direction, as a transfer unit, which is represented on Figure 58, the number

  transfers can be reduced by about two.

  We will now describe a method of projection

  wherein a data area comprising four pixels in the horizontal direction and two pixels in the vertical direction is considered as a data item and an address is assigned to it. Fig. 77 is a second illustration showing the method of projecting the data of image of the screen in the image gap buffer As shown in Fig. 77, an address of the image gap buffer is applied to the data area 865 comprising four pixels in the horizontal direction and two pixels in the vertical direction, which is considered a

  data element At this point, when a data area

  born 866 with 9 pixels in the horizontal direction

  and 9 pixels in the vertical direction must be trans-

  checked using data area 865 as a unit

  transfer rate, the number of data transfers required

  saires is 3 (horizontal direction) x 5 (vertical direction) = 15 Compared with the example shown

  in Fig. 58, wherein a data area comprises

  8 pixels in the horizontal direction is used as a transfer unit, the number of transfers can be reduced by three, and the 867 area that does not require

  a data transfer can be reduced.

  A first method of projecting a first and a second color difference image into the image gap memory will now be described. FIG. 78 is an illustration of the first method of projecting the first and second pixel data. difference in color in the image gap buffer Here, the first color difference pixel data is called the color difference pixel data Cb which has been converted from RGB format to YUV format, and is called second data. of pixel

  of color difference the pixel data of different

  of Cr color which have been converted in a similar way

  In Fig. 78, the data area 868 comprising four pixels in the horizontal direction is considered as a data item, and an address of the memory

  image slot buffer is assigned to it The first

  873 color difference pixel data and the second color difference pixel data 869 are projected alternatively, four pixels by four pixels in the horizontal direction The first color difference pixel data 873 and the second

  color difference pixel data 869 are mutually

  For example, in motion vector detection, the first and second color difference pixel data 873 and 869 must be processed simultaneously, so that the transfer of

  data is carried out simultaneously Therefore, when

  that the first color difference pixel data area 872 and the second color difference pixel data area 870 are to be transferred as the transfer area, it is necessary to transfer each of the data into the data area 871 In this case, because the first color difference pixel data area 872 and the second data area of

  870 color difference pixels are projected alter-

  natively, the color difference pixel data of the data area 871 can be respectively transferred by an address generation operation, so that the time required for the calculation for the address generation can be reduced, and the data

  image can be processed with high speed.

  a second method of projecting the first and second color difference pixel data into the image gap buffer will now be described. Fig. 79 is an illustration of the second method of projecting the first and second difference pixel data. color in the buffer

  In Fig. 69, a data area

  born 874 with two pixels in the horizontal direction

  tale and two pixels in the vertical direction is treated as a data element and is projected The first color difference pixel data 875 and the second color difference pixel data 879 are projected alternately, two pixels by two pixels in the horizontal direction In this example, when the first color difference pixel data area 878 and the second color difference pixel data area 876 are to be transferred,

  each of the data in data area 877 is trans-

  searched using data area 874 as a unit

  Therefore, it is possible to transfer

  data by a single address generation operation and a smaller number of data transfers. A third method of projecting the first and second color difference pixel data into the frame interval buffer will now be described. Fig. 80 is an illustration of the third method of projecting the first and second color difference pixel data into the frame interval buffer. In the example of Fig. 80, a data area comprising four pixels in the direction horizontal is considered a data element, and an address is assigned to it The first color difference pixel data and the second data of

  color difference pixels are arranged alternately

  Thus, in the data area of four pixels in the horizontal direction, to which an address is assigned, there are two pixels of the first color difference pixel data 880 and two pixels of the second color difference pixel data 881 When the first color difference pixel data area 884 and the second data area

* color difference pixel 882 must be trans-

  you have to transfer each of the data into

  data area 883, by a single operation of general

  At this time, the number of transfers

  would be 5 (horizontal direction) x 9 (vertical direction

  hold) = 45 When the first color difference pixel data and the second color difference pixel data are projected separately into the image gap buffer and are transferred using a data area that includes four pixels

  in the horizontal direction, as a unit of trans-

  in a manner similar to that described above, the number of data transfers required for the first and second color difference pixel data, as shown in FIG. 80, is 54, and therefore with the third projection process

  It is possible to reduce the number of transfers by nine.

  A fourth method for projecting the first and second color difference pixel data into the image gap buffer will now be described. FIG. 81 is an illustration of the fourth method of projecting the first and second difference pixel data. in the image gap buffer As shown in FIG. 81, a data area consisting of four pixels in the horizontal direction and two pixels in the vertical direction is considered a data element, and an address is is assigned for projection into the image gap buffer The first color difference pixel data and the second data

  color difference pixels are projected alternately

  Accordingly, in the data area which is projected as a single data element, there is found the first color difference pixel data 885, comprising two pixels in the horizontal direction and two pixels in the vertical direction, as well as the second color difference pixel data 886, comprising two pixels in the horizontal direction and two pixels in the vertical direction When the first color difference pixel data 889 and the second color data color difference pixel 887 are to be transferred, each of the data in the data area 888 must be transferred using as the transfer unit the data area comprising 4 pixels in the horizontal direction and 2 pixels in the

  vertical direction at this time, since the first

  the color difference pixel data and the second color difference pixel data are alternately arranged, data can be transferred by a single address generation operation, and a rectangular data area is used. as a transfer unit, it is possible to reduce the

number of transfers.

  We will now consider the effects of the first to fourth projection methods of the first and second color difference pixel data in

  the image gap buffer, described above.

  An example of an operation that will be carried out is

  killed in the overall command processor shown

  in Figure 9 in bidirectional prediction coding

  Figure 82 shows the operation that is carried out

  killed in the overall command processor in the

  bidirectional prediction coding.

  Referring to Fig. 82, it is noted that in step 891, in the input image write process, the first address is generated. Address generation is performed for the luminance pixel data. Y, the first difference pixel data

  Cb color and the second pixel data of different

  The data is transferred here from the control unit 2 to the image interval buffer 51 in the data processing apparatus.

  image which is shown in Figure 1.

  At step 892, the second general operation

  This process is accomplished for the luminance pixel data Y, and the data is transferred from the image interval buffer 51

to the control unit 2.

  Then, in step 893, a third address generation operation is performed during the reading for the motion search range. The process is performed here for the luminance pixel data Y, and the data is transferred. from the image interval buffer 51 to the prediction unit

of movement 41.

  Then, in step 894, the coding mode is determined. Next, in step 895, the fourth address generation operation is performed during the

  reading for the image with forward prediction The process

  is accomplished here for three different pixel data.

  Y, Cb and Cr, and the data is transferred from the image interval buffer 51 to the

pixel processing 3.

  At step 869, the fifth operation of general

  address is accomplished during playback for the image with backward prediction The process is performed here on three pixel data Y, Cb and Cr, and

  the data is transferred from the buffer memory

  image range 51 to the pixel processing unit 3.

  The table below shows the result of the comparison between embodiments using the first to fourth projection methods shown in FIGS. 78 to 81, and a comparative example, in relation to the number of operations performed in the processor of FIGS. set command described above In the comparative example, three types of pixel data Y, Cb and Cr

  are projected separately in the inter-

  image value 51, and addresses are generated for each of the pixel data. The reference character C in Table 1 below generally refers to the first and second difference pixel data of each pixel.

color Cb and Cr.

Table 1

  Transfer Content Example cc parative Embodiment Component Number Ccxposante Number of operations of operations write image Y, Cb, Cr 3 Y, C 2 input read image Y 1 Y 1 for the prediction of motion reading Y 1 Y 1 movement search reading image Y, Cb, Cr 3 Y, C 2 for forward prediction of image Y, Cb, Cr 3 Y, C 2 for the backward reading prediction of the image Y, Cb, Cr 3 Y, C 2 to be encoded total 14 As can be seen from the table, the number of address generation operations is reduced by four in Embodiments More precisely, in the address generation process of the comparative example, it is necessary to perform operations on each of the three different types of pixel data Y, Cb and Cr, and to place respective data in the registers of the image data transfer control unit 15 which is shown in FIG. On the other hand, in the embodiment described above, because addresses are collectively generated for the first color difference pixel data Cb and for the second color difference pixel data Cr The total number of operations can be reduced by four and the time required to place the data in the registers can be reduced. In the set control processor, various processes such as code volume control, various determinations related to the coding and other specific operations of the user, must be accomplished Therefore, if the number of operations is increased by these various operations, the reduction of the address calculation that is described above has a significant effect on coding

in real time.

  Although the present invention has been described and illustrated in detail, it is clear that this has been done by way of illustration and example only and should not be construed as limiting, the spirit and the scope of the present invention being limited only by the terms of the

appended claims.

Claims (28)

  An image data processing apparatus, characterized by comprising: control means (11) for controlling pipeline processing of a set of predetermined processes for image data compression and / or decompression image data; and   image processing means (12) for executing a process   above predetermined set of predetermined processes.   mined, under the control of a command signal which is   applied by the control means.   An image data processing apparatus according to claim 1, characterized in that the control means comprises: pipeline processing control means (11) for controlling pipeline processing relating to discrete cosine conversion, quantization and variable length data processing; and the image processing means comprises variable length processing means (12) for executing variable length data processing   dependent on a control signal which is   by the pipeline processing control means.   An image data processing apparatus according to claim 2, characterized in that it further comprises: pixel data recording means (51) for recording pixel data to be compressed; a pixel data bus (PB) for transferring data   pixels that are recorded in the recording media.   very much pixel data; pixel code output means (3) for performing discrete cosine conversion and quantization on the pixel data that is transferred by the pixel data bus, for transmitting a pixel code; and a pixel code bus (CB) for transferring the pixel code that is transmitted by the pixel code output means; wherein the variable length processing means includes variable length coding processing means (12) for performing variable length coding on the pixel code that is transmitted by the pixel code bus and for providing a code to variable length; and the pipeline processing control means controls pipeline processing on the pixel data bus, the pixel code output means, the pixel code bus, and the   variable length coding processing means.   An image data processing apparatus according to claim 2, characterized in that it further comprises: variable length code recording means (51) for recording a compressed variable length code; and a variable length code bus (PB) for transferring the variable length code which is registered in the variable length code register means; in which the treatment means to length   variable include: means of   variable length coding (12) for performing a variable length decoding on the variable length code which is transferred by the variable length code bus, for the transmission of a pixel code; the image data processing apparatus further comprising: a pixel code bus (CB) for transferring the pixel code output from the variable length decode processing means; and pixel data output means (3) for performing reverse quantization and inverse discrete cosine conversion on the pixel code that is transferred by the pixel code bus, to output decompressed pixel data; whereinthe pipeline processing control means controls a pipeline processing relating to the variable length code bus, the variable length decode processing means, the pixel code bus, and the data output means. of pixel.   An image data processing apparatus according to claim 2, characterized in that it further comprises: pixel processing means (3) for   perform discrete cosine conversion and quantum   on the pixel data in a mode of understanding.   data processing, and for performing inverse quantization and inverse discrete cosine conversion on a pixel code in a data decompression mode, wherein: the -a-variable-length processing means further comprises means for processing data; variable length coding / decoding (12) for performing variable length coding on the pixel code in the data compression mode, and for performing variable length decoding on the variable length code in the data decompression mode ; the image data processing apparatus further comprising: a first data bus (PB) for transferring image data and variable length code between the pixel processing means and the coding processing means; variable length decoding; and a second data bus (CB) for transferring the pixel code between the pixel processing means and the variable length coding / decoding processing means; wherein the pipeline processing control means controls a pipeline process for the pixel processing means, the variable length coding / decoding processing means, and   the first and second data buses.   An image data processing apparatus according to claim 5, characterized in that it further comprises: recording means (51) connected to the first data bus for recording pixel data to be compressed and a code to compressed variable length; and input / output image data storage means (81) connected to the first data bus for recording image data received from outside and image data to be transmitted to the first data bus. 'outside. An image data processing apparatus according to claim 5, characterized in that it further comprises: first motion prediction processing means (43) connected to the first data bus for performing a motion prediction in forward direction; and second motion prediction processing means (44) connected to the first data bus for   perform a forward motion prediction.   An image data processing apparatus according to claim 7, characterized in that it further comprises: first image data recording means (52) connected to the first data bus for recording data of image for the prediction of motion in the forward direction; and second image data storing means (53) connected to the first data bus for storing image data for the motion prediction in the backward direction. An image data processing apparatus according to claim 5, characterized by further comprising: motion prediction processing means (46) connected to the first data bus for performing a motion prediction; wherein the pipeline processing control means further comprises motion prediction control means   (13) which are directly connected to the means of   motion prediction to control the function of   tion of these prediction processing means of movement.   An image data processing apparatus according to claim 2, characterized by further comprising: first pixel data storing means (51) for storing pixel data to be compressed; a first pixel data bus (PB) for transferring the pixel data which is recorded in the first pixel data recording means;   image processing means (33) receiving the data   pixel data which is transferred by the first pixel data bus, for extracting reference data for motion prediction, by using the transferred pixel data, and having first and second data ports (Pl P 2 ) to emit the reference data for the motion prediction; a second pixel data bus (LDB) for transferring reference data for motion prediction that is   issued by the second data port of the means of   image; second pixel data recording means (56) for recording the data of   reference for motion prediction that are trans-   taken by the second bus; and motion prediction processing means (47) for executing a motion prediction by using the motion prediction reference data which is recorded in the second pixel data storing means, and which is transferred by the second pixel data bus, for generating a motion vector; wherein the pipeline processing control means comprises means (23) for controlling a pipeline processing relating to the first and second pixel data buses, the pixel processing means, and the means   motion prediction processing.   An image data processing apparatus according to claim 10, characterized in that the pixel processing means comprises first pixel processing means (34) receiving the data   which are transferred by the first data bus.   derived from pixel, for extracting reference data for motion prediction, using the transferred pixel data, and having a third data port   (P 3) to emit the reference data for the prediction   movement and a set of fourth data ports (P 4, P 5) for dividing and transmitting the reference data for motion prediction, said reference data for motion prediction including reference data representing the luminance of the image in motion search; the second pixel data bus comprises a set of third pixel data buses (LDB 1, LDB 2) established in correspondence with the fourth data ports for transferring the reference data for the motion prediction that is issued by the fourth data ports; data ports; the second pixel data recording means   comprise a set of third means of recording   pixel data (56 a, 56 b) established in accordance with   with the fourth data ports, to record   record the reference data for motion prediction that is transferred by the third pixel data buses; the motion prediction processing means comprises a set of first motion prediction processing means (47a, 47b) established in correspondence with the fourth data ports for executing a motion prediction using the reference data for the motion prediction that   are recorded in the third means of recording   of pixel data that are transferred by the   third pixel data buses; and the means of   pipeline processing includes means for controlling a pipeline processing relating to the first pixel data bus, the first pixel processing means, the set of third pixel data buses.   and the set of first means of prediction processing movement.   An image data processing apparatus according to claim 10, characterized in that the pipeline processing control means further comprises a system controller (114) which outputs an output control signal from the third and fourth ports   data processing means of pixels.   13 Image data processing apparatus   according to claim 11, characterized in that   further takes an address bus connected to the set of second pixel data recording means; in which: several fourth quarters are planned; the first pixel processing means (34) for dividing and transmitting the reference data for the   prediction of movement according to a type of   reference data for motion prediction, by the set of fourth data ports (P 4, PS); the set of first motion prediction processing means comprises a set of second motion prediction processing means (47a, 47b) for generating a motion vector in accordance with the type of the reference data for motion prediction; and the pipeline processing control means comprises means (25) for controlling pipeline processing relating to the first pixel data bus, the second pixel processing means, the set of third pixel buses, the address bus. and the set of seconds   motion prediction processing means.   An image data processing apparatus according to claim 10, characterized in that the pixel processing means comprises a set of   first pixel processing means (34a, 34b), receive   providing pixel data that is transferred by the first pixel data bus, for extracting reference data of different types for motion prediction, using the transferred pixel data, and having a third data port for outputting the data; reference data for motion prediction and a fourth data port for transmitting reference data for motion prediction according to the type of reference data for motion prediction; the second pixel data bus comprises a set of third pixel data buses (LDB 1, LDB 2) which are set in correspondence with the first pixel processing means for transferring reference data for motion prediction which are issued by the fourth data port; the second pixel data recording means comprises a set of third pixel data recording means 4eg (56c, 56d) which are set in correspondence with the first pixel processing means for recording the data of reference for the motion prediction that are transferred by the third pixel data bus; the motion prediction processing means comprises a set of first motion prediction processing means (34a, 34b) which are set in correspondence with the first pixel processing means for executing a motion prediction using the data reference frames for motion prediction which are recorded in the third pixel data recording means and which are transferred by the third pixel data bus, to generate a motion vector; and the pipeline processing means comprises means (26) for controlling a pipeline processing relating to the first pixel data bus, a set of first pixel processing means, the set of third pixel data buses, and the set of first means of   motion prediction processing.   Image data processing apparatus   according to claim 12, characterized in that the assembly   third means for recording pixel data record different reference data for   motion prediction, depending on whether the data con-   a luminance component or a component of color difference.   16 Image data processing apparatus   according to claim 13, characterized in that the assembly   third pixel data recording means record different reference data for the motion prediction, depending on whether the data relates to a luminance component or a component of color difference.   17 Image data processing apparatus   according to claim 14, characterized in that the assembly   third means for recording pixel data record different reference data for   motion prediction, depending on whether the data con-   a luminance component or a component of color difference.   An image data processing apparatus according to claim 10, characterized in that the pixel processing means comprises image processing means (313, 314) for performing discrete cosine conversion and / or conversion to cosine   inverse discreteness and quantification and / or quantification   inverse cation for image data compression and / or image data decompression; at least two interface means (318a, 318b) incorporated only for image data; recording means (331-333, 335) for storing data for image data compression and / or decompression of image data which is processed by the image processing means; and a data bus (IPB 2) for transferring data between   the interface means and the recording means.   An image data processing apparatus according to claim 10, characterized in that the pixel processing means comprises image processing means (313, 314) for performing discrete cosine conversion and / or conversion to cosine   inverse discreteness and quantification and / or quantification   inverse cation for image data compression and / or image data decompression; at least two interface means (318a, 318b) incorporated only for image data; recording means (331-333, 335) for storing data for image data compression and / or decompression of image data which is processed by the image processing means; and a set of data buses (IPB 2a, IPB 2b) established in correspondence with the interface means for transferring data between each of the interface means and the recording means.   An image data processing apparatus according to claim 3, characterized in that the pixel data recording means comprises N (n 2 2) memory cell arrays (801-832) for storing pixel data for to define pixels on a screen, these N memory cell arrays transmitting N pixel data respectively recorded in a corresponding one of the N memory cell arrays, under the effect of the application of an address signal of line and a column address signal, the N pixel data   defining a set of pixels arranged in a direction   vertical on the screen; and the pipeline processing control means further comprises address signal generating means responsive to a serial clock signal by serializing column address signals to define pixel data relating to   pixels that are arranged in a horizontal direction tale on the screen.   An image data processing apparatus according to claim 3, characterized in that the pixel data recording means comprises N (n> 2) memory cell arrays (801-832) for storing pixel data. for defining pixels on a screen, these N memory cell arrays transmitting N pixel data respectively stored in a corresponding one of the N memory cell arrays, under the effect of the application of an address signal line and a column address signal, the N pixel data defining a set of pixels arranged in a horizontal direction on the screen; and the pipelinecom processing control means further takes address signal generating means (840) responsive to a serial clock signal by serializing column address signals to define pixel data.   concerning pixels arranged in a vertical direction hold on the screen.   An image data processing apparatus according to claim 2, characterized in that the variable length processing means further comprises recording means (481) for recording a variable length code corresponding to a combination of range and level data, corresponding code length data, and a fixed length code processing indicator; reading means (531, 561, 564, 534) responsive to the applied range data and the applied level data by reading   in the recording means a variable length code   correspondingly, its code length data and a   fixed-length code processing indicator corresponding to   laying; fixed length coding means (527) for performing coding according to a predetermined rule on the applied range data and the data of   level applied, to issue a -code-to fixed length -   corresponding; selection means (530) which responds   sent to the fixed-length code processing indicator which is transmitted by the reading means by selecting either the variable length code or the fixed length code; and code coupling means (505) for successively coupling codes that are transmitted by the selection means.   An image data processing apparatus as claimed in claim 2, characterized in that the variable length processing means further comprises recording means (482) for recording range data and level data corresponding to a data element. variable length code, and a fixed length processing indicator; extraction means (5 05) for extracting a variable length code from a code stream at length   applied variable, including codes with varying lengths   coupled; reading means (502) responsive to the variable length code which is extracted by the extracting means by reading in the recording means   range data, level data and an indica-   corresponding fixed-length processing unit; fixed length decoding means (526) for performing a decoding according to a predetermined rule on the variable length code which is retrieved by the means   extraction and to transmit decoded data corresponding to   ponding; and selection means (530) responsive to the fixed-length processing flag that is issued   by the reading means by selecting either the   range and the level data, ie the decoded data. An image data processing apparatus according to claim 1, characterized in that the control means further comprises control means of   parallel operation (11) for controlling the function   parallel to predetermined processes and the processing   parallel operation of image data for image data compression and / or image data decompression; the image data processing apparatus comprising in   in addition to a set of execution control means (14-   16), each responsive to a control signal which is applied by the parallel operation control means, independently controlling the execution of the predetermined process and the transfer of the image data. An image data processing apparatus according to claim 24, characterized in that   further takes a first data bus (214) for transmitting   data between the operating control means   parallel operation and the set of execution control means; and a second data path (210-213) for   transfer data between each of the means of the   a plurality of execution control means.   An image data processing apparatus according to claim 1, characterized in that it further comprises first recording means (7) for recording table data for conversion; second recording means (51) for recording   image data to be processed; third means of recording   recording (81) for recording image data for viewing; fourth recording means (6) recording converted image data; first access means (17) for accessing the first recording means; second access means (18) for accessing the second recording means; third access means (19) for accessing the third recording means and the fourth access means (20) for accessing the fourth recording means; wherein the control means further comprises access control means (11) for independently controlling the start of an access operation of the   first to fourth means of access.   27 Image data processing apparatus,   characterized in that it comprises: means for recording   tremely (481) for storing a variable length code corresponding to a combination of range and level data, corresponding code length data, and a fixed length code processing indicator; reading means (534, 561) responsive to applied range data and level data applied by reading in the means;   a variable length code corresponding to the   its code length data and a code processing indicator to length; fixed length coding means (527) for encoding according to a predetermined rule on the applied range data and the applied level data to produce a corresponding fixed length code; selecting means (530) responsive to the fixed-length code processing indicator output from the reading means, selecting either the variable length code or the fixed length code; and   code coupling means (505) for successively coupling   codes that are issued by the selection means.   2 & _Image of image data processing,   characterized in that it comprises: means for recording   trest (482) for storing range data and level data corresponding to a variable length code and a fixed length code indicator; extracting means (505) for extracting a variable length code from an applied variable length code stream comprising coupled variable length codes; reading means (502) responsive to the variable length code which is retrieved by the extracting means for reading in the recording means the range data, the level data and the fixed-length processing indicator correspondents; fixed length decoding means (526) for decoding according to a predetermined rule on the variable length code which is retrieved by the means   extraction, to provide corresponding decoded data; and selection means (530) corresponding to the indicator   fixed-length processing method that is output by the reading means, for selecting either the range data and the level data, or the decoded data. An image data processing apparatus, characterized by comprising: first pixel data storing means (51) for storing pixel data to be compressed; a first pixel data bus (PB) for transferring pixel data   which are recorded in the first means of recording   very much pixel data; pixel processing processing means (33) receiving the pixel data that is transferred by the first pixel data bus, for extracting reference data for the motion prediction, using the transferred pixel data, and having first and second data ports (Pi, P 2) for transmitting reference data for motion prediction; a second pixel data bus (LDB) for transferring reference data for motion prediction that is output from the second data port of the pixel processing means; second pixel data recording means (56) for storing the motion prediction reference data which is transferred by the second bus; motion prediction processing means   (47) to execute a motion prediction using   the reference data for the prediction that are-   recorded in the second pixel data recording means, and which are transferred by the second pixel data bus, to generate a motion vector; and pipeline processing control means (23) for controlling a pipeline processing relating to the first and second pixel data buses, the pixel processing means and the   motion prediction processing.   An image data processing apparatus according to claim 29, characterized in that the pipeline processing control means comprises a system control unit (114) for transmitting a control signal of the first and second data ports of the data. pixel processing means.   An image data processing apparatus according to claim 29, characterized in that the pixel processing means comprises first pixel processing means (34) for receiving pixel data transferred by the first data bus. pixel data and extracting reference data for motion prediction using the transferred pixel data, and which includes a third data port (P 3) for outputting the reference data for the motion prediction and a set of fourth data ports (P 4, P 5) for dividing and transmitting reference data for motion prediction; the second pixel data bus comprises a set of third pixel data buses (LDB 1,   LDB 2) which are established in correspondence with the fourth   my data ports for transferring reference data for motion prediction that is transmitted by the fourth data ports; the second pixel data recording means comprises a set of third pixel data recording means (56a, 56b) which are set in correspondence with the fourth data ports, for recording the reference data for the motion prediction that is transferred by the third pixel data bus; the motion prediction processing means comprises a set of first motion prediction processing means (47a, 47b) which are set in correspondence with the fourth data ports, for effecting motion prediction using the reference data. for motion prediction which are recorded in the third pixel data recording means and which are transferred by the third pixel data bus, to generate a motion vector; and the pipeline processing control means comprises means (24) for controlling a pipeline processing relating to the first pixe data bus, the first pixel processing means,   the set of third pixel data buses and the set of first motion prediction processing means. An image data processing apparatus according to claim 31, characterized in that   further takes an address bus connected to the set of second pixel data recording means; wherein the first pixel processing means com-20 takes second pixel processing means (34) to divide and output the reference data for motion prediction in dependence on reference data types for motion prediction. from the set of fourth data ports (P 4, P 5); the set of first motion prediction processing means comprises a set of second motion prediction processing means (47a, 47b) for generating a motion vector dependent on the type of the reference data for the prediction of motion. movement; and the pipeline processing control means comprises means (25) for controlling a   pipeline processing relating to the first pixel data bus, the second pixel processing means, the set of third pixel data buses, the address bus and the set of second motion prediction processing means.   An image data processing apparatus according to claim 29, characterized in that the pixel processing means comprises a set of first pixel processing means (34a, 34b) receiving pixel data which is transferred. by the first pixel data bus, for extracting reference data for motion prediction of different types, utilizing the transferred pixel data, and having a third data port for transmitting the data reference for motion prediction, and a fourth data port for transmitting reference data for motion prediction according to the type of reference data for motion prediction; the second pixel data bus comprises a set of third pixel data buses which are mapped to the first pixel processing means for transferring the motion prediction reference data that is transmitted by the fourth port of data; the second pixel data recording means comprises a set of third pixel data recording means (56c, 56d) which are set in correspondence with the first pixel processing means, for   record reference data for the prediction of.   motion that are transferred by the third pixel data bus; the motion prediction processing means comprises a set of first motion prediction processing means (34a, 34b) which are set in correspondence with the first pixel processing means for motion prediction using the data reference frames for motion prediction which are recorded in the third pixel data recording means and which are transferred by the third pixel data bus; and the pipeline processing control means includes means for controlling pipeline processing relating to the first pixel data bus, the set of first pixel processing means, the set of third pixel data buses, and the set first means of prediction processing of movement.   34 Image data processing apparatus   according to claim 31, characterized in that the assembly   third means for recording pixel data record different reference data for   motion prediction, depending on whether the data con-   a luminance component or a component of color difference.   Image data processing apparatus   according to claim 32, characterized in that the assembly   third means for recording pixel data record different reference data for   motion prediction, depending on whether the data con-   a luminance component or a component of color difference.   36 Image data processing apparatus   according to claim 33, characterized in that the assembly   third means for recording pixel data record different reference data for   motion prediction, depending on whether the data con-   a luminance component or a component of color difference.   An image data processing apparatus according to claim 29, wherein the pixel processing means comprises image processing means (313, 314) for performing discrete cosine conversion and / or cosine conversion. discrete inverse and quantization and / or inverse quantization   for image data compression and / or decompression   image data; at least two interface means (318a, 318b) established only for image data;   recording means (331-333, 335) for recording   tracing data for image data compression and / or image data decompression that is processed by the image processing means; and a data bus (IPB 2) for transferring data between   interface means and the recording means.   An image data processing apparatus according to claim 29, wherein the pixel processing means comprises image processing means (313, 314) for performing discrete cosine conversion and / or conversion. in discrete inverse cosine and quantization and / or inverse quantization   for image data compression and / or decompression   image data; at least two interface means (318a, 318b) established only for image data;   recording means (331-333, 335) for recording   tracing data for image data compression and / or image data decompression that is processed by the image processing means; and a set of data buses (IPB 2a, IPB 2b) established in   correspondence with the interface means, for trans-   data between each of the interface means and the recording means.   39 Image data processing method   to encode a set of defined macroblocks of data   pixels forming an image plane, in a pipeline processing mode, characterized in that it comprises: a first step of performing a conversion   in discrete cosine and quantification on a macro-   data block for generating a pixel code (57); a second step of performing variable length coding on the pixel code generated in the first step to generate a variable length code (59); and a third step of coupling the variable length code that is generated in the second step   to generate a variable length code train.   Image data processing method   to decode a variable length code train comprising   a set of variable length codes defining pixels that form an image plane, in a pipeline processing condition, characterized in that it comprises a first step of extracting the variable length code from the code stream to variable length (632); a second step of performing a variable length decoding of the variable length code that is retrieved in the first step to generate a pixel code; and a third step of performing reverse quantization and reverse discrete cosine conversion on the pixel code generated in the second step to generate a macro data block defining pixels that form the image plane.