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FR2786009B1 - Procede de fabrication d'une carte a puce hybride par impression double face - Google Patents

Procede de fabrication d'une carte a puce hybride par impression double face

Info

Publication number
FR2786009B1
FR2786009B1 FR9814363A FR9814363A FR2786009B1 FR 2786009 B1 FR2786009 B1 FR 2786009B1 FR 9814363 A FR9814363 A FR 9814363A FR 9814363 A FR9814363 A FR 9814363A FR 2786009 B1 FR2786009 B1 FR 2786009B1
Authority
FR
France
Prior art keywords
double
manufacturing
chip card
sided printing
hybrid chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9814363A
Other languages
English (en)
Other versions
FR2786009A1 (fr
Inventor
Olivier Brunet
Jean Christophe Fidalgo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gemplus SA
Original Assignee
Gemplus Card International SA
Gemplus SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus Card International SA, Gemplus SA filed Critical Gemplus Card International SA
Priority to FR9814363A priority Critical patent/FR2786009B1/fr
Priority to AU10516/00A priority patent/AU1051600A/en
Priority to PCT/FR1999/002693 priority patent/WO2000030032A1/fr
Publication of FR2786009A1 publication Critical patent/FR2786009A1/fr
Application granted granted Critical
Publication of FR2786009B1 publication Critical patent/FR2786009B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07766—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card comprising at least a second communication arrangement in addition to a first non-contact communication arrangement
    • G06K19/07769—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card comprising at least a second communication arrangement in addition to a first non-contact communication arrangement the further communication means being a galvanic interface, e.g. hybrid or mixed smart cards having a contact and a non-contact interface
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743—External electrical contacts
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
FR9814363A 1998-11-16 1998-11-16 Procede de fabrication d'une carte a puce hybride par impression double face Expired - Fee Related FR2786009B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR9814363A FR2786009B1 (fr) 1998-11-16 1998-11-16 Procede de fabrication d'une carte a puce hybride par impression double face
AU10516/00A AU1051600A (en) 1998-11-16 1999-11-04 Method for making a hybrid smart card by double face printing
PCT/FR1999/002693 WO2000030032A1 (fr) 1998-11-16 1999-11-04 Procede de fabrication d'une carte a puce hybride par impression double face

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9814363A FR2786009B1 (fr) 1998-11-16 1998-11-16 Procede de fabrication d'une carte a puce hybride par impression double face

Publications (2)

Publication Number Publication Date
FR2786009A1 FR2786009A1 (fr) 2000-05-19
FR2786009B1 true FR2786009B1 (fr) 2001-01-26

Family

ID=9532770

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9814363A Expired - Fee Related FR2786009B1 (fr) 1998-11-16 1998-11-16 Procede de fabrication d'une carte a puce hybride par impression double face

Country Status (3)

Country Link
AU (1) AU1051600A (fr)
FR (1) FR2786009B1 (fr)
WO (1) WO2000030032A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2817373B1 (fr) * 2000-11-30 2003-02-07 D Vito Antoine Orazio Procede de fabrication d'objets portables de type cartes sans contact
DE10139395A1 (de) * 2001-08-10 2003-03-06 Infineon Technologies Ag Kontaktierung von Halbleiterchips in Chipkarten
DE10151941A1 (de) * 2001-10-22 2003-01-02 Infineon Technologies Ag Chipmodul und Chipkarte oder Speicherkarte
FR2880160B1 (fr) * 2004-12-28 2007-03-30 K Sa As Module electronique double face pour carte a puce hybride
DE102005038132B4 (de) 2005-08-11 2008-04-03 Infineon Technologies Ag Chipmodul und Chipkarte
DE102008019571A1 (de) 2008-04-18 2009-10-22 Giesecke & Devrient Gmbh Chipkarte und Verfahren zu deren Herstellung
EP2189928A1 (fr) * 2008-11-21 2010-05-26 Gemalto SA Dispositif à circuit integré muni de différents moyens de connexion
US9196554B2 (en) 2013-10-01 2015-11-24 Infineon Technologies Austria Ag Electronic component, arrangement and method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4105869C2 (de) * 1991-02-25 2000-05-18 Edgar Schneider IC-Karte und Verfahren zu ihrer Herstellung
US5574470A (en) * 1994-09-30 1996-11-12 Palomar Technologies Corporation Radio frequency identification transponder apparatus and method
FR2726106B1 (fr) * 1994-10-21 1996-11-29 Solaic Sa Carte electronique utilisable avec un lecteur de cartes sans contact et un lecteur de cartes a contacts
ATE167319T1 (de) * 1994-11-03 1998-06-15 Fela Holding Ag Basis folie für chip karte
FR2753305B1 (fr) * 1996-09-12 1998-11-06 Schlumberger Ind Sa Procede de fabrication d'un ensemble de modules electroniques pour cartes a memoire sans contact

Also Published As

Publication number Publication date
FR2786009A1 (fr) 2000-05-19
WO2000030032A1 (fr) 2000-05-25
AU1051600A (en) 2000-06-05

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20090731