FR2762172A1 - Signal processing circuit receiving packet data from application side for transfer to serial bus - Google Patents

Abstract

The circuit includes a control device intended to create data used for control purposes and to insert this data between the existing packets. This is in the form of a control packet which is transmitted in the packet stream to the series interface bus (BS). The circuit incorporates two (104a, 104b) memories, and a control device intended to regulate the control data, giving an instruction to write control data into the first memory and to transmit control data when it is necessary to do so. First and second transmission circuits (106, 107) are also incorporated. The second transmission circuit puts back to zero the control data established by the control device when the transmission of the control pack is ended.

Description

 The present invention relates to a signal processing circuit used in a serial digital interface.

In recent years, the 1394 high performance serial bus from IEEE (Institute of Electrical and Electronic
Engineers) has become the standard for performing high-speed data transfers and real-time transfers as a multimedia data transfer interface.

 The types of data transfer of this IEEE 1394 serial interface include asynchronous transfer of requests, requests for acknowledgment of receipt and confirmation of receipt of the associated technique, and isochronous transfer by which the data is transmitted in a single times from a certain node in 125 ps.

 In this way, with an IEEE 1394 serial interface having these two transfer modes, the data is transferred in units representing packets.

 Figures 3A and 3B show the size in bytes of a source packet in isochronous communication.

FIG. 3A represents the size of a packet in the digital video broadcasting method (DVB), while FIG. 3B represents the size of a packet in the digital satellite system (DSS) method, TSD designating the data of the transport current.

 The source packet, in the DVB method, consists of 192 bytes, i.e. 4 bytes of source packet header (SPH) and 188 bytes of transport current specific data (TSD) as shown in the Figure 3A.

 On the contrary, the source packet, in the DSS method, is composed of 144 bytes, i.e. 4 bytes of source packet header (SPH), 10 bytes of additional data (ADO to AD9) and 130 bytes of data specific to the transport current (TSD).

 Additional data is inserted between the header of the source package and the data. It should be noted that in the IEEE 1394 standard, the minimum data unit that can be managed is a quadruplet (4 bytes or 32 bits) so that the transport current data and the additional data must be set so that they can be formed in total of 32-bit units.

 It should be noted that, by default, no additional byte is incorporated.

 FIG. 4 represents an example of correspondence between the original data, when the data is transmitted by isochronous communication according to the IEEE 1394 standard, and the packets actually transmitted.

 As shown in Figure 4, each of the source packets in the upper line of the original data has a source packet header indicated on the left in gray on the second line, comprising 4 bytes, and padding data indicated on the right in grayed out, for adjusting the data length, then it is divided into a predetermined number of data blocks, as shown on the third line.

 It should be noted that, since the unit of data during the transfer of a packet is a quadruplet (4 bytes), the lengths in bytes of the data blocks, of the various headers, etc. are all set to multiples of 4.

 The bottom line represents the packet which includes a synchronous cycle signal represented by a thin line, a cycle start packet represented by a black rectangle, a packet header and a CIP header represented by a grayed out rectangle, and a data block represented by a white rectangle.

 Figure 5 shows the header format of a source packet.

 As shown in Figure 5, a time stamp element is written on 25 bits of the source packet header, as shown on the right, to remove fluctuations when for example MPEG-TS data (MPEG = group of motion picture experts, and TS = transport current) used in digital satellite broadcasts, etc. using the DVB method are transmitted by isochronous communications. The 7 bits on the left are reserved.

 Such a packet header, a common isochronous packet header (CIP) or other data is then added to a predetermined number of data blocks for the production of completed packets.

 Figure 6 shows an example of the basic configuration of a packet used for isochronous communications.

As shown in Figure 6, in an isochronous communications packet, the first quadruplet includes the 1394 header, the second quadruplet includes a header
CRC, the third quadruplet includes a CIP 1 header, the fourth quadruplet includes a CIP 2 header, the fifth quadruplet is a source packet header (SPH), the sixth quadruple and the following represent data regions . The final quadruplet represents CRC data.

 The 1394 header includes, in the hatched region, a "data length" which represents the length of the data, a label, a channel indicating the number of the channel (from 0 to 63) transferred by this packet, a T code representing a processing code and a synchronous code prescribed therein by each application.

 The CRC header is a packet header error detection code.

 The CIP 1 header is formed by a source node identity region (SID) of the number of the transmission node, by a data block dimension region (DBS) indicating the length of the data block, a fraction number (FN) region for the number of divisions of the data in the packet formation, a quadruple fill number (QPC) region indicating the number of quadruplets of the fill data, a source packet header region (SPH) for the flag indicating the existence of the source packet header, and a data block continuity counter (DBC) region of the counter which detects the number of isochronous packets.

 It should be noted that the DBS region indicates the number of quadruplets transferred in an isochronous packet.

 The CIP 2 header includes a floer region for the signal format indicating the type of data to be transferred and a format dependent field region (FDF) used to match the signal format.

 The SPH header includes a time stamp region in which a value obtained by adding a fixed delay value to the packet of the transport stream is established.

 In addition, the CRC data from the last quadruple represents a data field error detection code.

 The signal processing circuit of the IEEE 1394 serial interface for the transmission and reception of packets having the aforementioned structure essentially consists of a physical layer circuit intended to drive the IEEE 1394 serial bus directly and a circuit link layer for controlling data transfer from the physical layer circuit.

 In the isochronous communications system of the IEEE 1394 serial interface as indicated for example in FIG. 7, the circuit 2 of the link layer is connected to an application, that is to say an MPEG transport member 1, while circuit 2 of the link layer and connected to a serial interface bus BS by a circuit 3 with physical layer.

 During the transfer of the data from the IEEE 1394 serial interface, the transmission data and the reception data are kept in a storage device such as a file memory (FIFO) placed in the circuit 2 with link layer. In reality, a queue memory using asynchronous packets and a queue memory using isochronous packets are provided separately.

 As shown in Figure 8, it is sometimes necessary to insert data from a control packet (hereinafter called packet inserted and represented by the second line in Figure 8) between the usual data of the MPEG transport current TSD, represented by the first line. The result is indicated by the bottom line.

 For example, a Program Assignment Table (PAT) for use when an MPEG transport stream is flowing is written. It is then necessary to decide what should be assigned to the particular channel of this transport member or when to select a channel for its transmission.

 In the signal processing circuit of the current IEEE 1394 serial interface, however, no configuration has been made to allow the transmission of an insertion packet used for controlling the aforementioned type between the MPEG source packets in the form of isochronous packets.

 The present invention has been made in view of these circumstances and its object is the production of a signal processing system which allows the insertion of a packet intended to be used for control in a usual transport current which is intended to be transmitted.

 To this end, the invention relates to a signal processing circuit intended to receive the packet data of the transmission current on the application side and to transmit the packet data of the transmission current to a serial interface bus in a cycle of predetermined duration, this circuit having a control device intended to create the data used for the control and to insert the data used for the control between the packets of the transmission current in the form of the control packet and to transmit the latter as a packet of the transmission current to the serial interface bus.

 The invention also relates to a signal processing circuit 2. Signal processing circuit intended to receive the packet data of a transmission current coming from the side of an application and to transmit it to a serial interface bus during a cycle of predetermined duration, the circuit comprising a first memory, a second memory, a control device intended to adjust the control data giving an instruction to write control data to the first memory and to transmit control data when it is necessary to transmit the control data, a first transmission circuit which adds a source packet header, established with data indicating that the control data should not be transmitted, to the received packet data of the current transmission when no control data is established and stores them in the second memory with a predetermined format and which creates an established source packet header with data indicating that a control packet should be transmitted when the control data has been established and stores it in the second memory, and a second transmission circuit which transmits the stored data in the second memory in the form of a transmission current packet to the serial interface bus when data indicating that no control data should be transmitted are established in the header of the source packet stored in the second memory , and which transmits the control data stored in the first memory in the form of a control packet to the serial interface bus when the data indicating the transmission of the control data is established in the header of the source packet stored in the second memory.

 In the signal processing circuit according to the invention, when it is necessary to transmit the control data during the transmission of the transmission current packet from the side of the application, the control data are created by the transmission control and the control data is inserted between the packets of the transmission current of the data packet and transmitted to the serial interface bus in the form of a packet of the transmission current.

 Furthermore, according to the present invention, when it is necessary to transmit the control data during the transmission of the transmission current packets from the Zen side of the application, this control data is written in the first storage device by the controller and control data indicating transmission of this control data are established.

 In this case, when the aforementioned command data has not been established, a source packet header having data indicating that command data should not be transmitted by the first transmission circuit is added to the packet data transmission current and stored in the second storage device with a predetermined format. Then, in the second transmission processing circuit, as the data indicating that no control data should be transmitted are established in the header of the source packet stored in the second storage device, the data stored in the second memory devices are transmitted as a packet of the transmission current to the serial interface bus.

 On the other hand, when the control data has been established, data indicating that a control packet is to be transmitted from the first transmission circuit is established and a source packet header is created and stored in the second memory device.

Then, in the second transmission circuit, as data indicating that the control data must be transmitted are established in the header of the source packet stored in the second storage device, the control data stored in the first storage device storage are transmitted in the form of a command packet to the serial interface bus.

Other characteristics and advantages of the invention will be better understood on reading the description which will follow of exemplary embodiments, made with reference to the appended drawings in which
Figure 1 is a block diagram showing the configuration of a signal processing circuit used for MPEG signals according to the present invention, applied to an IEEE 1394 serial interface
FIG. 2 is a diagram allowing the description of the concrete configuration of a time stamping element
FIGS. 3A and 3B are views indicating the size in bytes of a source packet in an isochronous communication, FIG. 3A representing the dimension of the packet with the DVB method and FIG. 3B the dimension of the packet with the DSS method
FIG. 4 represents an example of correspondence between the original data, when the data are transmitted by isochronous communication of the IEEE 1394 standard, and a packet actually transmitted
Figure 5 shows the format of a source packet header
FIG. 6 represents an example of a fundamental configuration of a packet used for isochronous communications
Figure 7 is a block diagram showing the basic configuration of an isochronous communications system circuit in an IEEE 1394 serial interface; and
FIG. 8 is a schematic view of the case in which it is necessary to insert data from a packet used for control between the data of the transport current of the usual MPEG signals.

 FIG. 1 is a block diagram of the configuration of an embodiment of an MPEG signal processing circuit used according to the invention, applied to an IEEE 1394 serial interface.

 This signal processing circuit consists of a link layer circuit 10, a physical layer circuit 20 and a central processing unit (CPU) 30 used as a host computer. In addition, the reference 40 designates an MPEG transport member.

 The link layer circuit 10 controls the asynchronous transfer and the isochronous transfer and controls the physical layer circuit 20 using the central unit 30.

 More specifically, as shown in FIG. 1, the circuit consists of a link core 101, a host interface circuit 102, an application interface circuit 103, a memory to queue 104 using command packets and ensuring asynchronous communications, comprising a transmission queue memory 104a, a reception queue memory 104b and a queue memory 104c used for the insertion packets, a separator 105 used for the automatic identification, a pre-transmission processing circuit 106 used for isochronous communications, a post-transmission processing circuit 107 used for isochronous communications, a pre-reception processing circuit 108 used for isochronous communications, and a circuit post-reception processing 109 used for isochronous communications, a file memory 110 used for isochronous communications and a configuration register 111.

 In the circuit of FIG. 1, a circuit of the asynchronous communications system is constituted by the circuit of the host interface 102, the queue memory 104a for transmission, the queue memory 104b for receiving asynchronous communications and the link core 101.

 An isochronous communications system circuit is constituted by the application interface circuit 103, the circuit 106 for processing prior to transmission, the circuit 107 for processing after transmission, the circuit 108 for processing prior to reception and the post-reception processing circuit 109, the queue memory 110 and the link core 101.

 The link core 101 is constituted by a transmission circuit of an asynchronous communications packet and an isochronous communications packet, a reception circuit, an interface circuit having the physical layer circuit 20 for direct control of the IEEE 1394 BS serial bus by these packets, a device for resetting the cyclic timer every 125 Ps, a cycle monitor and a CRC correction circuit. Time data, etc.

cyclic timer for example are then transmitted to the processing circuit of the isochronous communications system by the configuration register 111.

 The host interface circuit 102 essentially performs arbitration for writing, reading, etc. of the asynchronous communications packet, the central unit 30 being used as host computer, with the transmission and reception queue memories 104a and 104b, an arbitration for writing the insertion packet using the unit central unit 30 and file memory 104c for insertion packet, and an arbitration for the transmission and reception of the various data using the central unit 30 and the register 111.

 For example, the timestamp delay time established in the SPH source packet header of the isochronous communications packet is established from the central unit 30 in the register 111 using the host interface 102 .

 Furthermore, when it is necessary to insert the data of the insertion packet or of the control packet between the usual data of the MPEG transport current TSD, a logic signal "1" is placed in an IPT part of the configuration register 111.

 The packet intended for asynchronous communications transmitted on the IEEE 1394 BS serial bus is kept in the memory 104a while the packet intended for asynchronous communications transmitted by the IEEE 1394 BS serial bus is kept in the reception memory 104b.

 The control packet data is written to the insert packet memory 104c from the central unit 30.

 The capacity of the memory 104c is for example 188 bytes. Data up to 188 bytes is valid, while data exceeding this capacity is not transmitted.

 When the data to be transmitted comprises less than 188 bytes, data other than the written data is transmitted in the form "1".

 It should be noted that the memory 104c has a width for example of 33 bits. The most significant bit is "1" in the final quadruplet. In addition, when the pulsed read signal from the post-transmission processing circuit 107 described below is received after the transmission of the data having a most significant bit at "1", the command is carried out for the transmission of an "OxFFFFFFFF" signal (all bits are at 1).

 Then, the written data is retained even after transmission. When the data of the same content is transmitted continuously, the transmission is carried out by setting the corresponding IPT part of the register 111 to "1" after confirmation of the change to "0".

The application interface circuit 103 provides the arbitration between the transmission and reception of the MPEG transport current data containing the clock signals and the control signals using the transport member 40.
MPEG, circuit 106 for processing prior to the transmission of isochronous communications and circuit 109 for processing after the reception of isochronous communications.

 The separator 105 analyzes the automatic identification packet transmitted by the serial bus BS and stores it in the register 111.

 The processing circuit 106 prior to transmission confirms the arrangement made in the IPT part of the register 111 and performs a different processing between the case of a "0" and the case of a "1".

 When the IPT part of the register is set to "0", the data of the MPEG transport current coming from the member 40 is received via the circuit 103 of the application interface and the length of the data is adjusted in quadruplet (4 bytes) for isochronous communications according to the IEEE 1394 standard. The delay established in register 111 is used to determine the value of the time stamp. A 4-byte source packet header (SPH) is added and the result is stored in memory 110.

 It should be noted that the time stamp which determines the moment of transmission of the data on the reception side is set when the header of the source packet is added.

The operation is carried out as follows.

 First, the value of the internal cyclic register is kept at the time of reception of the final data of the packet from the MPEG transport member 40.

 Then, the transmission delay established in the register 111 is added to the value of the cyclic register from the central unit 30 via the host interface 102.

 Then the added value is inserted (established) in the source packet header of the received packet as time stamp data.

 Figure 2 is a view for describing the concrete configuration of the time stamp.

 As shown in Figure 2, the time stamp that determines when the data is transmitted from the receiving side indicates the current time by 25 bits.

More specifically, the timestamp includes 25 bits. The least significant 12 bits are assigned to a cycle shift region CO while the most significant 13 bits are assigned to a cycle number region
CC.

 The cyclic shift counts the 125 us from O to 3071 (12b 101111111111) (CLK clock s 24.576 MHz), and the number of cycles counts 1 s from O to 7 999 (13b 1111100111111).

 Thus, in principle, the least significant 12 bits of the timestamp never exceed 3072, while the most significant 13 bits never indicate more than 8000.

In addition, when the IPT part of register 111 is set to "1", the processing circuit 106 prior to transmission creates the source packet header, for example on the posterior flank of the packet space and writes it in queue 110. At this point, as shown in Figure 2, the 29-bit designated for the insert packet mark
IPM is set to "1" to indicate that the source packet header written to this memory 110 should be used as the insert packet. It should be noted that, at the time of creating the usual source packet header in which the IPT register part is set to "0", the IPM bit 29 is always kept at "0".

 Then, the memory queue write pointer is shifted to the start of the next packet.

The magnitude S of the pointer offset is given by the following equation, when the size of the packet is PS
S = (PS - 4) / 4 (quadruplet).

For example, the amplitude S of the pointer offset is equal to 188/4, that is to say 47, in the case of the method
DVB whereas it is 140/4, that is to say 35, in the case of the DSS method.

 Then, the source packet header used for the insert packet is not created until the IPT part of the register has returned to a "0" setting.

 The post-transmission processing circuit 107 reads the data stored in the memory 110, confirms whether the 29 ′ bit designated by the IPM insertion packet mark of the header is at “O” or “1” at each start of the source packet header, and performs a different processing according to the established value.

 When the IPM insert packet mark is "0", the data containing the source packet header stored in memory 110 is read, the header 1394 and the CIP headers 1 and 2 shown on the FIG. 9 are added, and the assembly is transmitted to the transmission circuit of the connecting core 101.

 In addition, the post-transmission processing circuit 107 performs the transmission processing of the insertion packet when the IPM mark is at "1".

 It should be noted that, when the IPM insert packet mark is confirmed, the preceding 7 bits of the source packet header are replaced by the content of the SPH-RSV register of the configuration register 111 and transmitted to the kernel of link 101.

 More specifically, when the IPM insert packet mark is "1", so that the data written to the insert packet memory 104c by the central unit 30 as data after the source packet header be used, the read pulse signals INS-RD are transmitted to the memory 104c with exactly the quantity of data required, the necessary data are read sequentially, and for example the indicated predetermined header is added, and the packet insertion is transmitted to the connecting core 101.

 Furthermore, the post-transmission processing circuit 107 establishes the signal INS-MK in the logic state "1" during the transmission processing of the insertion packet.

This INS-MK signal is actually obtained by memorizing the IPM signal from the header of the source packet. It should be noted that the INS-MK signal is set to 1 even when the header of the source packet of the insert packet is determined to be "late" and is not transmitted.

 The INS-MK signal is used to reset the IPT part of the register to "O". After confirming that the data of this register IPT part has become "O", the central unit 30 recognizes the end of the transmission processing of the insertion packet.

 Then, the post-transmission processing circuit 107 places the INS-MK signal in the "0" state when processing the source packet header of the next isochronous packet.

 The pre-reception processing circuit 108 receives the packet for isochronous communications transmitted by the bus BS via the core 101, analyzes the content of the 1394 header and of the CIP headers 1 and 2, etc.

of the received packet, restores the data and keeps the source packet header and the data in memory 110.

 The post-reception processing circuit 109 reads the time stamping time data from the source packet header kept in the memory liO in the internal register, compares the reading time stamping data (TS) and the duration of the cycle (CT) using the cyclic timer placed in the kernel 101 and, when the cycle time CT has exceeded the TS timestamp data, reads the data other than the source packet header kept in the memory 110 and transmits them by the application interface circuit 103 to the MPEG transport member 40 in the form of data of the MPEG transport current.

 The central unit 30 controls the entire system. In addition, as noted above, it sets the time stamp delay time to a value such that the SPH source packet header of the isochronous communications packet is placed in register 111 through the host interface. 102.

 Furthermore, when it is necessary to insert the data of the insertion packet in the form of a control packet between the TSD data of the usual MPEG transport current, the central unit places a "1" in the IPT part of the register 111 Then, when this IPT part is switched to "O", it is recognized that the insertion packet is finished.

 Next, the operation of transmitting the packet for isochronous communications transmitted by the IEEE 1394 BS serial bus is described.

When a packet for isochronous communications is transmitted to the IEEE 1394 BS bus for example, the timestamp delay intended to be placed in the header of the source packet
SPH of the isochronous communications packet is moved from the central unit 30 to the register 111 via the host interface 102.

Furthermore, at the time of the usual processing, when it is not necessary to insert the data of the insertion packet in the form of a control packet between the data of the usual transport stream MPEG TSD, the part
IPT of register 111 is kept at "0".

 In ordinary transmission processing, the pre-transmission processing circuit 106 receives the MPEG transport data stream under the action of the transport member 40 and the application interface circuit 103 and adjusts the length of the data expressed in quadruplet (4 bytes) for isochronous communications according to the IEEE 1394 standard. At this time, the delay established in register 111 is used, the timestamp value is determined, the source packet header SPH of 4 bytes are added and the result is kept in memory 110.

 In addition, when creating an ordinary source packet header when the register IPT part is "O", the IPM bit 29 of the 29 'bit insert packet is kept at "0".

 In this case, in the processing circuit 107 after the transmission, after reception of the storage information signal by a circuit for controlling access to a queue of the circuit 106, the header 1394 and the headers CIP 1 and 2 are added to the data containing the source packet header kept in the memory 110, the data are transmitted to the transmission circuit of the kernel 101 and they are transmitted by the physical layer circuit 20 to the bus BS in the form of a packet of isochronous communications.

 In this case, when it is necessary to insert the insert packet data in the form of a control packet between the TST data of the usual MPEG transport stream, the control packet is first written by the central processing unit 30 in the insertion packet memory 104c. In addition, a "1" is placed in the register IPT part 111 by the central unit 30.

 Then, in the circuit 106 of processing prior to transmission, when it is confirmed that the IPT part of the register 111 is at "1", the header of the source packet is created on the posterior edge of the packet space and the writing is carried out in the memory 110.

 At this time, the 29 'bit designated for the mark of the IPM insert packet is set to "1" so that the source packet header written in memory 110 is marked for use with the packet. insertion.

 Then, the queue write pointer is shifted to the start of the next packet.

 Then, in the post-transmission processing circuit 107, when the source packet data stored in the memory 110 is read and when it is confirmed that the IPM insert packet mark has been set to "1", the transmission processing of the insert packet is executed.

 When it is confirmed that the mark of the IPM insertion packet is "1", so that the data written in the memory 104c can be used by the central unit 30 in the form of data according to the header of the packet source, the reading pulse signals INS-RD are transmitted to the memory 104c for the exactly necessary quantity of data.

 In this way, the necessary control data is read sequentially, for example, a predetermined header is added, and the data of the insert packet is transmitted to the link kernel 101.

 In addition, in the post-transmission processing circuit 107, the INS-MK signal is set to "1" during the transmission processing of the insertion packet.

 Then, in the post-transmission processing circuit 107, when the transmission of the insertion packet is finished and the header of the source packet of the next isochronous packet is processed, the signal INS-MK is set to "O" .

 Then, in the central unit 30, by confirming that the register part IPT is at "O", it is verified that the transmission processing of the insertion packet is finished.

 As described above, in the embodiment considered, the control packet queue 104c is a memory device for the asynchronous communications system and the control data are freely established from the central unit 30 and the packet command is inserted between the usual MPEG transport currents by the circuit 106 for processing before transmission and the circuit 107 for processing after transmission under the control of the central unit 30, so that the command packet can be transmitted freely in the form of an isochronous packet other than a packet formed by a usual current of transport.

 As indicated above, according to the invention, the packet used for the order can be transmitted in an inserted form between the usual transport currents.

 Of course, various modifications can be made by those skilled in the art to the circuits which have just been described solely by way of nonlimiting example without departing from the scope of the invention.

Claims (3)

 1. Signal processing circuit for receiving the packet data of a transmission current on an application side and for transmitting the packet data of the transmission current to a serial interface bus (BS) during a cycle of predetermined duration, characterized in that it comprises a control device intended to create the data used for the control and to insert this data used for the control between the packets of the transmission current in the form of a control packet and to transmit it in the form of a packet of the transmission current to the serial interface bus (BS).  2. Signal processing circuit intended to receive the packet data of a transmission current coming from the side of an application and to transmit it to a serial interface bus (BS) during a predetermined duration cycle, characterized in that it includes  a first memory (104a),  a second memory (104b),  a control device intended to adjust the control data giving an instruction to write control data to the first memory and to transmit control data when it is necessary to transmit the control data,  a first transmission circuit (106) which adds a source packet header, established with data indicating that the control data should not be transmitted, to the received packet data of the transmission current when no control data n 'is established and stores them in the second memory in a predetermined format and which creates an established source packet header with data indicating that a control packet should be transmitted when the control data has been established and stores them in the second memory, and  a second transmission circuit (107) which transmits the data stored in the second memory in the form of a transmission current packet to the serial interface bus when data indicating that no control data is to be transmitted are established in the header of the source packet stored in the second memory, and which transmits the control data stored in the first memory in the form of a control packet to the serial interface bus when the data indicating the transmission of the control data is established in the header of the source packet kept in the second memory.  3. Signal processing circuit according to claim 2, characterized in that the second transmission circuit resets the control data established by the control device when the transmission of the control packet is completed.