FR2636170B1 - - Google Patents
Info
- Publication number
- FR2636170B1 FR2636170B1 FR8911726A FR8911726A FR2636170B1 FR 2636170 B1 FR2636170 B1 FR 2636170B1 FR 8911726 A FR8911726 A FR 8911726A FR 8911726 A FR8911726 A FR 8911726A FR 2636170 B1 FR2636170 B1 FR 2636170B1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4867—Applying pastes or inks, e.g. screen printing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/481—Insulating layers on insulating parts, with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63222413A JPH0272695A (ja) | 1988-09-07 | 1988-09-07 | 混成集積回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2636170A1 FR2636170A1 (fr) | 1990-03-09 |
FR2636170B1 true FR2636170B1 (fr) | 1995-03-17 |
Family
ID=16781995
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR8911726A Granted FR2636170A1 (fr) | 1988-09-07 | 1989-09-07 | Circuit integre hybride dans lequel une plaque de cuivre est formee directement sur le substrat de ceramique, et son procede de fabrication |
Country Status (4)
Country | Link |
---|---|
US (1) | US5036167A (fr) |
JP (1) | JPH0272695A (fr) |
DE (1) | DE3929789C2 (fr) |
FR (1) | FR2636170A1 (fr) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0480038B1 (fr) * | 1990-04-16 | 1997-07-09 | Denki Kagaku Kogyo Kabushiki Kaisha | Carte a circuits en ceramique |
JPH04221888A (ja) * | 1990-12-21 | 1992-08-12 | Matsushita Electric Ind Co Ltd | セラミック配線基板とその製造方法 |
US5210941A (en) * | 1991-07-19 | 1993-05-18 | Poly Circuits, Inc. | Method for making circuit board having a metal support |
JPH05166969A (ja) * | 1991-10-14 | 1993-07-02 | Fuji Electric Co Ltd | 半導体装置 |
US5242535A (en) * | 1992-09-29 | 1993-09-07 | The Boc Group, Inc. | Method of forming a copper circuit pattern |
US6441313B1 (en) * | 1999-11-23 | 2002-08-27 | Sun Microsystems, Inc. | Printed circuit board employing lossy power distribution network to reduce power plane resonances |
EP1187521A1 (fr) * | 2000-09-09 | 2002-03-13 | AB Mikroelektronik Gesellschaft m.b.H. | Procédé de fabrication d'une plaque de support pour des composants électroniques |
JP2003111486A (ja) * | 2001-09-26 | 2003-04-11 | Kusatsu Electric Co Ltd | 定点停止機能付き電動機 |
DE10227658B4 (de) * | 2002-06-20 | 2012-03-08 | Curamik Electronics Gmbh | Metall-Keramik-Substrat für elektrische Schaltkreise -oder Module, Verfahren zum Herstellen eines solchen Substrates sowie Modul mit einem solchen Substrat |
DE102009047592B4 (de) * | 2009-12-07 | 2019-06-19 | Robert Bosch Gmbh | Verfahren zur Herstellung eines Siliziumzwischenträgers |
WO2018180965A1 (fr) * | 2017-03-30 | 2018-10-04 | 株式会社 東芝 | Substrat de circuit en cuivre-céramique et dispositif à semi-conducteur faisant appel audit substrat |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3549784A (en) * | 1968-02-01 | 1970-12-22 | American Lava Corp | Ceramic-metallic composite substrate |
US3787219A (en) * | 1972-09-22 | 1974-01-22 | Du Pont | CaTiO{11 -CRYSTALLIZABLE GLASS DIELECTRIC COMPOSITIONS |
US4129243A (en) * | 1975-07-30 | 1978-12-12 | General Electric Company | Double side cooled, pressure mounted semiconductor package and process for the manufacture thereof |
JPS6054721B2 (ja) * | 1977-12-15 | 1985-12-02 | 日本電気株式会社 | 絶縁体形成用ペースト組成物 |
EP0074605B1 (fr) * | 1981-09-11 | 1990-08-29 | Kabushiki Kaisha Toshiba | Procédé pour fabriquer un substrat pour circuit multicouches |
FR2556503B1 (fr) * | 1983-12-08 | 1986-12-12 | Eurofarad | Substrat d'interconnexion en alumine pour composant electronique |
US4563383A (en) * | 1984-03-30 | 1986-01-07 | General Electric Company | Direct bond copper ceramic substrate for electronic applications |
JPS61229389A (ja) * | 1985-04-03 | 1986-10-13 | イビデン株式会社 | セラミツク配線板およびその製造方法 |
JPS61236192A (ja) * | 1985-04-12 | 1986-10-21 | 株式会社日立製作所 | セラミツク基板の電極形成方法 |
DE3621667A1 (de) * | 1985-06-29 | 1987-01-08 | Toshiba Kawasaki Kk | Mit einer mehrzahl von dickfilmen beschichtetes substrat, verfahren zu seiner herstellung und dieses enthaltende vorrichtung |
US4725333A (en) * | 1985-12-20 | 1988-02-16 | Olin Corporation | Metal-glass laminate and process for producing same |
US4687540A (en) * | 1985-12-20 | 1987-08-18 | Olin Corporation | Method of manufacturing glass capacitors and resulting product |
US4753694A (en) * | 1986-05-02 | 1988-06-28 | International Business Machines Corporation | Process for forming multilayered ceramic substrate having solid metal conductors |
-
1988
- 1988-09-07 JP JP63222413A patent/JPH0272695A/ja active Pending
-
1989
- 1989-09-06 US US07/402,854 patent/US5036167A/en not_active Expired - Fee Related
- 1989-09-07 DE DE3929789A patent/DE3929789C2/de not_active Expired - Fee Related
- 1989-09-07 FR FR8911726A patent/FR2636170A1/fr active Granted
Also Published As
Publication number | Publication date |
---|---|
DE3929789A1 (de) | 1990-03-29 |
JPH0272695A (ja) | 1990-03-12 |
US5036167A (en) | 1991-07-30 |
FR2636170A1 (fr) | 1990-03-09 |
DE3929789C2 (de) | 1993-12-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |