FR2693288A1 - Integrated circuit memory incorporating test programmes - receives external test and clock signals to initiate automatic test of all memory cells - Google Patents

Abstract

The memory is integrated with addressing circuits (6,7) which allow high speed testing of all memory cells under conditions of elevated temperature simulating ageing. The circuit is supplied with an external clock signal (H) and a test signal (T) which disables the control register and activates the addressing circuits, allowing the full memory map to be accessed. The tests allow failure of individual memory cells under conditions of ageing to be identified. ADVANTAGE - Ageing tests on integrated circuit memory at higher speed and lower cost than existing routines.

Description

MEMORY INCLUDING AN ADDRESSING CIRCUIT
INTERNAL FOR AGING TESTS
The invention relates to a memory and the aging test of this memory.

 The manufacturers of memory circuits must carry out numerous tests in order to qualify these circuits with respect to the various existing manufacturing and quality standards. In particular, accelerated aging makes it possible to determine whether the memory circuits will have at least the specified lifetime in a given environment. Such tests are carried out on samples taken from each manufacturing batch.

 The fragility of memory circuits is mainly due to memory cells. If a memory cell is corrupted, it can have significant current leaks which mask the current carried by a cell placed on the same bit line. Reading a cell on this bit line is no longer reliable. With the aging test, we therefore seek to age memory cells to measure their resistance.

 The aging test of a memory circuit therefore consists in accelerating the alteration of the cells by placing the memory circuit in an oven at high temperature - of the order of 1500C - and by permanently addressing the memory plane by accessing all the cells. successively for a determined period depending on the type of memory and the lifetime to be qualified. In one example, the test lasts 48 to 100 hours. At the end of the test, the state of memory deterioration is checked, by reading each cell and comparing with the result of a reading which will have been carried out before the start of the test.

 The aging test requires expensive equipment. It uses a test bench and memory access cards. A test bench must make it possible to test several circuits at the same time placed in the same oven, for example 20 to 50 circuits. It is always necessary to reduce manufacturing times - including testing - and use the machines to the maximum of their capacity, to reduce manufacturing costs which are always too high.

 However, the memory capacities are constantly increasing the number of signals necessary to address a memory plane is growing rapidly, while the input / output capacities of the test benches are not expandable: when a limit is reached, it is necessary to change of test bench. In addition, the memory access cards controlled by the test bench are placed with them in the ovens: they are therefore very expensive, since they must be able to withstand reliably and repeatedly high temperatures. They are therefore designed with a limited number of inputs / outputs corresponding to the state of the art at the time, to reduce their cost.

 Test benches therefore represent a very heavy burden for manufacturers which directly affects the costs of memory circuits.

 In the invention, an addressing circuit for the aging test integrated in each memory circuit is proposed, which allows an aging test bench to have simple access to the memory with a very reduced connection, independent of the memory capacity.

 In the invention, the test bench makes it possible to test all the memories comprising an addressing circuit for aging according to the invention, whatever the capacity of the memory.

 As claimed, the invention therefore relates to a memory comprising an input register of address signals connected as an output on the address bus of the memory plane. According to the invention, the memory further comprises an addressing circuit for generating addresses on the address bus for the aging test of the memory plane, comprising an input for receiving a test signal (T) and a input to receive a clock signal (H) to activate the addressing circuit and deactivate the address signal input register.

 When a test signal is detected, the output of the address signal input register is set to high impedance and an external clock signal is applied to the address sequence generator. The address generator then delivers address signals on the address bus of the memory plane.

Other characteristics and advantages of the invention are presented in the detailed description which follows, given in an indicative and nonlimiting manner with reference to the appended drawings in which
- Figure 1 shows a test device for
integrated aging according to the invention,
- Figure 2 shows a time diagram of
test signals.

 FIG. 1 shows a memory circuit 1. This memory circuit comprises in a known manner a memory plane 2, an address bus 3 of this memory plane, a decoder 4 of the addresses of the memory plane and an input register 5 address signals. The rest of the memory circuit, such as for example the sense amplifiers or the data input / output registers, is generally represented by a logic circuit 9. The elements of this logic circuit 9 are not used for accessing the memory plan during the aging test, they will not be detailed further.

The input register 5 receives the address bits necessary to address the memory plane 2 on input pins of the memory circuit, in the example MA0-MA8. The input register comprises an output stage 5 ′ connected at output to the address bus 3. This output stage is a 3-state gate circuit. It has a Hîl control input which, when active, allows the output of the stage to be placed on high impedance. This then has the effect of freeing the address bus 3 from the level imposed by the address inputs
MAO-MA8. By default, this HI1 command input is inactive. Address bus 3 arrives at decoder 4.

It is the decoder which allows access to one or more cells of the memory plane. In practice, one generally accesses several cells forming a memory word, for example a word of 8 data bits.

 In a conventional manner, the read access of a word from the memory plane is done in the following way: address signals are presented on the address input pins MA0-MA8. A selection signal of the memory circuit box typically noted CE (chip enable in English literature) is presented, which activates in particular the input registers and the decoder of the memory circuit. The input register 5 activated by this signal CE then transmits the address signals MA0-MA8 on the address bus 3 of the memory plane. The decoder 4 decodes the address signals A0-A8 which are presented to it by the bus and applies the read signals to the cells thus selected.

 According to the invention, the memory circuit comprises an addressing circuit for the aging test. This addressing circuit mainly comprises an address generator 6 connected as an output on the address bus 3 of the memory plane and a level detector 7 on a test command input T of the memory circuit which outputs a signal V test validation.

 The addressing circuit makes it possible to invalidate in test the access in conventional reading which we have just described to validate an access allowing the aging of the memory. The general principle of the invention is to invalidate the output 5 ′ of the input register 5 of the address signals; activate the address generator 6 by means of the validation signal V delivered at the output of the level detector 7; and applying an external clock signal H to a clock input CLK of the address generator. The generator 6 then permanently delivers addresses to the address bus 3 of the memory plane 2.

The external clock signal H is applied to an input of the memory circuit connected to the clock input
CLK of the address generator 6.

Advantageously, and as shown in FIG. 1, provision is made to transmit the external clock signal H on the input of the box selection signal
THIS. Indeed, this logic signal which is generally active on the low level, will thus pass from an active level to a passive level cyclically, which will also cyclically validate or invalidate all the logic circuits of the memory, in particular the decoder 4, the input register 5 and the logic circuit 9. In this way, very harsh operating conditions are imposed which will make it possible to measure the resistance of these logic circuits.

 In this case, the addressing circuit includes a logic switch 8, for switching or not the selection input of the box on the address generator 6. In fact, the latter must not be activated in normal operation of the memory circuit . The logic switch 8 receives as an input the selection signal from the box CE.

As a switching signal, it receives the test validation signal V output from the level detector 7 and outputs the clock signal H which is applied to the clock input CLK of the address generator 6. When the validation signal V is inactive, the logic switch outputs a reference potential, for example zero volts.

 The operation is as follows: when the memory circuit must be tested for aging, it is placed in an oven at high temperature. A test bench BT delivers the power supply signals from the memory circuit, typically Vcc (5 volts) and Vss, a clock signal H and a test signal T. The address generator 6 of the memory is then activated and the input register 5 invalidated. As soon as the test bench BT no longer delivers the external clock signal H or the test command signal T, the generator is no longer activated and there is no longer access to the memory plane. The test is then finished.

 In the example shown in FIG. 1, the clock signal H is applied to the selection input of the memory circuit CE and the test signal T is applied to a test input. When the detector 7 detects an active level of the test signal T on this input, it outputs a validation signal V whose active level invalidates the input register 5 of the address signals, validates the address generator 6 and switches the clock signal H to the clock input CLK of the address generator 6.

 The invalidation of the input register 5 of the address signals consists in disconnecting its output from the address bus, that is to say putting its output in high impedance, by applying a signal in high impedance of its stage Release.

 The validation of the address generator 6 consists in initializing it. The external clock H, which is applied to it via the logic switch 8, enables it to generate addresses on the address bus of the memory plane. A time diagram of the address signals is shown in Figure 2.

 In one example, the validation signal V is active at a high level; the initialization of the address generator 6 is done on a rising edge; and the high impedance signal of the output stage of the input register 5 is active at a high level. Under these conditions, the validation signal V is directly applied to the logic switch 8 and to the address generator 6. For the latter, a circuit for shaping the initialization front can be provided (not shown). Finally, an inverter 9 of the validation signal V is provided, the output of which is connected to the input Hîl for setting the high impedance of the output stage 5 '.

 In the example of FIG. 1, the address generator 6 comprises a counter 11 looped back onto itself and an output stage 12. The counter 11 counts the pulses of the clock H and delivers the counting result on 9 bits B0-B8 and 1 carry bit C. The carry bit C is looped back to the counter reset input, to reset the counter when the counter has counted 29 pulses. Thus, the counter counts indefinitely from 0 to 29-1 and thus cyclically addresses the entire memory plane. The carry bit C and the validation signal V, the rising edge of which is used to initialize the address generator, are therefore advantageously combined in an OR gate circuit 10, the output of which is applied to the reset input. 11.

 The 9 bits B0-B8 of the counter 12 are transmitted via an output stage 12 on the address bus 3 of the memory plane. The output stage 12 is a 3-state gate circuit having an input H12 for setting high impedance.

 When the test is not validated, this stage must be set to high impedance and when the test is validated, this stage must impose on the address bus the logic levels of bits B0-B8. By retaining as a convention that the input H12 for setting high impedance is active in the low state, the validation signal V is applied to this input H12 to obtain the desired function.

 Other realizations are possible. The generator can for example include as many successive clock dividers as address bits to be generated.

Advantageously, the test signal T is applied to an address bit of the memory plane, MA8 in the example. You can choose the test level equal to a high voltage, for example 12 volts. In this case, (shown in dotted lines in FIG. 1), the address bit A8 will not be directly transmitted to the input register 5 of the address signals which is generally in TTL logic. The detector 7 will then preferably be a three-level detector which:
- when it detects a first or a second level
corresponding to the binary logic of the bits
address, switches the address bit MA8 as input
input register 5 and disables its output from
validation V;
- when it detects a third corresponding level
in test mode, it does not switch the address bit
MA8 on input register 5 and activates its output
of validation V.

 Note that it is particularly advantageous to use pins already existing on the memory circuit box. Indeed, it is less expensive to add detectors or logic switches on pins already planned, than to have to add additional pins dedicated to new functions. example of a 20-pin box to a 24-pin box.

The test bench according to the invention is then particularly simplified. Instead of transmitting to each of the memory circuits placed in the oven, the address signals MA0-MA8, the supply voltages Vcc, Vss and the selection signal from the box CE, it is a matter of transmitting only a test signal
T, a clock signal H and the supply voltages
Vcc and Vss. The test bench according to the invention is independent of the memory capacity. The aging test is particularly simplified since the test bench no longer has to generate address sequences to the memory circuits placed in the oven. The addressing circuit according to the invention is produced by logic circuits whose integration is easy. It allows serious savings and a simplification of the test procedure.

Claims (7)

 1. Memory (1) comprising an input register (5) of address signals connected as an output on the address bus (3) of the memory plane (2), characterized in that it also comprises a circuit for generating addresses on the address bus (3) for the memory plane aging test (2), an input for receiving a test signal (T) and an input for receiving a clock signal ( H) enabling the addressing circuit and deactivating the address signal input register.  2. Memory according to claim 1, characterized in that the input for receiving the clock signal (H) is the selection input (CE) of the memory.  3. Memory according to claim 2, characterized in that the addressing circuit further comprises an address generator and a level detector (7), the input of which is connected to the input for receiving a test signal (T) and the output of which delivers a validation signal (V) to control the high impedance of the output (5 ') of the input register (5) of address signals.  4. Memory according to claim 2 or 3, characterized in that the validation signal (V) controls the switching of the clock signal (H) on the address generator (6).  5. Memory according to one of the preceding claims, characterized in that the address generator (6) is a counter (12) looped back on itself in order to carry out the complete addressing cycle of the memory plane indefinitely.  6. Memory according to claim 5, characterized in that the validation signal controls the reset of the counter (12).  7. Memory according to any one of the preceding claims, characterized in that the test input (T) corresponds to an address bit (MA8) and that the level detector (7) is a three-state detector, which on detection of a first (0 volt) or of a second level (5 volts) applies the address bit (A8) to the input register (5) of the address signals and which, on detection of the level test (T), puts the output of the input register (5) of the high impedance address signals and applies the clock signal (H) to the address generator (6).