FR2644027A1 - Device for coding and decoding television pictures, television picture transmission system incorporating such devices, and transmission and reception stages of such a system - Google Patents

Abstract

Device for coding television pictures, characterised in that it comprises a stage 110 for motion estimation and sequential conversion, intended to receive the said original interlaced pictures and to deliver a string of sequential frames Sn and a string of selected displacement vectors DS corresponding to each block of the original images, a circuit 120 for spatial coding intended to receive and code the said sequential frames, a circuit 130 for monitoring the interpolation errors, and a circuit 140 for multiplexing the outputs of the circuits 120, 130 for spatial coding and for monitoring interpolation errors. Application: TV transmission and recording.

Description

"DEVICES FOR CODING AND DECODING TELEVISION IMAGES,
TELEVISION IMAGE TRANSMISSION SYSTEM INCORPORATING
SUCH DEVICES, AND TRANSMISSION AND RECEPTION STAGES
OF SUCH A SYSTEM "Descrivtion
The present invention relates to a television picture coding device, as well as the corresponding decoding device. It also relates to a system incorporating such devices and intended for the transmission of television images via a digital channel with limited bandwidth involving processing to reduce the amount of information to be transmitted. Finally, it relates to the transmission and reception stages of such a system.

 The transmission or recording of television images in digital form requires, if the video signals are transformed as they are after digitization, a bandwidth eight times greater than in analog. Such digital transmission through a narrow band channel implies a very significant reduction in the bit rate necessary for the representation of images.

 The techniques permitting this reduction in bit rate can exploit the correlation present inside each image. US-A-4 394 774 describes such a block coding technique, based on discrete cosine transformation, which exploits this spatial correlation very effectively. However, an additional reduction in bitrate requires taking into account the correlation existing between images, in particular on fixed areas or on moving areas.

 Predictive techniques with aperture compensation are also known, which make it possible to reduce the bit rate to approximately 1 bit per image element (pixel), without annoying degradation of the quality of the decoded images: for example, an image loop to be imaged, that is to say, to transmit a block of each image, on.code is either the block itself, or the difference between this block and a block coming from the previous image coded and decoded . This technique therefore implies that, to decode an image in the receiver, it is necessary to have this coded and decoded previous image.

 This type of coding cannot therefore be used to record sequences of images on a video recorder, one of the essential properties of which is the possibility of rapidly scanning the magnetic tape while viewing images. Indeed, this characteristic. involves the decoding of an image from the data corresponding to this image, and only these, which eliminates any technique calling for any recursion from image to image.

 The object of the invention is to propose a coding device which uses image-to-image redundancy to reduce the bit rate by allowing the realization of the fast search function on a video recorder, that is to say which does not use no picture-to-picture prediction loop.

 The invention relates to this effect a device characterized in that it comprises a motion estimation and sequential conversion stage, intended to receive said original interlaced images and to deliver a series of 5n sequential frames and a series of selected displacement vectors DS corresponding to each block of the original images, a spatial coding circuit, intended to receive and code said sequential frames, a circuit for controlling the interpolation errors, and a circuit for multiplexing the outputs of the circuits of spatial coding and interpolation error checking.

 The structure thus proposed has the advantage of taking into account the image-to-image correction by coding one image out of two of the 625 signal 2, 50 Hz, 1: 1, the missing images being reconstructed in the decoder by interpolation. motion compensated from the previous and next images that were transmitted. Furthermore, the cosine transformation-based coding works in this case on a non-interlaced image, that is to say one which does not contain any inter-frame movement, which limited the efficiency of conventional codings. is therefore compatible with the "fast search with visualization" mode of video recorders, because it makes it possible to decode an image over a working horizon limited to 40 milliseconds, that is to say each image independent of the others, while maintaining a very good decoded image quality.

The features of the invention will now appear in more detail in the following description and in the accompanying drawings, given by way of non-limiting examples and in which
- Figures 1 and 3 show preferred embodiments of the image coding device according to the invention and the decoding device which corresponds to it
- Figure 2 shows a particular embodiment of the motion estimation and sequential conversion stage of the coding device of Figure 1;
FIG. 4 shows a particular embodiment of the spatial decoding and temporal interpolation circuit of the decoding device of FIG. 3.

 In the preferred embodiment shown in FIG. 1, the device according to the invention firstly comprises a stage 110 of motion estimation and sequential conversion. This stage 110 is shown in a particular embodiment in FIG. 2.

Stage 110 receives as input signals 50Hz interlaced images about which the following notations will be adopted
- n is an index designating the number or the rank of an image
I whole, that is, dirt comprising two wefts and occupying
itself 40 milliseconds
- It designates the first frame of such an image, of rank n;
not
- 12 designates the second frame of this n-th image.

not
Stage 110 comprises, as shown in FIG. 2, a motion estimation circuit 210 which receives the following three frames: the current frame I2, the pre frame
n yield I1 of the same image of rank n, the second frame
n I2 of the previous image of rank n-1 Circuits with nI delay 201 and 202, each imposing here a delay of 20 milliseconds, make it possible to appropriately delay the frames II (by 20 milliseconds) and I2 (by 40 milliseconds ) by
n nl compared to 12, so that these three frames are received in
n synchronism by the estimation circuit 210.

The estimation circuit 210 itself comprises a circuit 220 for determining the displacement vector by a method such as that of block correlation. This circuit 220 receives the three frames 12, I1, 12 (synchronized as
nI nn as we have just seen) by means of three circuits 221, 222, 223 of vertical interpolation in the frame, allowing a conversion of interlaced / sequential format, that is to say in the present case to pass from a format from 288 lines to 576 lines. These are the output frames of these three circuits 221 to 223, respectively called pn-12, pn1, pn2, which are sent to the three parallel inputs of the circuit 220 for determining the displacement vector.

 In this circuit 220, a distortion calculation circuit 224 delivers a distortion value DIS (formula (1) given in the appendix) which is supplied to a logic circuit 225 for seeking displacement. In the embodiment described here, the distortion associated with the vector (Vx, Vy) is therefore the sum, on the block considered, of the square of the point-to-point difference between the original frame and the result of the interpolation , motion compensated according to the vector (Vx, Vy) l from the previous and next even frames.

 The circuit 225 has two outputs: one is returned to the distortion calculation circuit 224 and represents the displacement vectors whose distortion DIS must be evaluated by the circuit 224 in the next step, thus allowing a sequential search for the best displacement vector, the other represents the displacement vector actually assigned to each inage block and constitutes the output, denoted DS, of the circuit 220 for determining the displacement vector.

This displacement vector DS is then sent on the one hand to the transmission channel C and on the other hand to a sequential conversion circuit 230. This circuit 230 also receives the frames 12, I1, I2, and determines at
nI nn from its different inputs a sequential frame noted
Sn. This Sm frame is constructed by inserting between each line of the Il (interlaced) frame an intermediate line for
n form an image containing twice as many lines. The determination of this additional line is however different according to the parity of the vertical component DV of the selected displacement vector DS.

Indeed, when the vertical component DV of the displacement corresponds to an odd value, the information present in frames 12 and 12 does not allow improvement
nl n rer the vertical resolution compared to an interpolation in the frame It because the information which would be used
n during the motion compensation would, in this case, already come from a vertical interpolation of the frames 12 and 12.

nl n
If the component DV is for example odd, it is therefore appropriate to determine the image points of the sequential frame Sm by simple interpolation in the frame I1 by using no
n other frame. If on the contrary the component DV is even, the sequential conversion is obtained from the lines 12 and nl 12. More precisely, if the displacement vector DS determined
na for horizontal and vertical components DH and DV, the calculation of each image point, located in column x of line y, of the sequential frame Sn to be determined is provided by the expression (2) given in the appendix.

The sequential conversion circuit 230 therefore comprises, in the first case, for the interpolation from the frame I1 alone, a filter with four coefficients1, 0, 9
n 1, 9, 0, -1, applied to the frame obtained, from the original frame, by inserting between each line a line of zero values. This interpolator filter comprises for this purpose two adders 231 and 232, two multipliers 233 and 234, an adder 235, and a multiplier 236. The adder 231 performs the operation I1Cx, y-2) + I1 (x, y + 2 ), and the
nn multiplier 233 multiplies the result of this addition by -1. The adder 232 performs the operation In1 (x, y-1) + In1 (x, y + 1) and the multiplier 234 multiplies the result of this addition by + 9. The adder 235 adds the outputs of these two multipliers , and the multiplier 236 multiplies the result of this last addition by 1/16.

In the case where DV is even, the sequential conversion circuit 230 this time comprises, in the example described, an adder 237 performing the operation 12 (x-DH, y-DV) + I2fx + DHry + DV), then a multiplier
nI n 238 of the result of this addition by 1/2. The outputs of the multipliers 236 and 238 are sent to a switch 242 which selects one or the other of these outputs according to the parity of the component DV, supplied by a circuit 241 for determining parity receiving the selected displacement vector DS. The output of switch 242 is the sequential frame Sn.

 The sequential frame 5n is then supplied on the one hand to a spatial coding circuit 120 and on the other hand to a circuit 130 for controlling the interpolation errors, which itself also receives the frame 12 and the displacement vector n -1 selected DS.

The circuit 120 is a spatial coding circuit of known type for example such as that described in the patent
US-A-4394774 already cited, and therefore essentially comprises a scan conversion circuit, a circuit for calculating the discrete cosine transform, a quantization circuit, a variable length coding circuit, and a buffer memory circuit ensuring that the outlet flow is properly regulated.

 The circuit 130 for controlling the interpolation errors is intended to check whether the R frames which will be reconstructed by time interpolation on reception will not exhibit excessive errors. This check is carried out for each picture block: if, for a given block, the distortion between the original values I and the interpolated values R exceeds a given limit value (which, in reality, will happen very rarely) , the temporal interpolation on decoding will be inhibited by the sending of an appropriate signal, and additional information, which is in fact coded data resulting from a direct spatial coding identical to that which has just been mentioned, is then transmitted by the channel to allow correct reconstruction of the frames 12 in n-1 the decoding device.

 A multiplexing circuit 140 receives the outputs of circuits 110, 120 and 130, that is to say the outputs which correspond to the information to be transmitted to the decoder to allow the reconstruction of the video signal, and generates the signal to be transmitted, which comprises in series the displacements of the frame 12, (coming from the circuit 110), the information of nl correction of the frame 12 or the additional information n-1 (coming from the circuit 130), and the information resulting from the coding of 5n (coming from the circuit 120). Connection 150 in broken lines concerns only one variant studied below.

 The invention relates not only to a device such as that which has just been described, but also to a system for transmitting television images via a channel with limited bandwidth involving processing to reduce the amount of information. transmitting. Such a system comprises on the one hand a transmission stage including in its coding part a device in accordance with the embodiment which has just been described and on the other hand a reception stage including in its decoding part a device carrying out, by report to said previous device, reverse processing of high definition image restitution. The invention also relates to such transmission and reception stages, respectively comprising a coding device and a decoding device as mentioned.

 FIG. 3 shows a preferred embodiment of the decoding device performing this reverse processing, which first of all comprises a circuit 350 for demultiplexing the information transmitted. This demultiplexing circuit 350 is followed on the one hand by a circuit 360 for spatial decoding and temporal interpolation and on the other hand by a circuit 370 for decoding the interpolation information, and finally by a circuit 380 for regeneration of the interlaced video signal.

The circuit 360 receives from the demultiplexing circuit 350 on the one hand the sequential frames Sn of output of the switch 242 having undergone the spatial coding carried out by the circuit 120, and on the other hand the displacement vector DS selected for each block of images and coded. This stage 360, represented in a particular embodiment in FIG. 4, itself comprises on the one hand a spatial decoding circuit 410, which receives the frames 5n and delivers frames
C1 which are odd frames corresponding to the frames
n odd 11, and on the other hand a circuit 420 for decoding in
n displacement formations, which receives the selected and coded DS displacement vectors and delivers decoded displacement vectors. Like spatial coding, spatial decoding is similarly carried out as indicated for example in patent US-A-4394774 already mentioned.

A motion compensated temporal interpolation circuit 430 receives on the one hand these decoded vectors, on the other hand the output frames C1 of the decoding circuit
n 410, and also the frames C1 previously delivered by nt this circuit 410 and delayed by a delay circuit 440 to be supplied to the circuit 430 in synchronism with the frames
C1. This circuit 430 includes variable delay circuits 431
n and 432, an adder 433, and a divider by two 434.

More precisely, the variable delay circuits 431 and 432, respectively receiving the frames C1 and C1 n ni supply to the adder 433, for each point of the frame
R2 (x, y) to reconstruct the signals C1 respectively
n-1 n (x + DH, y = DV) and Cn-11 (x-DH, y-DV); DH and DV are, as we recall, the horizontal and vertical components of the selected displacement vector DS, which, after transmission, has been decoded by circuit 420 for the block to which the point of spatial coordinates (x, y) belongs. The adder 433, which delivers the signal C1 (x-DH, y-DV) + C1 (x + DH, y + DV), is followed
nor n of a divider 434 of this result by two, which delivers the interpolated frame R2. A circuit 450 for frame recovery nor odd delivers the corresponding transmitted frame R1, with neither a delay expected to compensate for that introduced by the circuit 430. In the case where the temporal interpolation has been judged unsatisfactory by the circuit 130 of the coding device, the decoding circuit 370 replaces the block interpolated by the correction data of the frame I2, which have been coded, neither transmitted nor decoded by the decoding circuit 370.The circuit 380 for regenerating the interlaced video signal receives from the decoding circuit 360 the frame R1 and from the decoding circuit
n 370 the R2 frame and multiplexes this data frame by frame of
n so as to reconstruct an interlaced video signal consisting of the odd frames R1 and the even frames R2.

nn
Of course, the present invention is not limited to the embodiments described above and shown, from which variants can be proposed without departing from the scope of the invention. Such variants may relate more particularly to the processing of the coded data constituting the additional information delivered by the circuit 130 for checking interpolation errors and transmitted, via the multiplexing circuit 140 and the channel, to the decoder to allow a correct reconstruction of the frames.

 In the variant of image coding device shown (in FIG. 1), by means of the additional connection t50 in broken lines, said additional output information of the circuit 130 is provided, for multiplexing, no longer downstream of the spatial coding circuit 120 but upstream, via said connection. This modification simplifies the overall implementation since all of the spatial coding means are now pooled to process either the sequential image, in so-called normal mode, or the original frame associated with the additional information.

Within the framework of the variant thus proposed, the stage of motion estimation and sequential conversion is now represented in FIG. 5. As before, three consecutive frames of the type I2, I1, I2, and which are called
n-1 nn lera here Tan-1, T2n, T2n + 1 according to a quite obvious notation are presented to the delay circuits 201 and 202, unchanged, then, through these, to the movement timation circuit 210. A motion vector DS is then calculated for each image block by this estimation circuit 210 (identical to the previous one), from said frames T2n-1,
T2nr T2n + i. The sequential conversion circuit 230 uses the DS vector as previously to calculate a frame
T'2n whose lines complete the original frame
T2n (interlaced) to form the sequential image Sn transmitted.

 The two images Sn-1 and Snl consisting of the pairs of frames (T2n ~ 2r T'an-2) and (T2n, T12n) which appear successively as indicated above, are then temporally interpolated in the direction of movement to provide a new frame T "2n-1 corresponding spatially and temporally to the original traifle T2n ~ 1 This operation is carried out by a time interpolation circuit 510, at any point similar to the time interpolation circuit 430 of FIG. 4 and receiving the DS vector for delay control.

 An interpolation error control circuit 520 then evaluates the error between the interpolated frame T "2n1 and the original frame T2n-1 and leads to a distortion measurement which constitutes a criterion for selection of transmission mode by Two specific transmission modes are in fact defined per block: an interpolated mode, a non-interpolated mode.

In the first, a block of the image Sn (= T2n + T'2n), of size 8 x 8 for example, is transmitted (that is to say, two sub-blocks belonging to the frames T2n and T '2n respectively). In the second mode, the lines of the block Sn belonging to the frame T'Zn are not transmitted but replaced by the lines of the previous frame Ttn-l corresponding to them spatially. The two sub-blocks belonging to the frames T2n and TZn-1 of different parities naturally overlap (the frames being interleaved) to form a complete block. Each block, consisting in one case as in the other of two sub-blocks, is then spatially coded in a spatial coding circuit 530 of the conventional type, noting however that, for reasons of efficiency, it is preferable to code each of the two sub-blocks separately in the case of the non-interpolated mode where the interframe movement n is not negligible. It will be noted that the second mode is selected only when the quality of the interpolation proves to be insufficient, that is to say when the distortion measured on the sub-block belonging to the frame T2n-1 (as defined above) is too large.

 The selection of the blocks or sub-blocks is carried out by a multiplexing circuit 540, itself controlled by a signal MOD delivered by the interpolation error control circuit 520. A coding circuit 550 ensures the specific coding of the motion vector DS. The information generated by the circuit 530 for spatial coding of the video data and by this circuit 550, as well as the interpolation mode, are then stored, before transmission, in a buffer memory 560, the filling state of which feeds back on the spatial coding parameters, via connection 570, to regulate the rate of information transmitted at the output of this buffer memory. This buffer memory also ensures the multiplexing of the data to be transmitted.

 This variant embodiment of FIG. 5 has various advantages. For example, due to the multiplexing of additional information upstream of the spatial coding circuit, a greater simplicity of implementation is achieved, since the spatial coding members can be pooled to process either the sequential image, in interpolated mode, or the original frame associated with the additional information, in non-interpolated mode. Furthermore, in the variant thus proposed, the amount of additional information required is taken into account during the flow regulation provided by the buffer memory.

 The modifications introduced into the coding device within the framework of this variant lead to corresponding modifications in the decoding device, represented in FIG. 6. In this figure, the transmitted data are first received by a buffer memory 605 ensuring also the demultiplexing of the received data. These data are then processed according to reverse processing to those carried out.

coding. The video signals and the service information (displacement vector DS, interpolation mode MOD) are decoded by the decoding circuits 610 and 620 respectively, via a demultiplexer 630 in the case of the circuit 610, so to deliver C2n-ir C2n frames, and C'2n.

The treatments then differ according to whether the mode is interpolated or not. In the case of the non-interpolated mode, the data relating to the sub-blocks of the frame C'2n which corresponds to the frame T'za have not been transmitted. The sub-block is therefore recalculated by a simple vertical filtering of the coded C2n frame which, .corresponds to the fully transmitted T2n frame, carried out by a filtering circuit 640. The samples corresponding to the image n, that is to say tell the coded frames C2n and C'2n possibly reconstituted, are temporally interpolated to generate a frame C "2ni using a temporal interpolation circuit 650 similar to the circuit 510. In the case of the non-interpolated mode, the subblocks of the C2n ~ frame (T2n-1 coded frame) have been transmitted and therefore replace the sub-blocks of C "2ni previously calculated in the circuit 650. The filtering circuit 640 comprises a switch 670 controlled by the information MOD service to either select the frame directly
C'2n, ie the frame C2n filtered in a vertical filtering circuit 660, and supply the frame thus selected to the circuit 650 for temporal interpolation. A switch 680 finally selects, on command from the service information MOD, either the frame Can-1 or the frame C "2ni of the output of circuit 650, and this selected frame as well as the frame C2n are now available.

It will be noted finally, before transmission, that, when the vertical component of the displacement is odd, the frame T2n is calculated by simple vertical interpolation of
T2n. In this case, in the coding device, the mode of transmission of a block in the image composed of the frames T2n and T'2n can be substituted with an additional mode of transmission of a sub-block belonging to the frame T2n. The amount of information to be transmitted is thus reduced, and the vertical interpolation is carried out at the level of the decoding device, in the circuit 640 of image reconstruction. The transmission of service information relating to this additional mode of transmission is not useful since this mode is indicated by the parity of the vertical component of the motion vector DS which is itself transmitted.

APPENDIX (1) DIS (Vx, Vy) = # [pn1 (x, y)
block
- (pn2 (x + vx, y + vy) + pn-12 (x-vx, y-vy))] 2 (2) Sn (x, y) = [In-12 (x-DH, y-DV ) + In2 (x + DH, y + DV)]

Claims (10)

Claims 1. A device for coding television images, characterized in that it comprises a motion estimation and sequential conversion stage, intended to receive said original interlaced images and to deliver a series of sequential frames Sn and a series of selected displacement vectors corresponding to each block of the original images, a spatial coding circuit, intended to receive and code said sequential frames, a circuit for controlling the interpolation errors, and a circuit for multiplexing the outputs of the spatial coding and interpolation error control circuits. 2. Device according to claim 1, characterized in that the motion estimation and sequential conversion stage comprises two delay circuits for the synchronization of three successive frames, three vertical interpolation circuits, a vector determination circuit displacement by a method such as that of block correlation, and a sequential conversion circuit by intra-frame or inter-frame interpolation depending on whether the vertical component of the determined displacement vector is odd or even. 3. Device according to one of claims 1 and 2, characterized in that the circuit for controlling the interpolation errors comprises means of comparison between the original frames and the non-transmitted frames to be interpolated on reception, and means for replacing, in the event of excessive distortion between these frames, interpolation information with additional direct spatial coding information. 4. Device according to one of claims 1 to 3, characterized in that the spatial coding circuit is of the scanning conversion type, transformation into discrete cosine, quantization, variable length coding, and regulation by buffer memory. 5. Device according to claim 2, characterized in that said successive frames being called T2n ~, T2n, T2n + 1, it also includes a time interpolation circuit, receiving on the one hand the output frame T2n of the first delay circuit and the output frame T '2n of the sequential conversion circuit and on the other hand the displacement vector DS output of the displacement vector determination circuit for delivering a new frame T "2ni corresponding spatially and temporally to said frame T2n-1, taking into account the direction of movement, an error control circuit interpolation, receiving said original frame T2n-l and said new interpolated frame T "2n-l to deliver a signal MOD indicating the transmission mode linked to the quality of the interpolation carried out and intended to control a coding circuit spatial and a multiplexing circuit, said spatial coding circuit, intended to encode the image image blocks or sub-blocks of said multiplexing circuit, said multiplexing circuit, intended to receive the gold frames igine T2nI, T2n and the weft T'2n of output from the sequential conversion circuit for sending to said coding circuit, a coding circuit specific for the displacement vector DS, and a buffer memory for storing the coded frames output from said spatial coding circuit and said vector of coded movement, said buffer memory comprising on the one hand a first output on which the data to be transmitted are present and on the other hand a second output returned via a feedback connection to the spatial coding circuit in order to d 'a regulation of the debit of said data to be transmitted. 6. System for transmitting television images via a channel with limited bandwidth involving processing to reduce the amount of information to be transmitted, comprising on either side of the transmission channel a stage transmission and a reception stage, characterized in that said transmission stage comprises a coding device according to one of claims 1 to 5. 7. Transmission stage for a system for transmitting television images via a channel with limited bandwidth involving processing to reduce the amount of information to be transmitted, characterized in that it comprises a device coding according to one of claims 1 to 5. 8. Television image transmission system according to claim 6, characterized in that the reception stage comprises a decoding device itself comprising a circuit for demultiplexing the information transmitted by the transmission channel, a decoding circuit spatial and temporal interpolation receiving from said demultiplexing circuit the transmitted frames and the service information, a circuit for decoding additional information, and a circuit for regenerating the interlaced video signal. 9. television image transmission system according to claim 8, characterized in that, in the decoding device of the reception stage, the spatial decoding circuit itself comprises a spatial decoding circuit receiving the transmitted frames , a displacement information decoding circuit receiving the selected and coded displacement vectors, a temporal interpolation circuit from, on the one hand, two successively decoded frames supplied one by the spatial decoding circuit and l other by a delay circuit placed at the output of said decoding circuit and, on the other hand, decoded displacement vectors output from said displacement information decoding circuit, and a circuit for recovering the transmitted odd frame, the outputs of this recovery circuit and of the time interpolation circuit being sent to the regeneration circuit of the interleaved vidb signal. 10. Image transmission system according to claim 8, insofar as this depends on claim 5, characterized in that the decoding device comprises a buffer memory (605) for demultiplexing the information transmitted, followed a circuit (610) for spatial decoding of the transmitted frames and a circuit (620) for decoding service information, a demultiplexer (630) delivering frames C2n ~, C2n, C'2n, a circuit (640) for filtering from the frame-C'2n received directly and from the frame C2n received via a vertical filtering circuit (660), and a circuit (650) for temporal interpolation from the frames C2n and C'2n, the frames available at the output of said decoding device being finally on the one hand the C2n frame, on the other hand either the C2n ~ 1r frame or the C "2n-I frame output from said circuit (650) of temporal interpolation, according to the position of a switch (680) controlled by the relative information ve the mode of transmission.  he. Reception stage for a television image transmission system according to one of claims 8 to 10. 12. Decoding device equipping, in a television image transmission system, a reception stage according to claim 11.