FR2643166A1 - MICROPROCESSOR WITH PIPELINE ARCHITECTURE COMPRISING AN INSTRUCTION FOR ACCESSING DATA IN EXTERNAL MEMORY, AND METHOD OF ACCESSING THESE DATA - Google Patents

Abstract

A pipelined architecture microprocessor, comprising a data cache 70 and a processing unit with a data latch 78, and provided with an instruction for accessing data from an external memory through the invention is disclosed. 'intermediary of an external bus 40. According to the invention, this instruction implements memory means 65, to accumulate data; first circuit means, for supplying the memory means with data from the external memory in the event of a cache mismatch occurring; second circuit means, for delivering to the data latch the data accumulated in the memory means, these second circuit means also connecting the data cache to the first circuit means so as to return to the memory means the data residing in the cache, in case of a cache match; and bus control means, connected to the first and second circuit means, to the memory means and to the data cache, for controlling the pipelined flow of data from the external memory to the data latch in the event of cache mismatch, and to control the return of data from the cache memory to the memory means in the event of a cache match.

Description

- 1 2643166

  The present invention relates to the field of micro-

  semiconductor processors, in particular the processes

  sisters of this type who are able to access data

in an external memory.

  More specifically, the present invention relates to a pipeline floating point loading instruction that may be implemented within the bus control unit of a microprocessor. The microprocessor

  used in the case of the present invention is the micro-

  Intel 860T processor, often called NlOTM processor

  (Intel is a registered trademark of Intel Corporation).

  The N10 processor is a 32/64-bit IEEE-compatible flip-flop processor with a number processor

  32-bit RISCs and a three-bit graphics processor

  64-bit. Because it uses a processor

  optimized for both VECTO operations and

  and for scalar operations, it constitutes, in industry, the first integrated vector

  high performance incorporating more than one million

  sistors and providing performance of the order of

  half that of a Cray I, all on one chip.

  All processors have some form of

  truction of loading allowing access to information

  either from an external memory or from an earlier

  internal data memory. Access to externally stored data is usually done via an external data bus controlled by the processor's internal logic. The rationale for a data cache is the ability to get high-performance access to often-used information, which speeds up the speed of processing. In processors that use a data cache, the normal load instructions will act more efficiently if the data information resides in the cache embedded in the chip. In

  other words, if the data is not in the past

  memory, we will be penalized with regard to the perfor-

  when you want to access this data.

  Usually, when reference is made to external data

26 4 3 1 66

  by means of a normal loading instruction, this data is stored in the cache. The reason is that, under normal conditions, it is very likely that the data that has just been referenced is again referenced in a short time. We minimize the penalty related to access to the data by putting in the data cache

  the most frequently accessed information.

  and reserving external memory for information that is rarely referenced or reused. It's the

  localisaticn principle which makes the data cache

  is a useful tool, as programs tend to re-derive some data repeatedly

short delay.

  There is, however, a problem when it is necessary to treat data structures of a very large size in any case, in any case

  data that are much larger than what

  memory of d-nnees would normally contain. As illus-

  Another possibility is the case of a processor which is often asked to perform various floating-point tests, for example, mismatched inversions, multiplications, etc., which

  require the manipulation of huge data matrices.

  In the processors of the prior art, when the data is not in the data memory embedded in the chip, the processor must freeze the execution and request access to the external memory. During the duration of this freezing

  execution, the processor is prevented from delivering a certain

  conque new address to the memory. In other words, the processor must wait for the data necessary for the first operation to arrive from the external memory before continuing the execution of its operations. As a result, this type of access to an external memory can take up to six clock cycles, or even more. This introduces a significant delay, which affects the processing speed of the system when the data structures involved in the processing have frequent access to the external memory. Another problem related to the management of large data structures appears when one brings to the

  processor the data that has been accessed externally.

  When the external data is delivered to the processor, it is cached and generally replaces a

  data that previously resided there. However, we are

  will argue that some external data consists of seldom referenced operations (this case is extremely common with large data structures

  Dimensions), that is to say that we do not envisage

  use, while the data they replaced in ar. znememory were information that was going to be very

  probably be referenced shortly. Thus, the

  The processor eliminates data that must be reused in favor of data which, in all probability, will be referenced only once. As a result, unnecessary time is lost in recalling the cached data that has been substituted. This increased access time is another reason why the processors of the prior art t2 operate at a much lower speed than

allows the present invention.

  As will be seen, the present invention provides a

  pipeline structure that is able to perform operations

  memory at a much higher speed (practically at a speed corresponding to the maximum bandwidth of the bus) without any delay in waiting for the processor

  produce the following address. By using this structure

  pipeline, the processor associated with this invention.

  tion can continue to deliver addresses without having to wait for the arrival of data from the external memory. Compared to the processors of the prior art,

  this possibility provides a definite advantage to the micropro-

cessor that will be described here.

  To achieve this, the present invention provides a pipeline floating point loading instruction for quick access to data stored in external memory. This Pipeline Floating Point Software Instruction, which will be referred to as

2643 166

  c.dit "F-Pielined Floating-point Load" or "i-nstructor." FLD, can be used by a programmer to access stored data in either data cache embedded in the chip scit in an external system memory. The instruction is optimized to hold

  the case where the data does not already exist in the past.

  internal data memory of the processor. This situation will be referred to as a "cache mismatch" or, in another form, as "PFLoad nonconcordance". The opposite case, where the data to be loaded is already stored in the data memory, and which will be called "concordance".

  is managed by the present invention.

  In addition, the PFLoad instruction of the present invention will not replace the data already residing in the cache, but instead will direct the new data to a storage location.

  s: killed in the interest of: 'floating-point unit of the

  cessor. The instruction PFLcad will be described in the context of its implementation ncrmaie in the bus control unit of the processor NO.

  Cn. Will describe below a micropro-

  Specialized caterer optimized for accessing floating-point data stored in an external memory system. The invention uses the pipelined architecture of the microprocessor to efficiently retrieve the external data that will most likely not be reused in a short time, by transferring the data directly to a lock

  floating point data. Frequently referenced data

  encountered, which reside in the cached data incor-

  porée à la puce, will not be disturbed by these operations.

  The pipelined floating-point instruction of the present invention comprises a "first-in-first-out" memory cell, hereinafter referred to as "FIFO memory", for accumulating the data that has been obtained. accessed. First circuit means cooperates with the FIFO to provide the FIF data with the data from the external memory, and second circuit means are provided for transferring the PEPS memory data to the floating point data latch. The second circuit means also provides feedback of the data from the data cache to the FIFO in the case of a match.

  cache (that is, in the case where the referenced data

  encountered actually resides in the data cache).

  Finally, there are provided bus control means, connected

  first and second circuit means for controlling

  the pipeline flow of data from the

  external memory up to the floating-point unit.

  The invention also relates to a method for accessing, in such a processor comprising a processing unit, a data cache and a link to an external memory system, to a data item in this external memory, comprising the following steps : addressing the data in the external memory; writing this data from the external memory into a first-in first-out memory; reading this data, from this first-in-first-out memory, to a bus; and transferring this data on that bus to a data lock located within the storage unit. The present invention thus provides a pipelined instruction which is capable of performing memory operations at a significantly higher rate than in the case of prior art processors. In this way, the present invention makes it possible to continue delivering addresses without having to wait for the actual arrival of the

  data from the external memory.

  The present invention also makes it possible to thus access

  external data without replacing data already

  cached in the cache of data embedded in the chip.

  The present invention thus makes it possible to minimize the total access time, which makes it possible to increase the speed of operation. The present invention also makes it possible to have ur. efficient and fast way to handle arithmetic operations involving data structures of very

dimensonr ..

0

  The present invention will be better understood on reading the detailed description below and the accompanying drawings.

  of the preferred embodiment of the present invention.

  i0 However, this description and these drawings should not

  be considered as limiting the present invention to a particular mode of use, and they are given only

  4v and illustrative purposes.

  FIG. 9 is an exploded logic diagram of the processor associated with the floating point buffer instruction.

pipeline of the present invention.

  Figure 2 shows the currently implemented embodiment of the floating point load instruction

  in pipeline of the present invention.

  2C Figure iustre a series of charging instructions-

  pipelined floating point that were issued for performing a typical operation involving a vectorized memory array in external memory and an internal vector stored in the data cache embedded in

  the chip. The addresses associated with each

  pipelined floating point truction with their associated floating point storage locations. FIG. 4 illustrates a variant of the embodiment

of the present invention.

  Fig. 5A illustrates an embodiment of the pipelined floating-point first-to-first-out memory of the present invention. FIG. 5B illustrates the presently preferred embodiment of first-in-first-out memory

  forming part of the present invention.

  FIG. 6 is a flowchart showing the control operations performed by the bus control logic

  Assigned to the PFLoad instruction of the present invention.

  A microprocessor will be described comprising a pipelined floating point loading instruction

  to load data from an external memory

  dull. In the description that follows, we will give

  many particular details, e.g., bit sizes, etc., to allow a perfect understanding of the present invention. Those skilled in the art will of course understand that these particular details do not need to be necessarily repeated to implement the present invention. Conversely, well-known structures and circuits have not been described in detail

  so as not to unnecessarily burden the description of the

present invention.

  Referring to Figure 1, there is shown a

  exploded diagram of the M10 processor. The M10 processor is logi-

  physically divided into eight separate units.

  The arithmetic unit 35 comprises a floating point adder unit which makes it possible to perform single precision and double precision additions in accordance with the IEEE standard, and a floating point multiplier block, which allows, in the same way, perform single precision and double precision multiplications according to the IEEE standard. Both the adder and the multiplier consist of units that can operate in a three-stage pipeline. In operation, the input operands represented by the symbols "src1" and "src2" are applied to the arithmetic unit 35 through lines 42 and 43, respectively. The mnemonics "srcl" and "src2"

  (as well as the mnemonic "dest") indicate one of the thirty-

  two floating point registers located within the

  M010 processor. The output result of the arith-

  metic 35 appears on the line 49, which is connected to the destination bus 41 to 64 bits. The buses 41 to 43 each have a 64-bit arg and are connected to the floating-point control unit 33. The floating point source operands "srci" and "src2" are also applied to

the graphic unit 34.

  The graphic unit 34 is a 64-bit graphics processor making it possible to carry out at high speed calculations of

  pixels and three-dimensional graphics for various algo-

  and to check the stamp of the pro-

  foundry for the purpose of eliminating hidden surfaces. The graphics processor is able to consolidate the results of several round operations deliver on line 45 a

  result to destination bus 4_.

  Instructionemember 20, also called "unit 1", issues instructions on 32-bit integers and 32-bit floating-point numbers, both at the same time as the control unit. comma

  flcttante 33 on lines 24 and 25, respectively. The an-

  The memory of insru.zti.n is a two-dimensional associative memory

  ret: _onnee of 4 K. bytes, in blocks of 32 bytes. The

  instructions are given to the respective buses by

  memory 2 at each clock cycle. The memory management unit 21 performs the translation of the virtual address into a physical address for access to the data and instructions, performs control of the access violations and compares the physical addresses of the current cycle with those of the cycle. preceding to produce, on the same clock cycle, the nearest signal that follows. The translation is

  carried out by means of a translational translation buffer.

  encoding, which is a 64-input associative cache.

  The memory management unit 21 receives its input data via the buses 32 and 27 of 32 bits, at the output of the core

RSC 31.

  The RISC 3 kernel, also referred to as "runtime kernel" or "E-unit", performs all operations on 32-bit integers, and the loading / storing ones. It's the

  the central controller of the MIv processor. He has a bat-

  three ports, with 32 L_-s registers, a bypass network, a shifter, a

  arithmetic and logic and instruction pointers.

  Execution kernel unit 31 will search both the integer instructions and the floating point instructions. It contains the battery of integer registers and decodes and performs the operations of loading, memorizing, integer processing, processing

  binary and control-transfer values.

  The data cache unit 22 provides data cache and byte alignment functions for

  read / write operations and NI processors.

  change cache data is executed between the year

  data memory 22 and the floating-point control unit 33 via the bus 37. The data cache 22 can also receive external data via the control unit of the data carrier. bus 30 on a bus

at 64 bits 29.

  The bus control unit 30, also referred to as "unit B", is the bus cycle controller that provides the interface between the external bus and the internal chip. It receives bus cycle requests from the unit E, accesses the data cache and the cache.

  training, manages the cases of non-concordance

  memory, with freeze control and replacement of the cache line, checks the translation with the buffer of

  translation by transcoding and tracing of non-con-

  strings and faults, and provides interfacing with the external bus. The pipelined floating point loading instruction which is the subject of the present invention is implemented inside the bus control unit 30 of processor N10. The bus controller has a pipelined architecture that allows for up to three

  bus cycles simultaneously in progress.

  In the architecture of many microprocessors

  modern technologies, pipeline operation is used to

  to increase the speed at which one can introduce or execute operations. The pipeline architecture treats each operation as a series of primitive operations

  (called stages), which can be run in parallel.

  In the processor, the number of stages of the pipeline is reduced from one to three. An operation in DiBeline with a three-stage pipeline stores the result of the operation located three operations behind. A pipeline operation with a two-stage pipeline stores the result

  of the operation located two operations back. An operation

  Pipeline delivery with a one-stage pipeline stores the result of the previous operation. The processor N '! allows to have one. Pipelining operation of the bus cycle on three levels on the external bus, so that one can avcr. trc.s bus cycles that were issued before the

  data corresponding to the first cycle has been returned.

  In addition, the internal path of the addresses in the unit B is organized in a pipeline, so that the translation of the address of the following e is parallel to the cycle.

external bus in progress.

  As mentioned above, or.cn uses the PFLcad instruction to gain access, in external memory, to data that is rarely used, ie data that does not contain any data. reuse at short notice. Therefore, the logic that controls FLoad, which is found inside the control unit of the bus, is optimized to take into account the case of a nonconformance mismatch. A "mismatch of a.nememore" corresponds to the situation in which the data requested by PFLoad is not a resident datum

  already in the data cache unit.

  Figure 2 illustrates a preferred embodiment of

  implementing instruction of the present invention.

  The PFLoad instruction returns data from the external memory on a 64-bit bus 40. The data returned is the data that was sent three instructions back, according to the pipelined operation of processor N! 0. The logical three-state buffer 60 is used to

  apply the external data to the "zero" input of the multi-

  The buffer 60 is connected to the multiplexers 62 and 67 via the line 61. The buffer 60, as well as the control stages 69, 74 and 75, are connected to the multiplexer 62. , consist of stages of 1! classical control in three-state logic. In the same way, in the preferred embodiment, the multiplexers 62 and 67 are formed of conventional logic circuits. The control of the three-state driving stages 60, 69, 74 and 75, as well as the multiplexers 62 and 67, is ensured by the

  control logic of the bus inside the unit.

  B. This control logic has been synthesized by

  from a functional language description to

  high level of the bus control unit. A flow chart of the control operations executed by unit B will be given below. The implementation of the PFLoad instruction also requires a memory 65, hereinafter referred to as "FIFO memory".

  PFLoad "or" FIFO memory ", connected to the output of the multi-

  plexeur 62 by line 63. -The FIFO 65 produces data at its output 66, which is applied to the PFLD input of the multiplexer 67. In the presently preferred embodiment, the PEPS memory 65 has a size of 64. bits, with a depth of three words. PEPS memory PFLoad 65 contains the 64-bit data referenced by

  the previous three PFLoad statements. At the initiative

  processor, or after a reset, the contents of the FIFO are indeterminate. As a result, for the first three PFLoad instructions, these are unusable data or -that will be returned

  (programmers will then have to ignore the return data

  born by the first three PFLoad instructions that will have

been issued).

  The multiplexer 67 has an input for receiving data output from the top of the FIFO memory and another input for receiving data directly from the external memory. The external data is directly applied to the multiplexer 67 via the line 61. The PEPS memory 65 is connected to the multiplexer 67 via the line 66. The output of the multiplexer 67 appears on the line 68, which is connected to the tri-state buffer 69. tri-state bus buffer 69, in turn, is connected to a 64-bit internal bus, designated BiBUS, which has been illustrated in FIG.

  line 29. As its name indicates, this bus is bidirec-

  that is, it can deliver data to the floating-point unit and, as well, return to the

  multiplexer 62 data from the cache.

  The BIBUS bus 29 is connected, via the buffer 75,

  to a bus DABUS 76, which also has a width of 64 bits.

  The DABUS bus 76 connects the floating-point input data latch 78 to the data cache 70. As previously indicated, the BIBUS bus 29 is bidirectional

  to allow, in the case of an earlier match

  memory, the return to the multiplexer 62 data already residing in the data cache 70. The data in the cache are applied by the line 79

  to the BIBUS bus, via the buffer 74.

  1] 5 When the processor N10 needs to access a data, this data can be either in a system

  external memory is inside the data cache.

  born internally. When the data is external to the processor NIO, the instruction PFLoad acts so as to load the data FIFO PFLoad 65 data from the external memory, using the external bus 40 and through the

  multiplexer 62. After three successful PFLoad instructions

  cessives (corresponding to successive stages of the

  memcire PEPS) have been issued, the initial data is pro-

  on the line 66, and then delivered on the BIBUS bus 29. When the PEPS memory is full, each normal PFLoad cycle transfers the data from the top of the PEPS memory to the BIBUS bus 29, and then to the decimal input data latch 78, via the DEABUS bus 76. Thus, each normal PFLoad cycle triggers inside the processor a

corresponding reading cycle.

  When a new data arrives from the external data bus, it is normally directed to the base of the PEPS memory 65. However, if the addressed data already resides in the data cache, there will be a case of

  "PFLoad match" (synonymous with "previous agreement"

  "In the case of a PFLoad match, the Bus B control logic will wait for all current bus cycles to be completed, and then transfer the requested data from the bus. the data cache 70 at the base of the PEPS memory 65 following the data path constituted by the line 79, the buffer 74, the BIBUS bus 29 (connected to the input "1" of the

multiplexer 62) and line 63.

  The controller must wait for all current bus cycles to be completed to transfer the PFLoad match data from the data cache 70 to the base of the

  PEPS 65 memory for two reasons.

  First, there may be a PFLoad cycle in progress. Any attempt to register the PFLoad match data in the PEPS memory before all

  PFLoad cycles in progress have been completed will destroy the or-

  dre data in the FIFO memory.

  Second, the BIBUS bus 29 may already be busy with data that is being transferred to the floating point unit by means of a PFLoad instruction which is three instructions back. This will result in a

  bus conflict if the PFLoad match data from

  caching is immediately transferred to the BIBUS bus. To prevent the occurrence of a bus conflict, the bus control logic of the unit B turns off the buffer 74 for an additional clock cycle before resetting the data in the PEPS memory 65. Unit B waited until all the cycles in progress were

  Completed, the PFLoad match data is placed on the -

  based on FIFO memory, and PFLoad processing runs

in the usual way.

  30.It is possible for the processor to operate at a

  faster than the external bus or the memory.

  For example, if the processor speed is higher than that of the external hardware, the PEPS memory may be empty. The PEPS memory must have a sufficient number

  number of floors to keep the maximum number of addresses

  by the processor, and that it is also compatible

  ble with the pipeline architecture of the processor. Note that this is why the PFLoad instruction

  here described operates dynamically.

  Referring now to FIG. 5B, there is illustrated a PEPS memory PFLoad 65 constituted, in the presently preferred embodiment, by three locks or registers per bit, a read position counter 87 and a A write position counter 86. The read citation counter is connected to the decoder 88 which, in turn, is connected to the 3-to-1 multiplexer 95 by the lines 94 and 93. These lines are connected to the lines. for selecting the multiplexer 95 so that, during a PFLoad operation, the read counter 87 selects the register

  wherein the following PFLoad cycle will read the data.

  The write position counter 86 is connected to the decoder 85 which, in turn, is connected to the registers A, B and C, respectively by the lines 92, 91 and 90. The lines at 92 make it possible to lock in the appropriate register. the data appearing on the line 63. In operation, the write position counter 86 points to the lock in which the next PFLoad cycle will write the returned data. The reading position counter and the counter

  writing position are both composed of

classic curly 0-to-2.

  The reading counter is incremented when the instruction

  PFLoad is in the rewrite step or is in standby, the BIBUS bus is not active and the FIFO PFLoad is not empty. If the PEPS memory is empty, the read counter is incremented, although the data is not effectively locked in the PEPS memory but directly directed to the floating point input data lock. The write counter is incremented when the current external bus cycle is a PFLoad, or when a data PFLoad is being written from the data cache to the base of the PEPS memory in the case a PFLoad match. The two bits of the write position counter are used to produce the FIFO memory write signals that latch

the data in the PEPS memory.

  FIG. 5A shows a FIFO memory in which the data pass in series from the lock 1 to the lock 2, then to the lock 3 before being delivered as output. FIG. 5A shows a variant of the embodiment of the FIFO memory 65. FIG. on line 66. Although the PEPS memory of FIG. 5A makes it possible to preserve the pipelined nature of the PFLoad instructions, it does not have the same flexibility as the PEPS memory shown in FIG. 5B. For example, in the FIFO memory of FIG. 5B, data could be written in the latch 87 in one clock cycle and read in the next cycle without having to traverse the other registers. We can make some

  data in advance, if necessary.

  As previously explained, the N10 processor can

  transmit up to three bus cycles simultaneously in progress.

  If the processor delivers bus cycles at a rate higher than that of the external memory, the FIFO PFLoad may become empty. This implies that the three cycles in progress are PFLoad cycles. If a fourth PFLoad cycle is in the rewrite step and there is no available data to load in the data latch 78, the bus control unit issues a freeze command. When a PFLoad cycle is requested but the PEPS memory is empty, the kernel must be freezed until the PFLoad data is available on the DABUS bus (a PFLoad is in progress when the data from the PEPS memory does not can not be transferred to the data latch 78 because the FIFO PFLoad is empty, the bus BIBUS is busy or there is a mismatch of

  transcoding translation buffer).

  It will be noticed that when the data cache

  performs normal playback, the cache memory unit

  born 70 drives both the DABUS bus 76 and the DBBUS bus 80, so that it becomes impossible to deliver data.

  external to the lock during the same clock cycle.

  However, if a PFLoad instruction is used, the

  data memory 70 is controlled by the logic of the unit B so as to stop the internal circuits of

  cache control (which are connected to the bus DABUS 76).

  By stopping the cache control circuits connected to the DABUS bus 76, data external to the data latch 78 can be delivered without creating a bus contention situation. Once the PFLoad data has become available on the DABUS bus 76, the freeze is terminated. The external data is then controlled by the buffer 75 on the DABUS bus, from the BIBUS bus 29. The data delivered on the BIBUS bus can come either from the PEPS memory 65 or directly, via the line 61, from the external memory system. The multiplexer 67 selects the line 61 as the source of the data only when the PEPS memory 65 is empty. Whether or not the FIFO 65 is empty depends on the speed of the external memory, the frequency with which the programmer transmits

  -5 PFLoad instructions, etc. If the PFLoad sequence is

  broken, then the data will continue to be delivered to

  firing the external memory as long as there will be current PFLoad emitted on the external bus 40. The external data referenced by the previous PFLoad instructions will then accumulate in the PEPS 65 memory until the programmer starts to be issued again

PFLoad instructions.

* If the programmer issues successive PFLoad commands such that the data FIFO 65 becomes empty before any current PFLoad cycle has been completed, the new data arriving on the external data bus 40 will be applied to the line 61 by the multiplexer 67, for direct application to the BIBUS bus 29. Then, the data applied on the BIBUS bus 29 will be sent by the buffer 75 on the DABUS bus 76 so that it can finally be stored in the input data latch The data entry lock is actually part of the floating point unit of the N10 processor (the DBBUS bus is only used when handling 128-bit loads.) Like the PFLoad instruction only operates on 64-bit or 32-bit loads, the DBBUS bus does not directly affect the PFLoad instruction of the

present invention).

  When a cache matching situation

  appears, that is to say when the data requested is ef-

  fectively in the data cache and not in the external memory, then the following happens. First, the current data word must be returned either from

  the PEPS memory PFLoad 65 is the external data bus 40.

  For this purpose, the control logic of the bus control unit deactivates the buffer 75 and the data is returned following the path of the BIBUS bus which leads to the input "1" of the multiplexer 62. The multiplexer 62 , which is also controlled by the bus control unit, then returns the data to the base of the PEPS memory 65, via the

line 63.

  In the case where a number of current PFLoads have been issued, none of which has yet returned data from the external memory, and o a cache match occurs, the sequence of events is different. In this case, the processor can not, in the immediate future, do anything with the data word currently residing in the data cache. The bus control unit must first wait for all previously issued PFLoad instructions to return data from the external memory. The first data word returned is transferred into the data entry lock 78, either of the PEPS memory 65 or directly of the external bus, while the remaining two words are written in the memory PEPS.65. Finally, the data word stored in the data cache 70 is transferred to the PEPS memory 65 as the last word of this FIFO. We will have a penalty

  a significant temporal difference in the case of a concordance

  memory, because the programmer will have to wait until all current PFLoad cycles have been completed before transferring the cache data to FIFO memory. From the preceding explanations, we see that the instruction PFLoad

  is optimized for the case of antecedent mismatch

  rather than for the case of concordance

  memory. In Figure 4, there is shown a variant of the embodiment of the present invention. The circuit of FIG. 4 is identical to that of FIG. 2, except that the line 79, the buffer 74 and the return path of the BIBUS bus leading to the input "1" of the multiplexer 62 have been deleted. Instead, a bus 81 is provided. The bus 81 directly connects the internal buffer 82 of the cache to the "1" input of the multiplexer 62. The first benefit provided by this variant of the embodiment is that the user does not need to wait for the buffer 69 to turn off before entering the data in the memory PEPS 65. Because we have included a bus dedicated to the case of a concordance of ar. In addition, the programmer does not need to wait, before continuing, for any external data from pending PFLoad instructions to be returned. There is also no penalty in terms of additional clock cycles, since the data is delivered directly from the data cache 70 to the PEPS memory 65 when a case occurs.

cache concordance.

  On the other hand, the preferred embodiment of the sheet 2 has the advantage of a smaller silicon area, since only one bus is needed while, in the variant embodiment of FIG. requires

additional bus 81.

  FIG. 6 is a flowchart illustrating the control operations performed by the bus control logic

  associated with the PFLoad instruction of the present invention.

  This flowchart summarizes the description given above of

  the control logic of the bus implemented during

  the execution of the PFLoad instruction. In Figure 6, the

  PFLoad instruction flow chart begins at block 100, which corresponds to a PFLoad request. Once the request is issued,

  bus control logic and unit B must determine

  if the PEPS memory 65 is empty or if the BIBUS bus 29 is busy. This has been illustrated by test 101. If one of these two conditions is true, the bus controller will wait until the condition changes. If there is data present in the PEPS memory and the BIBUS bus is not busy, then the controller proceeds to block 102, where the PEPS memory data is transferred to the decimal data lock. 78. In test 103, the

  bus controller examines whether or not there has been a

  PFLoad, that is to say, in other words, if one has

  had a concordance cache. If the data resides in

  External memory and is not in the data cache 70, the bus controller will then issue a PFLoad bus cycle, as shown in block 104. The processing continues in a normal way until reaching the end of the instruction. . It may also happen that a PFLoad match appears, in which case the bus control logic must examine whether there is a current PFLoad cycle or whether the BIBUS bus is busy or not. This is illustrated in FIG. 6 by the test block 105. If current cycles are in progress, or if the BIBUS bus is busy, the bus control logic must wait until all the bus cycles are completed. currently being completed and that the BIBUS bus is available to transfer the data. When this happens, the data is then transferred from the data cache to the PEPS memory base, as illustrated by block 106. The transfer can take place as described with reference to FIG. line 79, via the buffer 74, to be returned by the BIBUS bus to the input "1" of the multiplexer 62. In the variant embodiment, the data from the data cache 70 passes directly,

  along the line 81, at the input "1" of the multiplexer 62.

  Here again, the operation follows its normal course until

dye the end of the instruction.

  To better understand the operation and benefits

  of the present invention, reference will now be made to

  example of operation given in Figure 3. The example of

  given by the equation of Figure 3 is: k.Vl + V2 -> V2 ok is a given predetermined constant, Vi is one of 1000 vectors with 1000 different elements stored in the external memory and V2 is a vector stored internally in the data cache unit 70. For this particular calculation, the processor must reuse the vector V2 a thousand times (once for each of the different elements of each vector Vi), while the various

  Vi elements are only used once. In use

  reading the PFLoad instruction of the present invention, the processor loads the various elements of the vector V2 into the floating-point register without rewriting the data

  W residing in 'cache' data.

  Figure 3 shows a first instruction PFLoad, referenced

  encountered PF-LD:, de-signed at the address of Vii in order to load the first element of the first vector V: at the floating-point storage location F2. The order PFLD1 needs two clock cycles to start. Without waiting for the data to be returned from the external memory, a second PFLoad instruction, referenced PFLD2, is sent to the address of the vector element V12, which is directed to the floating point storage location F. -. Other PFLoads are started for vector elements V13, V; 4, V: 5, and so on. You can request a new PFLoad command every two clock cycles, because the external bus can transmit

  a new address every two clock cycles.

  When the fourth order PFLoad, i.e. the order PFLD4, is sent, the external memory begins to return the data of the first instruction PFLoad. This returned data corresponds to the PFLoad instruction located

  three instructions backwards, so that the

  The receiver specified by the fourth PFLoad instruction is the F2 register. The arrival of the data for the PFLoad order located three instructions back is illustrated by the dashed lines and the arrows going, diagonally, from

  the floating-point storage location on the

  Pfload. The programmer can continue to specify PFLoad commands every two clock cycles, thus using the full bandwidth capability of the external bus. In practice, there is a total of six latency clock cycles between the time when the programmer specifies the address of the data and the instant that this data is returned. It therefore takes a total of six clock cycles to the memory system to output the data, even if a new bus cycle commences every two clock cycles. This corresponds to a tripling of the speed at which one can

  treat the cycles. Without the pipeline concept, the

  grammor would be forced to emit a new cycle every six clock cycles instead of issuing it both

clock cycles.

  It will be understood that, of course, the description

  above assumes that each PFLoad instruction matches a data cache nonconformance. If this was a normal floating point load with a prior art processor, since the programmer would have attempted to execute a second PFLoad instruction, the bus control unit would have replied that the we had an ongoing access and would have frozen all six clock cycles waiting for the return of the bus loads in

  course. Thus, with a processor of the prior art, the

  grammar can issue new address only every six clock cycles, instead of issuing them both

  clock cycles. The pipeline concept associated with the

  PFLoad truction of the present invention thus enables

  the user to send addresses at a higher rate than

  higher, despite the fact that the data does not reside in the cache embedded in the chip. Thus, it is possible to efficiently process and access data structures of

large dimensions.

  The present invention makes it possible to store the vector V2 on the same chip, while the element Vi is stored in the external memory, so that the user can reference the elements of V1 by means of a PFLoad instruction and reference V2 using a normal load instruction. In a typical microprocessor of art

  without PFLoad instruction, whenever the use of

  In the reference editor V., the data elements are brought into the cache, thereby removing the elements of the vector V2. This produces an additional delay at a time

  next one where one has to load the element of V2.

2O

Claims (22)

  1. A pipelined microprocessor, including a data cache (22,70), a processing unit, and a bus control unit which controls access to an external memory by an external bus (40), and provided with an instruction for pipelining the loading of data in the microprocessor, characterized in that this instruction implements: i0 - first circuit means (30,62,65,67), for storing data in pipeline when it is delivered from the external memory, - bus means (29), connected to the first circuit means, for transferring to a data latch - (78) the -5 dcnnée stored in these first circuit means, and control means (30) for controlling the first circuit means and the data cache so that data can be pipelined from the external memory to the data latch within the microprocessor.   The microprocessor of claim 1, wherein the external data is transferred directly to the lock of   data, without being cached.   The microprocessor of claim 2, wherein said instruction is capable of transmitting to the full bus bandwidth the additional data addresses associated with the external memory when the data to which it is accessed does not   is not in the data cache, thus allowing   if to increase the speed of access to this external memory.   The microprocessor of claim 3, wherein the data cache (70) is connected to the bus means (29) by a buffer (74) such that the cached data is returned to the first circuit means   in case of cache concordance, this buffer is also   controlled by the means of control. 26 43 16-6   The microprocessor of claim 4, wherein the first circuit means comprises: a first multiplexer (62) having an input connected to the external bus (40), another input connected to the bus means (29) and an output, - a first-in-first-out memory (65), with an input and an output, this input being connected to the output of the first multiplexer, and - a second multiplexer (67), with an input (PFLD )   : ^ connected to the memory input of the first input type   another output (DBS) connected to the external bus a (4) and one output: ie, the output of this second multiplexer being connected to the bus means (29) via another buffer, first multiplexer delivering data to first-in-first-out type memory from   the external memory, in the case of non-compliance   cached cache, or data cache; in the case of a cache match, and the second multiplexer delivering the data to the bus means from the first-in-first-type memory   out, or directly from the external bus.   The microprocessor of claim 5, wherein the data cache (70) is connected to the data latch (78) by a data bus (76), said means   forming bus (29) being connected to this data bus by the   third buffer (75), this third buffer and the data cache being controlled by the control means so as to deny the data cache access to the data bus when the bus means   are transferring data to the data lock   in order to avoid bus conflicts.   The microprocessor of claim 6, wherein each of the buffers (69,74,75) is a logical three-state buffer. 8. A pipelined microprocessor, including a data cache (22,70) and a data lock processing unit (78), and provided with an instruction to access data from a external memory via an external bus (40), characterized in that this instruction implements: - memory means (65), for accumulating data, - first circuit means (60,62) , for delivering to the memory means data from the memory   in the event of the occurrence of an earlier mismatch   memory, - second circuit means (67, 69, 74, 75), for outputting to the data latch the data accumulated in the memory means, these second circuit means also connecting   the cache of data to the first circuit means of   to return to the memory means the data residing in the cache, in case of cache concordance, and - bus control means (30), connected to the first and second circuit means, to the memory means and to the data cache, for controlling the pipeline flow of data from the external memory to the data lock in case of cache mismatch, and for controlling the return of the cache data to the memory means; concordance case.   The microprocessor of claim 8, wherein the memory means (65) comprises a memory of the type first in, first out.   The microprocessor of claim 9, wherein the first circuit means comprises a first multiplexer (62) and a first buffer (60), which first buffer connects the external bus (40) to one of the inputs of the first multiplexer. , and this first multiplexer having its other input connected to the second circuit means and its output connected to the first-in-first-type memory out (65).   11. The microprocessor of claim 10, wherein the first buffer (60) connects the external bus (40) to the second circuit means so as to be able to directly transfer the data to the data latch from the external memory when the first type memory first-out is empty.   The microprocessor of claim 11, wherein the second circuit means comprises a second mux-ultiplexer (67) having an input operably connected to receive data from the first-in-first-out memory. output (65), another input connected to the first buffer (60) and an output, the circuit means seccnds further comprising a second buffer (69) coupled to the output of the second multiplexer and a bidirectional bus (29) for outputting data to the data latch (78) and return the data of that data latch to adite other input of the first mutiptlexer The microprocessor of claim 12, wherein   the first-in, first-out memory (65)   gate: - a plurality of registers (A, B, C),   first selection means (85, 86) for selecting   one of the plurality of registers, the one in which the data must be written, and the second selector means (87, 88, 95) for determining, among this plurality of registers, the one in which which one must read the data.   The microprocessor of claim 13, wherein said instruction can issue addresses in   direction of the external memory using the full capacity   bandwidth quoted from the external bus.   A pipeline architecture processor including a data cache (70), a processing unit, and a bus control unit (30) that controls access to an external memory by an external bus (40), and provided with an instruction for pipelining the loading of data in the microprocessor, characterized in that this instruction implements: a first buffer (60), connected to the external bus, for delivering data to the processor; from the external memory, - first circuit means (30; 62,65,67), for memorizing data in pipeline when delivered from the external memory by this buffer, - a first bus (29; ), connected to the first circuit means, for transferring to a data latch (78) the data stored in these first circuit means, and - control means (30), for controlling said buffer Dremier, the first circuit means and the man data cache to be able to pipeload the data from the external memory to the data lock   located inside the microprocessor.   The processor of claim 15, further comprising a second bus (81) connecting the data cache (70) to the first circuit means so that the   cached data is returned to the first   circuits in the event of the occurrence of a concordance cache dance.   The processor of claim 16, wherein the first circuit means comprises: - a first multiplexer (62), having an input connected to said first buffer (60), another input connected to said second bus (81) and an output a first-in-first-out memory (65), with an input connected to the output of the first multiplexer and an output, and a second multiplexer (67), with an input (PFLD)   connected to the memory output of the first input type   first-out, -another entry (DBS) connected to said first   buffer (60) and an output, this output of the second multi-   clexeur being connected to said first bus (29) via   of a third buffer (69), e first multiplexer delivering data to first-in-first-out memory from   external memory, in the case of non-concordance   cache memory, either data cache, in the case of cache concordance, and the second multiplexer delivering the data to said first bus C from the first-in-first-out type memory, or directly since said first buffer when this first-in-first-out memory is empty.   18. A method for accessing, in a processor comprising a processing unit, a data cache (70) and a link to an external memory system, to a data item located in this external memory, characterized in that it comprises the following steps: (a) addressing the data in the external memory, (b) writing this data, from the external memory, to a memory of the first-in-first-out type (65), (c) reading this given from this first-in-first-out memory to a bus (29), and (d) transferring this data on that bus to a lock   (78) located within the processing unit.   ment. 19. The method of claim 18, wherein the   Steps (a) to (d) are executed in pipeline.   20. The method of claim 19, comprising in   in addition to the step of returning the data from the   memory (70) to the memory of the first input type   first out (65) if a cache match occurs. 264316-6   The method of claim 20, further comprising the step of directly transferring data from the external memory to the data latch (78) when the memory of the type   first-in, first-out porridge (65) is empty.   22. The method of claim 20, further comprising the step of waiting for completion of the cycles.   current bus before returning the data from the previous   memory (70) to the memory of the first input type   first-out (65), in the event of a cache match occurring. 5